Semiconductor test structure and test method

Abstract

The invention discloses a semiconductor test structure and a test method. The structure comprises a substrate; the semiconductor device comprises a substrate and a plurality of MOS devices located on the substrate, each MOS device comprises a grid electrode, a source region and a drain region, the source regions and the drain regions are located in the substrate between the grid electrodes respectively, the grid electrodes, the drain regions and the source regions are arranged in the first direction, each drain region is located between the adjacent source regions, the source regions are electrically connected with one another, and the source regions are electrically connected with one another. The plurality of drain regions are electrically connected with one another; the first source leading-out end and the second source leading-out end are electrically connected with the plurality of source regions respectively; the first drain leading-out terminal and the second drain leading-out terminal are electrically connected with the plurality of drain regions respectively; according to the test structure, the obtained conduction resistance value of the test structure is closer to a real resistance value, so that the accuracy of the obtained conduction current value is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor testing structure and a testing method. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, MOS for short) is a commonly used semiconductor device, widely used in switching, amplification, modulation and other functions in electronic circuits.

[0003] In the design of some chips, customers often use a multi-finger structure to save area. Compared with a single MOS tube, using multiple MOS tubes in the multi-finger structure in parallel can improve the current carrying capacity.

[0004] However, when testing the on-current of a multi-finger structure, the test results obtained by the existing test methods are often lower than the actual value, making it difficult to make a correct evaluation of the performance of MOS products. Therefore, the existing test methods for the on-current of MOS devices need to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor test structure and a test method to improve the accuracy of on-current test results.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor test structure, including: a substrate; a plurality of MOS devices located on the substrate, each of the MOS devices including a gate, a source region and a drain region, the source region and the drain region are respectively located in the substrate between the gates, the plurality of gates, the plurality of drain regions and the plurality of source regions are arranged along a first direction, and each drain region is located between adjacent source regions, the plurality of source regions are electrically connected to each other, and the plurality of drain regions are electrically connected to each other; a first source lead-in terminal and a second source lead-in terminal respectively electrically connected to the plurality of source regions; a first drain lead-in terminal and a second drain lead-in terminal respectively electrically connected to the plurality of drain regions; and a gate lead-in terminal electrically connected to the plurality of gates.

[0007] Optionally, the test structure further includes: a substrate lead-out region located in the substrate; and a substrate lead-out terminal electrically connected to the substrate lead-out region.

[0008] Optionally, the test structure also includes: a first interconnection layer, a number of the source regions are electrically connected to each other through the first interconnection layer, and the first source lead-out terminal and the second source lead-out terminal are electrically connected to the number of source regions respectively; a second interconnection layer, a number of the drain regions are electrically connected to each other through the second interconnection layer, and the first drain lead-out terminal and the second drain lead-out terminal are electrically connected to the drain regions respectively; a third interconnection layer, the third interconnection layer connects a number of the gates, and the gate lead-out terminal is electrically connected to the gates; a fourth interconnection layer, the fourth interconnection layer connects the substrate lead-out layer, and the substrate lead-out terminal is electrically connected to the substrate lead-out region.

[0009] Optionally, the test structure also includes: a first source pin, the first source pin is electrically connected to the first source lead-out terminal and is located at an end of the first source lead-out terminal; a second source pin, the second source pin is electrically connected to the second source lead-out terminal and is located at an end of the second source lead-out terminal; a first drain pin, the first drain pin is electrically connected to the first drain lead-out terminal and is located at an end of the first drain lead-out terminal; a second drain pin, the second drain pin is electrically connected to the second drain lead-out terminal and is located at an end of the second drain lead-out terminal; a gate pin, the gate pin is electrically connected to the gate lead-out terminal and is located at an end of the gate lead-out terminal; and a substrate pin, the substrate pin is electrically connected to the substrate lead-out terminal and is located at an end of the substrate lead-out terminal.

[0010] Correspondingly, the technical solution of the present invention also provides another semiconductor testing method, including: providing a test structure, the test structure including: a substrate; a plurality of MOS devices located on the substrate, each of the MOS devices including a gate, a source region and a drain region, the source region and the drain region are respectively located in the substrate between the gates, the plurality of gates, the plurality of drain regions and the plurality of source regions are arranged along a first direction, and each of the drain regions is located between adjacent source regions, the plurality of source regions are electrically connected to each other, and the plurality of drain regions are electrically connected to each other; a first source lead-in terminal and a second source lead-in terminal electrically connected to the plurality of source regions respectively; a first drain lead-in terminal and a second drain lead-in terminal electrically connected to the plurality of drain regions respectively; a gate lead-in terminal electrically connected to the plurality of gates; after turning on the plurality of MOS devices, applying a preset on-current between the first drain lead-in terminal and the first source lead-in terminal, and obtaining a voltage test value between the second drain lead-in terminal and the second source lead-in terminal; obtaining an on-resistance value of the test structure according to the preset on-current and the voltage test value; obtaining an actual on-current value of the test structure according to the preset voltage and the on-resistance value.

[0011] Optionally, it also includes: providing a constant current source device, one end of which is electrically connected to the first drain lead-in terminal, and the other end is electrically connected to the first source lead-in terminal, for providing the preset on-current; providing a voltage testing device, one end of which is electrically connected to the second source lead-in terminal, and the other end is electrically connected to the second drain lead-in terminal, for obtaining the voltage test value.

[0012] Optionally, the method for obtaining the on-resistance value of the test structure includes: according to the preset on-current I test and the voltage test value V test , obtain the on-resistance value R on =V test / I test .

[0013] Optionally, the method for obtaining the actual value of the conduction current of the test structure includes: according to a preset voltage V p and the on-resistance value R on , obtain the actual value of the on-current I real =V P / R on .

[0014] Optionally, the test structure further includes: a substrate lead-out region located in the substrate; and a substrate lead-out terminal electrically connected to the substrate lead-out region.

[0015] Optionally, the conductivity types of some of the MOS devices are N-type, and the method for turning on some of the MOS devices includes: applying a power supply voltage to the gate lead-out terminal and grounding the substrate lead-out terminal; the conductivity types of some of the MOS devices are P-type, and the method for turning on some of the MOS devices includes: grounding the gate lead-out terminal and connecting the substrate lead-out terminal to the power supply voltage.

[0016] Optionally, the test structure also includes: a first interconnection layer, a number of the source regions are electrically connected to each other through the first interconnection layer, and the first source lead-out terminal and the second source lead-out terminal are electrically connected to the number of source regions respectively; a second interconnection layer, a number of the drain regions are electrically connected to each other through the second interconnection layer, and the first drain lead-out terminal and the second drain lead-out terminal are electrically connected to the drain regions respectively; a third interconnection layer, the third interconnection layer connects a number of the gates, and the gate lead-out terminal is electrically connected to the gates; a fourth interconnection layer, the fourth interconnection layer connects the substrate lead-out layer, and the substrate lead-out terminal is electrically connected to the substrate lead-out region.

[0017] Optionally, the test structure also includes: a first source pin, the first source pin is electrically connected to the first source lead-out terminal and is located at an end of the first source lead-out terminal; a second source pin, the second source pin is electrically connected to the second source lead-out terminal and is located at an end of the second source lead-out terminal; a first drain pin, the first drain pin is electrically connected to the first drain lead-out terminal and is located at an end of the first drain lead-out terminal; a second drain pin, the second drain pin is electrically connected to the second drain lead-out terminal and is located at an end of the second drain lead-out terminal; a gate pin, the gate pin is electrically connected to the gate lead-out terminal and is located at an end of the gate lead-out terminal; and a substrate pin, the substrate pin is electrically connected to the substrate lead-out terminal and is located at an end of the substrate lead-out terminal.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] In the semiconductor testing method provided by the technical solution of the present invention, a first source lead-out terminal and a second source lead-out terminal are led out from a source region, a first drain lead-out terminal and a second drain lead-out terminal are led out from a drain region, a preset on-current is applied to a plurality of MOS devices through the first source lead-out terminal and the first drain lead-out terminal, a constant current is generated between the source region and the drain region, a voltage testing device is connected between the second source lead-out terminal and the second drain lead-out terminal, and the voltages at both ends of the source region and the drain region of the plurality of MOS devices are measured. Since the resistance of the voltage testing device itself is very high, the connection of the voltage testing device makes the contact resistance between the voltage testing device and the second source lead-out terminal and the second drain lead-out terminal have a smaller voltage dividing effect in the circuit, and the difference between the voltage test value obtained by measurement and the actual voltage value of the test structure is very small. In the loop where the constant current source device and the test structure are located, since the excitation current provided by the constant current source device is not affected by the contact resistance between the constant current source device and the first source lead-out terminal and the first source lead-out terminal, the on-resistance value of the test structure obtained through the preset on-current and the voltage test value is closer to the actual resistance value, thereby improving the accuracy of the obtained on-current value.

[0020] In the semiconductor test structure provided by the technical solution of the present invention, a first source lead-out terminal and a second source lead-out terminal are respectively electrically connected to the plurality of source regions, and a first drain lead-out terminal and a second drain lead-out terminal are respectively electrically connected to the plurality of drain regions. A preset conduction current is applied to the plurality of MOS devices through the first source lead-out terminal and the first drain lead-out terminal, so that a constant current is generated between the source region and the drain region. A voltage test device is connected between the second source lead-out terminal and the second drain lead-out terminal to measure the voltage across the source region and the drain region of the plurality of MOS devices. Since the voltage test device has a high resistance, the connection of the voltage test device causes the voltage to The contact resistance between the test device and the second source lead-out terminal and the second drain lead-out terminal has a small voltage-dividing effect in the circuit, and the voltage test value obtained by measurement is very close to the actual voltage value of the test structure. In the loop where the constant current source device and the test structure are located, the excitation current provided by the constant current source device is not affected by the contact resistance between the constant current source device and the first source lead-out terminal and the first source lead-out terminal. Therefore, the on-resistance value of the test structure obtained through the preset on-current and the voltage test value is closer to the actual resistance value, thereby improving the accuracy of the obtained on-current value. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a semiconductor test structure;

[0022] Figure 2 is an equivalent circuit diagram of a semiconductor test structure;

[0023] Figure 3 is a flowchart of the steps of a semiconductor testing method according to an embodiment of the present invention;

[0024] Figure 4 is a schematic structural diagram of a semiconductor test structure according to an embodiment of the present invention;

[0025] Figure 5 is an equivalent circuit diagram of a semiconductor test structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0027] As the background technology, the existing MOS device on-current test method needs to be further improved. Now, a semiconductor test structure and test method are described and analyzed.

[0028] Figure 1 A schematic diagram of a semiconductor test structure.

[0029] Please refer to Figure 1The semiconductor test structure includes: a substrate 100, the substrate 100 includes a first region (not shown in the figure) and a second region (not shown in the figure) surrounding the first region; a plurality of gates 101 located on the first region; a source doping region 102 and a drain doping region 103 located in the first region on both sides of each gate, the source doping region 102 and the drain doping region 103 are of a first conductivity type; a substrate lead-out region 104 located in the second region, the substrate lead-out region 104 is of a second conductivity type, and the first conductivity type and the second conductivity type are different; a first metal layer located on the substrate 100, the first metal layer includes a first conductive layer 105, a second conductive layer 106, a first conductive layer 107, a second conductive layer 108, a first conductive layer 109, a second conductive layer 110, a first conductive layer 111, a second conductive layer 112, a first conductive layer 113, a first conductive layer 114, a second conductive layer 115, a first conductive layer 116, a first conductive layer 117, a first conductive layer 118, a first conductive layer 119, a first conductive layer 120, a first conductive layer 121, a first conductive layer 122, a first conductive layer 123, a first conductive layer 124, a first conductive layer 125, a second conductive layer 126, a first conductive layer 127, a first conductive layer 128, a first conductive layer 129, a first conductive layer 130, a first conductive layer 131, a first conductive layer 132, a first conductive layer 133, a first conductive layer 134, a first conductive layer 135, a second conductive layer 136, a first conductive layer 137, a first conductive layer 138, a first conductive layer 139, three conductive layers 107 and a fourth conductive layer 108, wherein the first conductive layer 105 is electrically connected to each of the gate electrodes 101, the second conductive layer 106 is electrically connected to each of the source doped regions 102, the third conductive layer 107 is electrically connected to each of the drain doped regions 103, and the fourth conductive layer 108 is electrically connected to the substrate lead-out region 104; a gate pin G, a source pin S, a drain pin D and a substrate pin B are located on the substrate 100, the gate pin G is electrically connected to the first conductive layer 105, the source pin S is electrically connected to the second conductive layer 106, the drain pin D is electrically connected to the third conductive layer 107, and the substrate pin B is electrically connected to the fourth conductive layer 108.

[0030] The semiconductor test structure described above is a comb finger (multi-finger) structure. When the MOS tube is turned on, a conduction current will be generated between the source and the drain. For the multi-finger structure, multiple MOS tubes are used in parallel. The on-current (Ion) of the device is theoretically the sum of the on-currents of each MOS tube. However, the parallel resistance of multiple MOS tubes is small. The MOS tube is turned on by connecting the source pin S to the power supply voltage and the substrate pin B to the ground. Then the current between the source pin S and the drain pin D is tested to obtain the on-current. However, when testing the on-current, it is difficult to obtain accurate test results due to the large influence of contact resistance. For details, please refer to Figure 2 .

[0031] Figure 2 It is an equivalent circuit diagram of a semiconductor test structure.

[0032] Please refer to Figure 2 , Figure 2 For conducting current test, Figure 1The equivalent circuit diagram of the test structure includes four ports, namely, a drain terminal D, a source terminal S, a gate terminal G, and a substrate terminal B. When measuring the on-current, the large current path is from the drain terminal D to the source terminal S, the contact resistance of the gate terminal G and the substrate terminal B can be ignored, while the contact resistance of the drain terminal D and the source terminal S cannot be ignored, which is equivalent to externally attaching an equivalent resistor R0 to each of the drain terminal D and the source terminal S, resulting in the voltage applied to the drain terminal D being less than the preset value, and the potential of the source terminal S also being raised, thereby causing the test current to become smaller, and the more fingers there are, the greater the impact of the contact resistance on the test structure.

[0033] Therefore, a test structure is needed to accurately characterize the on-current of a multi-finger MOS device and avoid the influence of contact resistance.

[0034] In order to solve the above problems, the present invention provides a semiconductor test structure and a test method. Since the voltage test device has a very high resistance itself, the connection of the voltage test device makes the contact resistance between the voltage test device and the second source lead-out terminal and the second drain lead-out terminal have a smaller voltage dividing effect in the circuit, and the difference between the measured voltage test value and the actual voltage value of the test structure is very small. In the loop where the constant current source device and the test structure are located, the excitation current provided by the constant current source device is not affected by the contact resistance between the constant current source device and the first source lead-out terminal and the first drain lead-out terminal. Therefore, the on-resistance value of the test structure obtained by the preset on-current and the voltage test value is closer to the actual resistance value, thereby improving the accuracy of the obtained on-current value.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figure 3 It is a flowchart of the steps of the semiconductor testing method according to an embodiment of the present invention.

[0037] In this embodiment, the semiconductor testing method includes the following steps:

[0038] Step S201, providing a test structure;

[0039] Step S202, after turning on the plurality of MOS devices, applying a preset conduction current between the first drain terminal and the first source terminal, and obtaining a voltage test value between the second drain terminal and the second source terminal;

[0040] Step S203, obtaining an on-resistance value of the test structure according to the preset on-current and the voltage test value;

[0041] Step S204, obtaining an actual value of the on-current of the test structure according to the preset voltage and the on-resistance value.

[0042] The following is a detailed description with reference to the accompanying drawings.

[0043] Figure 4 Schematic diagram of the semiconductor test structure according to an embodiment of the present invention.

[0044] Please refer to Figure 4 , and please continue to refer to Figure 3 , providing a test structure, the test structure comprising: a substrate 300; a plurality of MOS devices located on the substrate 300, each of the MOS devices comprising a gate 301, a source region 302 and a drain region 303, the source region 302 and the drain region 303 being respectively located in the substrate 300 between the gates 301, the plurality of gates 301, the plurality of drain regions 303 and the plurality of source regions 302 being arranged along a first direction X, and each of the drain regions 303 being located between adjacent source regions 302, the plurality of source regions 302 being electrically connected to each other, and the plurality of drain regions 303 being electrically connected to each other; a first source lead-out terminal 304 and a second source lead-out terminal 305 being respectively electrically connected to the plurality of source regions 302; a first drain lead-out terminal 306 and a second drain lead-out terminal 307 being respectively electrically connected to the plurality of drain regions 303; and a gate lead-out terminal 308 being electrically connected to the plurality of gates 301.

[0045] In this embodiment, the test structure further includes: a substrate lead-out region 309 located in the substrate 300 ; and a substrate lead-out terminal 310 electrically connected to the substrate lead-out region 309 .

[0046] In this embodiment, the test structure further includes: a first interconnection layer 311, through which the plurality of source regions 302 are electrically connected to each other, and the first source lead-out terminal 304 and the second source lead-out terminal 305 are electrically connected to the plurality of source regions 302 respectively; a second interconnection layer 312, through which the plurality of drain regions 303 are electrically connected to each other, and the first drain lead-out terminal 306 and the second drain lead-out terminal 307 are electrically connected to the drain regions 303 respectively; a third interconnection layer 313, the third interconnection layer 313 is connected to the plurality of gates 301, and the gate lead-out terminal 308 is electrically connected to the gates 301; and a fourth interconnection layer 314, the fourth interconnection layer 314 is connected to the substrate lead-out layer 309, and the substrate lead-out terminal 310 is electrically connected to the substrate lead-out region 309.

[0047] In this embodiment, the test structure further includes: a first source pin S1, the first source pin S1 is electrically connected to the first source lead-out terminal 304 and is located at the end of the first source lead-out terminal 304; a second source pin S2, the second source pin S2 is electrically connected to the second source lead-out terminal 305 and is located at the end of the second source lead-out terminal 305; a first drain pin D1, the first drain pin D1 is electrically connected to the first drain lead-out terminal 306 and is located at the end of the first drain lead-out terminal 306; a second drain pin D2, the second drain pin D2 is electrically connected to the second drain lead-out terminal 307 and is located at the end of the second drain lead-out terminal 307; a gate pin G, the gate pin G is electrically connected to the gate lead-out terminal 308 and is located at the end of the gate lead-out terminal 308; a substrate pin B, the substrate pin B is electrically connected to the substrate lead-out terminal 310 and is located at the end of the substrate lead-out terminal 310.

[0048] Please continue to refer to Figure 3 and Figure 4 After turning on the plurality of MOS devices, a preset conduction current is applied between the first drain terminal 306 and the first source terminal 304 , and a voltage test value between the second drain terminal 307 and the second source terminal 305 is obtained.

[0049] There is contact resistance at both application points when a preset conduction current is applied; there are also two contact points when a voltage test is performed, generating contact resistance.

[0050] In this embodiment, a constant current source device (not shown in the figure) is further provided, one end of which is electrically connected to the first drain lead-out terminal 306, and the other end of which is electrically connected to the first source lead-out terminal 304, for providing the preset conduction current. Specifically, the two ends of the constant current source device are electrically connected to the first drain pin D1 and the first source pin S1, respectively.

[0051] In this embodiment, a voltage test device (not shown in the figure) is further provided, one end of which is electrically connected to the second source lead-out terminal 305, and the other end of which is electrically connected to the second drain lead-out terminal 307, for obtaining the voltage test value. Specifically, the two ends of the voltage test device are electrically connected to the second source pin S2 and the second drain pin D2, respectively.

[0052] In this embodiment, the conductivity type of the plurality of MOS devices is N-type, and the method of turning on the plurality of MOS devices includes: applying a power supply voltage to the gate lead terminal 308 and grounding the substrate lead terminal 310 .

[0053] In another embodiment, the conductivity types of the plurality of MOS devices are all P-type, and the method for turning on the plurality of MOS devices includes: grounding the gate lead terminal and connecting the substrate lead terminal to a power supply voltage.

[0054] For ease of understanding, now combined Figure 5 The equivalent circuit diagram is used to illustrate.

[0055] Figure 5 is an equivalent circuit diagram of a semiconductor test structure according to an embodiment of the present invention.

[0056] Please refer to Figure 5 , and continue to refer to Figure 3 , according to the preset conduction current I test and the voltage test value V test , obtain the on-resistance value R of the test structure on .

[0057] In this embodiment, the method for obtaining the on-resistance value of the test structure includes: according to the preset on-current I test and the voltage test value V test , obtain the on-resistance value R on =V test / I test .

[0058] It should be noted that, in the equivalent circuit diagram, R1 is the contact resistance between the first drain lead-out terminal 306 when a preset on-current is applied, R2 is the contact resistance between the first source lead-out terminal 304 when a preset on-current is applied, R3 is the contact resistance between the second drain lead-out terminal 307 during a voltage test, and R3 is the contact resistance between the second source lead-out terminal 305 during a voltage test.

[0059] according to Figure 5 The equivalent circuit diagram of , has the following relationship:

[0060] The current I flowing through the test structure dev , I dev =I test -I v , where I v Where is the current flowing through the voltage test device.

[0061] The voltage across the test structure V dev , V dev =I v *(R3+R4+R v )=I dev *R on ;

[0062] The voltage V obtained by the test test=I v *R v ;

[0063] Due to R v >>R3+R4, R v >>R dev , V dev ≈I v *R v =V test ;

[0064] Due to R v >>R dev , so I test >>I v , so I dev ≈I test ;

[0065] So R on =V test / I dev =V test / I test .

[0066] Please continue to refer to Figure 3 , according to the preset voltage V p and the on-resistance value R on , obtaining the actual value of the on-state current of the test structure.

[0067] In this embodiment, the method for obtaining the actual value of the conduction current of the test structure includes: according to the preset voltage V p and the on-resistance value R on , obtain the actual value of the on-current I real =V P / R on .

[0068] In summary, since the voltage test device's own resistance is very high, the connection of the voltage test device makes the contact resistance between the voltage test device and the second source lead-out terminal 305 and the second drain lead-out terminal 307 have a smaller voltage-dividing effect in the circuit, and the voltage test value obtained by measurement is very close to the actual voltage value of the test structure. In the loop where the constant current source device and the test structure are located, the excitation current provided by the constant current source device is not affected by the contact resistance between the constant current source device and the first source lead-out terminal 304 and the first drain lead-out terminal 306. Therefore, the on-resistance value of the test structure obtained through the preset on-current and the voltage test value is closer to the actual resistance value, thereby improving the accuracy of the obtained on-current value.

[0069] Accordingly, the embodiment of the present invention further provides a semiconductor test structure for the above semiconductor test method, please continue to refer to Figure 4 The test structure includes: a substrate 300; a plurality of MOS devices located on the substrate 300, each of the MOS devices including a gate 301, a source region 302 and a drain region 303, the source region 302 and the drain region 303 are respectively located in the substrate 300 between the gates 301, the plurality of gates 301, the plurality of drain regions 303 and the plurality of source regions 302 are arranged along a first direction X, and each of the drain regions 303 is located between adjacent source regions 302, the plurality of source regions 302 are electrically connected to each other, and the plurality of drain regions 303 are electrically connected to each other; a first source lead-out terminal 304 and a second source lead-out terminal 305 electrically connected to the plurality of source regions 302, respectively; a first drain lead-out terminal 306 and a second drain lead-out terminal 307 electrically connected to the plurality of drain regions 303, respectively; and a gate lead-out terminal 308 electrically connected to the plurality of gates 301.

[0070] Here, a preset on-current is applied to a plurality of MOS devices through the first source lead-out terminal 304 and the first drain lead-out terminal 306 to generate a constant current between the source region 302 and the drain region 303. A voltage test device is connected between the second source lead-out terminal 305 and the second drain lead-out terminal 307 to measure the voltages across the source region 302 and the drain region 303 of the plurality of MOS devices. Since the voltage test device has a very high resistance, the connection of the voltage test device makes the contact resistance between the voltage test device and the second source lead-out terminal 305 and the second drain lead-out terminal 307 have a smaller voltage dividing effect in the circuit. The difference between the voltage test value obtained by measurement and the actual voltage value of the test structure is very small. In the loop where the constant current source device and the test structure are located, since the excitation current provided by the constant current source device is not affected by the contact resistance between the constant current source device and the first source lead-out terminal 304 and the first drain lead-out terminal 306, the on-resistance value of the test structure obtained through the preset on-current and the voltage test value is closer to the actual resistance value, thereby improving the accuracy of the obtained on-current value.

[0071] In this embodiment, the test structure further includes: a substrate lead-out region 309 located in the substrate 300 ; and a substrate lead-out terminal 310 electrically connected to the substrate lead-out region 309 .

[0072] In this embodiment, the test structure further includes: a first interconnection layer 311, through which the plurality of source regions 302 are electrically connected to each other, and the first source lead-out terminal 304 and the second source lead-out terminal 305 are electrically connected to the plurality of source regions 302 respectively; a second interconnection layer 312, through which the plurality of drain regions 303 are electrically connected to each other, and the first drain lead-out terminal 306 and the second drain lead-out terminal 307 are electrically connected to the drain regions 303 respectively; a third interconnection layer 313, the third interconnection layer 313 is connected to the plurality of gates 301, and the gate lead-out terminal 308 is electrically connected to the gates 301; and a fourth interconnection layer 314, the fourth interconnection layer 314 is connected to the substrate lead-out layer 309, and the substrate lead-out terminal 310 is electrically connected to the substrate lead-out region 309.

[0073] In this embodiment, the test structure further includes: a first source pin S1, the first source pin S1 is electrically connected to the first source lead-out terminal 304 and is located at the end of the first source lead-out terminal 304; a second source pin S2, the second source pin S2 is electrically connected to the second source lead-out terminal 305 and is located at the end of the second source lead-out terminal 305; a first drain pin D1, the first drain pin D1 is electrically connected to the first drain lead-out terminal 306 and is located at the end of the first drain lead-out terminal 306; a second drain pin D2, the second drain pin D2 is electrically connected to the second drain lead-out terminal 307 and is located at the end of the second drain lead-out terminal 307; a gate pin G, the gate pin G is electrically connected to the gate lead-out terminal 308 and is located at the end of the gate lead-out terminal 308; a substrate pin B, the substrate pin B is electrically connected to the substrate lead-out terminal 310 and is located at the end of the substrate lead-out terminal 310.

[0074] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor test structure, characterized in that: include: substrate; A plurality of MOS devices located on the substrate, each of the MOS devices comprising a gate, a source region and a drain region, the source region and the drain region being respectively located in the substrate between the gates, the gates, the drain regions and the source regions being arranged along a first direction, and each drain region being located between adjacent source regions, the source regions being electrically connected to each other, and the drain regions being electrically connected to each other; A first source lead-out terminal and a second source lead-out terminal electrically connected to the plurality of source regions respectively; A first drain lead-out terminal and a second drain lead-out terminal electrically connected to the plurality of drain regions respectively; A gate lead-out terminal electrically connected to the plurality of gates.

2. The semiconductor test structure according to claim 1, characterized in that: The test structure further includes: a substrate lead-out region located in the substrate; and a substrate lead-out terminal electrically connected to the substrate lead-out region.

3. The semiconductor test structure according to claim 2, characterized in that: The test structure further includes: a first interconnection layer, through which a plurality of the source regions are electrically connected to each other, and the first source lead-out terminal and the second source lead-out terminal are electrically connected to the plurality of the source regions, respectively; a second interconnection layer, through which a plurality of the drain regions are electrically connected to each other, and the first drain lead-out terminal and the second drain lead-out terminal are electrically connected to the drain regions, respectively; a third interconnection layer, the third interconnection layer is connected to a plurality of the gates, and the gate lead-out terminal is electrically connected to the gates; and a fourth interconnection layer, the fourth interconnection layer is connected to the substrate lead-out layer, and the substrate lead-out terminal is electrically connected to the substrate lead-out region.

4. The semiconductor test structure according to claim 2, characterized in that: The test structure also includes: a first source pin, the first source pin is electrically connected to the first source lead-out terminal and is located at an end of the first source lead-out terminal; a second source pin, the second source pin is electrically connected to the second source lead-out terminal and is located at an end of the second source lead-out terminal; a first drain pin, the first drain pin is electrically connected to the first drain lead-out terminal and is located at an end of the first drain lead-out terminal; a second drain pin, the second drain pin is electrically connected to the second drain lead-out terminal and is located at an end of the second drain lead-out terminal; a gate pin, the gate pin is electrically connected to the gate lead-out terminal and is located at an end of the gate lead-out terminal; and a substrate pin, the substrate pin is electrically connected to the substrate lead-out terminal and is located at an end of the substrate lead-out terminal.

5. A semiconductor testing method, characterized in that: include: A test structure is provided, the test structure comprising: substrate; A plurality of MOS devices located on the substrate, each of the MOS devices comprising a gate, a source region and a drain region, the source region and the drain region being respectively located in the substrate between the gates, the gates, the drain regions and the source regions being arranged along a first direction, and each drain region being located between adjacent source regions, the source regions being electrically connected to each other, and the drain regions being electrically connected to each other; A first source lead-out terminal and a second source lead-out terminal electrically connected to the plurality of source regions respectively; A first drain lead-out terminal and a second drain lead-out terminal electrically connected to the plurality of drain regions respectively; A gate lead terminal electrically connected to the plurality of gates; After turning on the plurality of MOS devices, applying a preset conduction current between the first drain terminal and the first source terminal, and obtaining a voltage test value between the second drain terminal and the second source terminal; Acquiring an on-resistance value of the test structure according to the preset on-current and the voltage test value; The actual value of the on-current of the test structure is obtained according to the preset voltage and the on-resistance value.

6. The semiconductor testing method according to claim 5, characterized in that: Also includes: Providing a constant current source device, one end of which is electrically connected to the first drain lead-out terminal, and the other end of which is electrically connected to the first source lead-out terminal, for providing the preset on-current; A voltage testing device is provided, one end of which is electrically connected to the second source lead-out terminal, and the other end of which is electrically connected to the second drain lead-out terminal, for obtaining the voltage test value.

7. The semiconductor testing method according to claim 5, characterized in that: The method for obtaining the on-resistance value of the test structure comprises: according to the preset on-current I test and the voltage test value V test , obtain the on-resistance value R on =V test / I test .

8. The semiconductor testing method according to claim 5, wherein: The method for obtaining the actual value of the conduction current of the test structure includes: according to the preset voltage V p and the on-resistance value R on , obtain the actual value of the on-current I real =V P / R on .

9. The semiconductor testing method according to claim 5, characterized in that: The test structure further includes: a substrate lead-out region located in the substrate; and a substrate lead-out terminal electrically connected to the substrate lead-out region.

10. The semiconductor testing method according to claim 9, wherein: The conductivity types of some of the MOS devices are N-type, and the method of turning on some of the MOS devices includes: applying a power supply voltage to the gate lead-out terminal and grounding the substrate lead-out terminal; the conductivity types of some of the MOS devices are P-type, and the method of turning on some of the MOS devices includes: grounding the gate lead-out terminal and connecting the substrate lead-out terminal to the power supply voltage.

11. The semiconductor testing method according to claim 9, wherein: The test structure further includes: a first interconnection layer, through which a plurality of the source regions are electrically connected to each other, and the first source lead-out terminal and the second source lead-out terminal are electrically connected to the plurality of the source regions, respectively; a second interconnection layer, through which a plurality of the drain regions are electrically connected to each other, and the first drain lead-out terminal and the second drain lead-out terminal are electrically connected to the drain regions, respectively; a third interconnection layer, the third interconnection layer is connected to a plurality of the gates, and the gate lead-out terminal is electrically connected to the gates; and a fourth interconnection layer, the fourth interconnection layer is connected to the substrate lead-out layer, and the substrate lead-out terminal is electrically connected to the substrate lead-out region.

12. The semiconductor testing method according to claim 11, wherein: The test structure also includes: a first source pin, the first source pin is electrically connected to the first source lead-out terminal and is located at an end of the first source lead-out terminal; a second source pin, the second source pin is electrically connected to the second source lead-out terminal and is located at an end of the second source lead-out terminal; a first drain pin, the first drain pin is electrically connected to the first drain lead-out terminal and is located at an end of the first drain lead-out terminal; a second drain pin, the second drain pin is electrically connected to the second drain lead-out terminal and is located at an end of the second drain lead-out terminal; a gate pin, the gate pin is electrically connected to the gate lead-out terminal and is located at an end of the gate lead-out terminal; and a substrate pin, the substrate pin is electrically connected to the substrate lead-out terminal and is located at an end of the substrate lead-out terminal.

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