Semiconductor device and etching method and preparation method thereof

Abstract

The invention discloses a semiconductor device and an etching method and a preparation method thereof, a first etching process is adopted to etch a dummy gate to remove the dummy gate of a first thickness and retain the dummy gate of a second thickness, the first thickness is greater than the second thickness, a second etching process is adopted to etch the dummy gate of the second thickness, and the second thickness is greater than the second thickness. The second etching process comprises a gasification process, the gasification process is used for converting the dummy gate with the second thickness into a gaseous substance and enabling the gaseous substance to escape, and the corrosion of the second etching process, such as the gasification process, to the barrier layer is smaller than the corrosion of the first etching process, such as a dry etching process or a wet etching process, to the barrier layer; therefore, the damage of etching of the dummy gate to the barrier layer can be reduced, the metal blocking capability of the barrier layer cannot be obviously reduced, the probability that metal in the metal gate is diffused to the gate dielectric layer with a high dielectric constant can be reduced, and the reliability of the semiconductor device can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and an etching method and a preparation method thereof. Background Art

[0002] With the development of semiconductor technology, the size of semiconductor devices (such as transistors) is constantly shrinking, while the leakage current and power consumption of semiconductor devices are constantly increasing. Although the leakage current and power consumption of semiconductor devices can be effectively reduced by replacing the traditional gate dielectric material with a high dielectric constant gate dielectric material and replacing the polysilicon gate with a metal gate, in the process of forming the metal gate using the last gate process, after the pseudo gate is replaced with the metal gate, the metal barrier ability of the barrier layer between the gate and the high dielectric constant gate dielectric layer will be significantly reduced, resulting in an increase in the probability of the metal in the metal gate diffusing into the high dielectric constant gate dielectric layer, resulting in poor reliability of the semiconductor device. Summary of the invention

[0003] The invention discloses a semiconductor device and an etching method and a preparation method thereof, so that the metal barrier capability of the barrier layer will not be significantly reduced.

[0004] In a first aspect, the present invention discloses an etching method for a semiconductor device, comprising: providing a semiconductor device to be etched, the semiconductor device comprising a substrate, a dummy gate structure and an interlayer dielectric layer located on the substrate, the dummy gate structure comprising a high dielectric constant gate dielectric layer, a barrier layer and a dummy gate layer stacked in sequence on the substrate, the substrates on both sides of the dummy gate structure having doped regions, the interlayer dielectric layer filling between the dummy gate structures and exposing the dummy gate; etching the dummy gate using a first etching process to remove the dummy gate of a first thickness and retaining the dummy gate of a second thickness; the first thickness is greater than the second thickness; etching the dummy gate using a second etching process to remove the dummy gate of the second thickness; the second etching process is less corrosive to the barrier layer than the first etching process; and the second etching process comprises a gasification process, the gasification process is used to convert the dummy gate of the second thickness into a gaseous substance and escape.

[0005] In some embodiments of the present invention, the material of the dummy gate is polysilicon, and the etching of the dummy gate by the second etching process includes: using a first sub-process to convert part of the polysilicon of the dummy gate of the second thickness into silicon dioxide; using a second sub-process to make the silicon dioxide react with the remaining polysilicon of the dummy gate of the second thickness to generate silicon monoxide, and allowing the silicon monoxide to escape in a gaseous form.

[0006] In some embodiments of the present invention, the first sub-process includes an oxidation process; the oxidation process includes one or more of a dry oxygen oxidation process, a wet oxygen oxidation process, and an in-situ water vapor growth process.

[0007] In some embodiments of the present invention, the first sub-process includes a wet cleaning process; and the cleaning solution of the wet cleaning process includes an APM cleaning solution.

[0008] In some embodiments of the present invention, the thickness of the portion of polysilicon converted into silicon dioxide ranges from 8 Å to 12 Å.

[0009] In some embodiments of the present invention, the second sub-process includes a rapid annealing process; the rapid annealing process includes a rapid annealing process under an inert atmosphere.

[0010] In some embodiments of the present invention, the first etching process includes one or more of a dry etching process and a wet etching process.

[0011] In some embodiments of the present invention, the second thickness is less than or equal to 100 Å.

[0012] In a second aspect, the present invention discloses a method for preparing a semiconductor device, comprising: forming a dummy gate structure on a substrate, and making the dummy gate structure include a high dielectric constant gate dielectric layer, a barrier layer and a dummy gate stacked in sequence on the substrate, so that the substrate on both sides of the dummy gate structure forms a doped region; forming an interlayer dielectric layer on the substrate, so that the interlayer dielectric layer fills between the dummy gate structures and exposes the dummy gate; etching the dummy gate using an etching method as described in any of the above items; and sequentially forming a metal work function layer and a metal gate in the opening from which the dummy gate is etched.

[0013] In a third aspect, the present invention discloses a semiconductor device manufactured by the manufacturing method described above.

[0014] The semiconductor device and its etching method and preparation method disclosed in the present invention adopt a first etching process to etch a pseudo gate to remove a pseudo gate of a first thickness and retain a pseudo gate of a second thickness, wherein the first thickness is greater than the second thickness, and a second etching process is adopted to etch the pseudo gate of the second thickness to remove the pseudo gate of the second thickness, wherein the second etching process comprises a gasification process, wherein the gasification process is used to convert the pseudo gate of the second thickness into a gaseous substance and to escape, because the second etching process such as the gasification process has less corrosiveness to the barrier layer than the first etching process such as the dry etching process or the wet etching process, therefore, the damage of the pseudo gate etching to the barrier layer can be reduced, thereby preventing the metal barrier capability of the barrier layer from being significantly reduced, thereby reducing the probability of the metal in the metal gate diffusing into the gate dielectric layer with a high dielectric constant, thereby ensuring the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0016] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor device to be etched with a dummy gate.

[0017] Figures 2 to 4 A schematic diagram of the cross-sectional structure of a semiconductor device showing various steps of replacing a dummy gate with a metal gate using a gate-last process.

[0018] Figure 5 The present invention is a flowchart of a method for etching a semiconductor device disclosed in an embodiment of the present invention.

[0019] Figure 6 The cross-sectional structure diagram of a semiconductor device to be etched disclosed in an embodiment of the present invention.

[0020] Figure 7 It is a schematic diagram of the cross-sectional structure of a semiconductor device with a dummy gate of a first thickness removed according to an embodiment of the present invention.

[0021] Figure 8 It is a schematic cross-sectional structure diagram of a semiconductor device with a dummy gate of a second thickness removed according to an embodiment of the present invention.

[0022] Fig. 9 It is a schematic diagram of the cross-sectional structure of a semiconductor device after a first sub-process disclosed in an embodiment of the present invention.

[0023] Fig.10 It is a schematic diagram of the cross-sectional structure of a semiconductor device after a second sub-process disclosed in an embodiment of the present invention.

[0024] Fig.11 The present invention is a flowchart of a method for preparing a semiconductor device disclosed in an embodiment of the present invention.

[0025] Figures 12 to 16 The schematic diagram is a cross-sectional structure diagram of a semiconductor device at various steps of preparing a semiconductor device using a gate-last process. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] As described in the background technology, replacing the traditional gate dielectric material with a high dielectric constant gate dielectric material and replacing the polysilicon gate with a metal gate can effectively reduce the leakage current and power consumption of the semiconductor device. However, because the metal gate is not resistant to high temperatures, in order to avoid the high temperature annealing during the source and drain region doping process affecting the performance of the metal gate, a post-gate process is usually used to form the metal gate. In the post-gate process, a polysilicon dummy gate is first formed on the substrate, and then the source and drain regions on both sides of the dummy gate are doped and high-temperature annealed, and then the dummy gate is replaced with a metal gate.

[0028] The following uses semiconductor devices including transistors as an example to illustrate the replacement process of the dummy gate and the metal gate. Figure 1 As shown, the semiconductor device to be etched with a dummy gate includes a substrate 10, a dummy gate structure 11 and an interlayer dielectric layer 12 located on the substrate 10, the interlayer dielectric layer 12 covers the dummy gate structure 11 and fills the gap between the dummy gate structures 11, the substrate 10 on both sides of the dummy gate structure 11 has a doping region, etc., and the dummy gate structure 11 includes a high dielectric constant gate dielectric layer 110, a blocking layer 111 and a dummy gate 112 which are sequentially stacked on the substrate 10.

[0029] like Figures 2 to 4 As shown, the interlayer dielectric layer 10 is first subjected to a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer 10 and expose the dummy gate 112; then, the dummy gate 112 is etched and the etching is stopped at the top of the barrier layer 111; then, a metal work function layer 13 and a metal gate 14 are sequentially formed in the opening where the dummy gate 112 is removed.

[0030] The inventors have found that although the metal blocking capability of the barrier layer 111 can be improved by diffusing silicon into the barrier layer 111 through the pseudo gate 112 of polysilicon, etching the pseudo gate 112 using conventional etching processes such as dry etching or wet etching will damage the barrier layer 111, resulting in a significant decrease in the metal blocking capability of the barrier layer 111, and an increased probability of the metal in the metal gate 14 diffusing into the gate dielectric layer 110 with a high dielectric constant, resulting in reduced reliability of the semiconductor device.

[0031] Based on this, the present invention discloses an etching scheme, which first uses a dry etching process or a wet etching process with greater corrosiveness to remove most of the pseudo gate 112, and then uses a gasification process with less corrosiveness to remove the remaining small part of the pseudo gate 112, so as to reduce the damage of the etching of the pseudo gate 112 to the blocking layer 111, thereby ensuring that the metal blocking ability of the blocking layer 111 will not be significantly reduced, thereby reducing the probability of the metal in the metal gate 14 diffusing into the gate dielectric layer 110 with a high dielectric constant, thereby ensuring the reliability of the semiconductor device.

[0032] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses an etching method for a semiconductor device, such as Figure 5 As shown, the etching method comprises: S101: Provide a semiconductor device to be etched, which includes a substrate, a dummy gate structure and an interlayer dielectric layer located on the substrate, the dummy gate structure includes a high dielectric constant gate dielectric layer, a barrier layer and a dummy gate layer stacked in sequence on the substrate, the substrate on both sides of the dummy gate structure have doped regions, and the interlayer dielectric layer is filled between the dummy gate structures and exposes the dummy gate. In some embodiments of the present invention, Figure 6 As shown, the semiconductor device includes a substrate 10, a dummy gate structure 11 located on the substrate 10, and an interlayer dielectric layer 12. The substrate 10 includes a first region 101, a second region 102, and a shallow trench isolation structure 103 located between the first region 101 and the second region 102. The first region 101 is used to form a PMOS transistor, the second region 102 is used to form an NMOS transistor, and the shallow trench isolation structure 103 is used to isolate the first region 101 and the second region 102. In addition, the first region 101 and the second region 102 both include a lightly doped region 1000, a heavily doped region 1001, and a metal silicide layer 1002. The dummy gate structure 11 includes a high dielectric constant gate dielectric layer 110, a barrier layer 111, and a dummy gate 112 stacked in sequence on the substrate 10. The sidewalls of the dummy gate structure 11 have sidewalls 113. The interlayer dielectric layer 12 is filled between the dummy gate structures 11 and exposes the top of the dummy gate 112.

[0033] After forming the interlayer dielectric layer 12 filling between the dummy gate structures 11 and covering the dummy gate structures 11, the interlayer dielectric layer 12 may be subjected to a chemical mechanical polishing process to expose the dummy gate 112 from the interlayer dielectric layer 12. In addition, a gate oxide layer 104 may be provided between the substrate 10 and the dummy gate structure 11. Furthermore, the material of the substrate 10 may be any material suitable for forming a semiconductor device, such as silicon carbide, gallium nitride, aluminum nitride, indium nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire or silicon wafer, etc.; the shallow trench isolation structure 103 is a shallow trench structure filled with insulating materials such as silicon oxide; the material of the high dielectric constant gate dielectric layer 110 may be one or more of materials such as hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium oxynitride, zirconium oxynitrosilicate, hafnium silicate, hafnium oxynitrosilicate, lanthanum hafnium oxynitride or hafnium aluminum oxide, etc.; the material of the barrier layer 111 may be titanium nitride, etc.; the material of the pseudo gate 112 may be polycrystalline silicon, etc.; the material of the interlayer dielectric layer 12 may be silicon oxide, etc.; the sidewall 113 may be a stacked structure composed of silicon oxide and silicon nitride; the material of the gate oxide layer 104 may be silicon oxide, etc.

[0034] It should be noted that the embodiments of the present invention only use semiconductor devices including PMOS transistors and NMOS transistors as an example for illustration, but are not limited to this. In other embodiments, the semiconductor device may also include PMOS transistors, NMOS transistors, static random access memories, image sensors or power devices, etc., which will not be repeated here.

[0035] S102: Etching the dummy gate using a first etching process to remove the dummy gate having a first thickness and retaining the dummy gate having a second thickness; wherein the first thickness is greater than the second thickness.

[0036] In some embodiments of the present invention, Figure 7 As shown, after the dummy gate 112 is etched by the first etching process, the dummy gate 112 of the first thickness D1 is removed, and the dummy gate 112 of the second thickness D2 is retained. The first thickness D1 is greater than the second thickness D2. In some embodiments of the present invention, the second thickness D2 is less than or equal to 100Å to ensure that the subsequent second etching process can completely remove the dummy gate 112.

[0037] The first etching process includes one or more of a dry etching process and a wet etching process. Specifically, a photoresist layer can be formed on the surface of the semiconductor device, and after the photoresist layer is exposed and developed, the photoresist layer exposes the dummy gate 112, and then the dummy gate 112 is etched using an etching gas of a dry etching process or an etching solution of a wet etching process.

[0038] S103: using a second etching process to etch the dummy gate of the second thickness to remove the dummy gate of the second thickness; wherein the second etching process is less corrosive to the barrier layer than the first etching process, and the second etching process includes a gasification process, and the gasification process is used to convert the dummy gate of the second thickness into a gaseous substance and escape.

[0039] In some embodiments of the present invention, Figure 8 As shown, the dummy gate 112 can be etched by a second etching process to remove the dummy gate 112 of the second thickness D2. The second etching process is less corrosive to the barrier layer 111 than the first etching process, and the second etching process includes a gasification process, which is used to convert the dummy gate 112 of the second thickness D2 into a gaseous substance and escape.

[0040] Because the second etching process, such as the gasification process, is less corrosive to the barrier layer 111 than the first etching process, such as the dry etching process or the wet etching process, the damage to the barrier layer 111 caused by the etching of the pseudo gate 112 can be reduced, and the metal blocking ability of the barrier layer 111 will not be significantly reduced, thereby reducing the probability of the metal in the metal gate diffusing into the gate dielectric layer 110 with a high dielectric constant, thereby ensuring the reliability of the semiconductor device.

[0041] Moreover, because the etching rate of the dummy gate 112 in the first etching process is greater than the etching rate of the dummy gate 112 in the second etching process, and the first thickness D1 is greater than the second thickness D2, it can be ensured that the etching rate of the dummy gate 112 will not be significantly reduced, and thus it can be ensured that the preparation efficiency of the semiconductor device will not be significantly reduced.

[0042] In some embodiments of the present invention, the material of the dummy gate 112 is polysilicon, such as Fig. 9 As shown, a first sub-process may be used to convert a portion of polysilicon of the dummy gate 112 having a second thickness D2 into silicon dioxide, such as Fig.10 As shown, a second sub-process is then used to react silicon dioxide with the remaining polysilicon of the pseudo gate 112 of the second thickness D2 to generate silicon monoxide, and the silicon monoxide is released in a gaseous form, which can be expressed by the formula SiO 2 +Si→SiO↑.

[0043] In some embodiments of the present invention, the first sub-process may include an oxidation process. Among them, the oxidation process may include one or more of a dry oxygen oxidation process, a wet oxygen oxidation process, or an in-situ steam growth process (In-Situ Steam Generation, ISSG for short). In some embodiments, a dry oxygen oxidation process may be used to form silicon dioxide. Specifically, the semiconductor device may be placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen may be introduced into the furnace tube, so that part of the polysilicon of the pseudo gate 112 reacts with oxygen at high temperature to generate a dense silicon dioxide layer.

[0044] Of course, the present invention is not limited to this. In other embodiments, the first sub-process may also include a wet cleaning process. Among them, the cleaning solution of the wet cleaning process includes an APM cleaning solution. Among them, the APM cleaning solution is also called SC1 cleaning solution, which includes a mixture of ammonium hydroxide, hydrogen peroxide and deionized water. The APM cleaning solution can not only remove mild organic contamination and partial metal contamination on the surface of the pseudo gate 112 of the second thickness D2, but also oxidize polysilicon into silicon dioxide. Of course, the present invention is not limited to this. In other embodiments, other processes can also be used to convert part of the polysilicon of the pseudo gate 112 of the second thickness D2 into silicon dioxide, which will not be repeated here.

[0045] In some embodiments of the present invention, the thickness of the portion of polysilicon converted into silicon dioxide ranges from 8 Å to 12 Å. In some embodiments, the thickness of the portion of polysilicon converted into silicon dioxide is about 10 Å. Based on this, silicon dioxide can fully react with the remaining portion of polysilicon to generate silicon monoxide, so as to completely remove the pseudo gate 112 of the second thickness D2.

[0046] In some embodiments of the present invention, the second sub-process may include a rapid annealing process, and the rapid annealing process includes a rapid annealing process under an inert atmosphere, and the inert atmosphere includes nitrogen or argon, etc. Among them, the annealing temperature and time of the rapid annealing process can be set according to requirements, and will not be repeated here.

[0047] It should be noted that, when the material of the dummy gate 112 is polysilicon, a gasification process including an oxidation process or a wet cleaning process and a rapid annealing process can be used to remove the dummy gate 112 of the second thickness D2. However, the present invention is not limited to this. When the material of the dummy gate 112 is not polysilicon, a gasification process including other sub-processes can be used to remove the dummy gate 112 of the second thickness D2.

[0048] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a method for preparing a semiconductor device, such as Fig.11 As shown, the etching method comprises: S201: forming a dummy gate structure on a substrate, and making the dummy gate structure include a high dielectric constant gate dielectric layer, a barrier layer and a dummy gate sequentially stacked on the substrate, so that the substrate on both sides of the dummy gate structure forms doped regions.

[0049] In some embodiments of the present invention, a substrate 10 may be provided first, a hard mask including a silicon oxide layer and a silicon nitride layer may be formed on the substrate 10, a photolithography process may be used to make the hard mask have a plurality of openings, and the hard mask and a portion of the substrate 10 at the opening positions may be removed to form a shallow trench, and then an insulating material may be filled in the shallow trench to form a structure such as Fig.12 The shallow trench isolation structure 103 is shown. Then, ion implantation is performed on the substrate 10 to form a first region 101 and a second region 102 with different doping types. Then, a gate oxide layer 104 is formed on the surface of the substrate 10, and a high dielectric constant gate dielectric layer 110, a barrier layer 111 and a dummy gate 112 are sequentially formed on the surface of the substrate 10, and are etched to form Fig.13 The dummy gate structure 11 is shown.

[0050] like Fig.14As shown, after the dummy gate structure 11 is formed, the substrate 10 on both sides of the dummy gate structure 11 is lightly doped to form a lightly doped region 1000, and then sidewalls 113 are formed on both sides of the dummy gate structure 11, and then the substrate 10 on both sides of the dummy gate structure 11 is heavily doped to form a heavily doped region 1001, and the heavily doped region 1001 is subjected to high temperature annealing to activate it, and then a metal silicide layer 1002 is formed on the heavily doped region 1001 to improve the contact resistance of the conductive plug subsequently formed on the source and drain.

[0051] S202: forming an interlayer dielectric layer on the substrate, so that the interlayer dielectric layer fills between the dummy gate structures and exposes the dummy gate.

[0052] like Fig.15 As shown, an etch stop layer 20 and an interlayer dielectric layer 12 are formed on the substrate 10 , and the interlayer dielectric layer 12 is subjected to chemical mechanical polishing to expose the dummy gate 112 from the interlayer dielectric layer 12 .

[0053] S203: Etching the dummy gate using the etching method in any of the above embodiments.

[0054] like Figure 7 , Fig. 9 and Fig.10 As shown, the dummy gate 112 is first etched by a first etching process, and then the dummy gate 112 of the first thickness D1 is removed, and the dummy gate 112 of the second thickness D2 is retained, and then an oxidation process is used to convert part of the polysilicon of the dummy gate 112 of the second thickness D2 into silicon dioxide, and then a rapid annealing process is used to react the silicon dioxide with the remaining part of the polysilicon of the dummy gate 112 of the second thickness D2 to generate silicon monoxide, and the silicon monoxide is allowed to escape in a gaseous form.

[0055] S204: forming a metal work function layer and a metal gate in sequence in the opening where the dummy gate is etched away.

[0056] like Fig.16 As shown, a metal work function layer 13 and a metal gate 14 are sequentially formed in the opening where the dummy gate 112 is removed. The metal work function layer 13 includes one or more of tantalum nitride, titanium nitride, titanium aluminide, titanium aluminum nitride or tungsten nitride. The metal gate 14 can be a metal material with good conductivity such as metal aluminum, tungsten, copper or silver. The metal gate 14 can include a single layer of metal, a multilayer of metal or a metal compound stack. Of course, a source electrode and a drain electrode can also be formed on the substrate 10 later, which will not be repeated here.

[0057] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a semiconductor device, which is prepared by the preparation method described in the above embodiment. Fig.16As shown, the semiconductor device includes a substrate 10, a gate structure and an interlayer dielectric layer 12 located on the substrate 10. The gate structure includes a high dielectric constant gate dielectric layer 110, a barrier layer 111, a metal work function layer 13 and a metal gate 14 stacked sequentially on the substrate 10. Of course, the present invention is not limited to this. In other embodiments, the semiconductor device also includes a source and a drain.

[0058] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A method for etching a semiconductor device, characterized in that: include: A semiconductor device to be etched is provided, the semiconductor device comprising a substrate, a dummy gate structure and an interlayer dielectric layer located on the substrate, the dummy gate structure comprising a high dielectric constant gate dielectric layer, a barrier layer and a dummy gate sequentially stacked on the substrate, the substrate on both sides of the dummy gate structure having doped regions, the interlayer dielectric layer filling between the dummy gate structures and exposing the dummy gate; Etching the dummy gate by a first etching process to remove the dummy gate having a first thickness and retaining the dummy gate having a second thickness; The first thickness is greater than the second thickness; Etching the dummy gate using a second etching process to remove the dummy gate having the second thickness; The corrosiveness of the second etching process on the barrier layer is less than the corrosiveness of the first etching process on the barrier layer; Furthermore, the second etching process includes a gasification process, and the gasification process is used to convert the dummy gate of the second thickness into a gaseous substance and make it escape.

2. The etching method according to claim 1, characterized in that: The material of the dummy gate is polysilicon, and the etching of the dummy gate by the second etching process includes: Using a first sub-process to convert a portion of polysilicon of the dummy gate of the second thickness into silicon dioxide; A second sub-process is used to make the silicon dioxide react with the remaining polysilicon of the dummy gate with the second thickness to generate silicon monoxide, and the silicon monoxide is released in a gaseous form.

3. The etching method according to claim 2, characterized in that: The first sub-process includes an oxidation process; the oxidation process includes one or more of a dry oxygen oxidation process, a wet oxygen oxidation process, and an in-situ water vapor growth process.

4. The etching method according to claim 2, characterized in that: The first sub-process includes a wet cleaning process; and a cleaning solution of the wet cleaning process includes an APM cleaning solution.

5. The etching method according to claim 2, characterized in that: The thickness of the portion of polysilicon that is converted to silicon dioxide ranges from 8 Å to 12 Å.

6. The etching method according to claim 2, characterized in that: The second sub-process includes a rapid annealing process; and the rapid annealing process includes a rapid annealing process under an inert atmosphere.

7. The etching method according to claim 1, characterized in that: The first etching process includes one or more of a dry etching process and a wet etching process.

8. The etching method according to claim 1, characterized in that: The second thickness is less than or equal to 100 Å.

9. A method for preparing a semiconductor device, characterized in that: include: Forming a dummy gate structure on a substrate, wherein the dummy gate structure includes a high dielectric constant gate dielectric layer, a barrier layer and a dummy gate sequentially stacked on the substrate, and forming doped regions on the substrate at both sides of the dummy gate structure; forming an interlayer dielectric layer on the substrate, so that the interlayer dielectric layer fills between the dummy gate structures and exposes the dummy gate; Etching the dummy gate by using the etching method according to any one of claims 1 to 8; A metal work function layer and a metal gate are sequentially formed in the opening where the dummy gate is etched away.

10. A semiconductor device, characterized in that: The preparation method according to claim 9 is used for preparation.

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