Memory element

Abstract

A memory device includes a bonding structure and a plurality of bit lines. The substrate includes a first region and a second region adjacent to each other. The bonding structure is disposed over the substrate. The bonding structure includes a bonding dielectric layer, a plurality of first bonding pads and a plurality of second bonding pads. A bonding dielectric layer is over the substrate in the first region and the second region. A plurality of first bonding pads are buried in the bonded dielectric layer of the first region. A plurality of second bonding pads are buried in the bonding dielectric layer of the second region. A plurality of bit lines are disposed over the bonding structure, extending from the first region to the second region. A density of the plurality of first bonding pads in the first region is greater than a density of the plurality of second bonding pads in the second region. The memory element can be a 3D NAND flash memory with high capacity and high performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a memory device. Background Art

[0002] Non-volatile memory elements (eg, flash memory) have become a widely used memory element in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.

[0003] The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. For example, the bit line may not be connected to the via window, causing reliability problems. Summary of the invention

[0004] A memory element according to an embodiment of the present invention comprises: a substrate, a bonding structure and a plurality of bit lines. The substrate comprises a first region and a second region adjacent to each other. The bonding structure is arranged above the substrate. The bonding structure comprises a bonding dielectric layer, a plurality of first bonding pads and a plurality of second bonding pads. The bonding dielectric layer is above the substrate in the first region and the second region. The plurality of first bonding pads are in the bonding dielectric layer in the first region. The plurality of second bonding pads are in the bonding dielectric layer in the second region. The plurality of bit lines are arranged above the bonding structure, extending from the first region to the second region, and each of the plurality of first bonding pads is electrically connected to one of the bit lines. The density of the plurality of first bonding pads in the first region is greater than the density of the plurality of second bonding pads in the second region.

[0005] In some embodiments of the present invention, the first area includes a first sub-area of ​​a memory array area overlapping with a page cache area, and the second area includes a staircase area overlapping with a decoding area and a second sub-area of ​​the memory array area overlapping with a peripheral circuit area.

[0006] In some embodiments of the present invention, the memory element further includes a plurality of third bonding pads and a plurality of fourth bonding pads. The plurality of third bonding pads are in the bonding dielectric layer of the page buffer area. The plurality of fourth bonding pads are in the bonding dielectric layer of the decoding area and the peripheral circuit area. The plurality of third bonding pads are bonded to the corresponding plurality of first bonding pads, and the plurality of fourth bonding pads are bonded to the corresponding plurality of second bonding pads.

[0007] Based on the above, the memory device of the embodiment of the present invention increases the density of the bonding pads in the memory array region, which can increase the number of contact windows connected to the bit lines. Therefore, the electrical connection between the bit lines and the contact windows can be ensured, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1H The invention is a cross-sectional view of a manufacturing process of a memory device having a CMOS-Bonded-Array (CbA) structure according to an embodiment of the invention.

[0009] FIG. 2A to FIG. 2H FIG. 4 is another cross-sectional schematic diagram of a manufacturing process of a memory element with a CbA structure according to an embodiment of the present invention.

[0010] Figure 3 yes Figure 1A A top view of a partial area of ​​the first wafer.

[0011] Figure 4A yes Figure 1C and Figure 2C FIG. 1 is a top view of a partial area of ​​the second wafer.

[0012] Figure 4B yes Figure 1D and Figure 2D FIG. 1 is a top view of a partial area of ​​the second wafer.

[0013] FIG. 5A to FIG. 5C A top view and a three-dimensional view are shown of a plurality of bonding pads and a plurality of bit lines in two adjacent regions.

[0014] FIG. 6A to FIG. 6B A top view and a perspective view are shown of a same group of bonding pads and a same region of a same region and a same group of bit lines.

[0015] FIG. 7A to FIG. 7B A top view and a perspective view are shown of multiple groups of bonding pads and multiple bit lines in the same area.

[0016] 10, 100: Base

[0017] 10W: First Chip

[0018] 20: Component layer

[0019] 30, 40: Internal connection structure

[0020] 30a, 32a, P1: Part I

[0021] 30b, 32b, P2: Part 2

[0022] 31a, 31b, 42, 50, 107, 115, 128, 130: dielectric layer

[0023] 32: Joint structure

[0024] 33a, 33b: Internal connection

[0025] 34, 34a, 34b: Bonding dielectric layer

[0026] 35b: Connection features

[0027] 36a, 36b: Connecting plug

[0028] 38, 38a, 38b, 38b11, 38b12, 38b15, 38b16, 38b21, 38b22, 38b25, 38b26: Bonding pads

[0029] 46. ​​COA: Contact Window

[0030] 48. CL1, CL2: Wire

[0031] 92, 101, 102: Insulation layer

[0032] 93, 94, 126: Conductor layer

[0033] 100W: Second chip

[0034] 103, 129: Stop layer

[0035] 104: Middle layer

[0036] 105: Insulation structure

[0037] 106: Opening

[0038] 108: Charge storage structure

[0039] 110: Channel layer

[0040] 112: Insulation column

[0041] 114: Channel plug

[0042] 116: Separation channel

[0043] 117: Gap wall

[0044] 121: Horizontal channel

[0045] AR1: First array

[0046] AR2: Second array

[0047] BL, BL1, BL2, BL3, BL 25 BL26 BL 27 BL n BL n+24 BL n+48 BL n+m BL n+2m : Bit line

[0048] BR1: Zone 1

[0049] BR2: Second Zone

[0050] C1, C2, C3, C4: Row / 1st row, 2nd row, 3rd row, 4th row

[0051] CP1: First connection

[0052] CP2: Second connection

[0053] CSL: Common Source Line

[0054] CT1, CT2: Center line

[0055] D1: First distance

[0056] D2: Second distance

[0057] d1: distance

[0058] G, G1, G2, G3: Group

[0059] L1: first length

[0060] L2: Second length

[0061] L3: The third length

[0062] PIC: Support structure

[0063] R1, R1′, R2, R2′, R3: Area

[0064] RSC: Anti-step structure

[0065] Rw1~Rw8:row

[0066] SC: Ladder structure

[0067] SK1, SK2: stacked structure

[0068] SLT: Separated Structure

[0069] SR1′: First sub-region

[0070] SR2′: Second sub-region

[0071] TV: Perforation

[0072] U1, U2: Unit

[0073] V1, V2: Plug

[0074] V3: Interlayer Window

[0075] VC: Vertical Channel Column

[0076] WL: Word Line

[0077] XDEC: row decoder and column decoder

[0078] II′, II-II′: line DETAILED DESCRIPTION

[0079] The CMOS-Bonded-Array (CbA) structure is a memory element architecture that combines a chip with a complementary metal oxide semiconductor element and a chip with a memory array by bonding. In this architecture, the bit line is connected to the page buffer in the chip of the complementary metal oxide semiconductor element through a via, a bonding pad, and an internal connection. In order to allow the bit line to be connected to the via, the reliability of the memory element can be ensured by setting a plurality of vias. However, the number of bonding pads will also increase, occupying more chip area. The embodiments of the present invention can increase the number of vias connected to the bit line without increasing the area by changing the density and arrangement of the bonding pads, thereby improving the reliability of the memory element.

[0080] Figures 1A to 1H It is a cross-sectional schematic diagram of a manufacturing process of a memory element with a CbA structure according to an embodiment of the present invention. FIG. 2A to FIG. 2H FIG. 4 is another cross-sectional schematic diagram of a manufacturing process of a memory element with a CbA structure according to an embodiment of the present invention. Figure 3 yes Figure 1A A top view of a partial area of ​​the first wafer. Figure 4A yes Figure 1C and Figure 2C FIG. 1 is a top view of a partial area of ​​the second wafer. Figure 4B yes Figure 1D and Figure 2D FIG. 1 is a top view of a partial area of ​​the second wafer. Figure 1A To Figure 1 H is along Figure 3 as well as Figure 4A as well as Figure 4B Cross-sectional view along line II′. FIG. 2A to FIG. 2H For along Figure 3 as well as Figure 4A as well as Figure 4B Cross-sectional view along line II-II′.

[0081] Reference Figure 1A , Figure 2A and Figure 3 , providing a first wafer 10W. The first wafer 10W includes a substrate 10. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The substrate 10 may include regions R1, R2, and R3 (shown in FIG. Figure 3 ). The regions R1, R2 and R3 may be respectively referred to as page buffer regions, peripheral circuit regions and row decoder and column decoder regions.

[0082] Reference Figure 1A , Figure 2A and Figure 3 , component layer 20 (shown in Figure 1A ) is formed in regions R1, R2, R3 (shown in Figure 3 ) on the substrate 10. The component layer 20 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor (CMOS) component. Since the component layer 20 is disposed below the memory array (for example, located Figure 1H or 2H stacked structure SK2), and the component layer 20 is, for example, a complementary metal oxide semiconductor component (CMOS). Therefore, this architecture can also be called a memory array (CMOS-Bonded-Array, CbA) structure of a bonded complementary metal oxide semiconductor component. The component layer 20 on the region R1 may include a plurality of page buffers PB. The component layer 20 on the region R2 may include a plurality of peripheral circuits PC. The component layer 20 on the region R3 may include a plurality of row decoders and column decoders XDEC.

[0083] Reference Figure 1A and Figure 2A , a first portion 30a of the interconnect structure 30 is formed on the device layer 20. The first portion 30a of the interconnect structure 30 may include a multi-layer dielectric layer 31a and an interconnect 33a formed in the multi-layer dielectric layer. The interconnect 33a includes a plurality of plugs V1 and a plurality of conductors CL1.

[0084] Reference Figure 1A , Figure 2A and Figure 3 , a bonding structure 32 (shown in FIG. 1 ) is formed on the first portion 30a of the interconnect structure 30. Figure 1G). The first part 32a of the bonding structure 32 includes a bonding dielectric layer 34a and a bonding plug 36a and a bonding pad 38a buried in the bonding dielectric layer 34a. The bonding dielectric layer 34a is, for example, silicon oxide, silicon nitride or a combination thereof. The bonding plug 36a and the bonding pad 38a are, for example, copper. The bonding pad 38a is connected to the topmost conductor CL1 of the first part 30a of the inner connection structure 30 via the bonding plug 36a. The bonding pad 38a and the bonding plug 36a can be formed by single inlay or double inlay. The bonding pad 38a, the bonding plug 36a and the bonding dielectric layer 34a can be planarized and coplanar by a chemical mechanical polishing process.

[0085] Reference Figure 3 In an embodiment of the present invention, the arrangement of the plurality of bonding pads 38a in region R1 is different from the arrangement of the bonding pads 38a in regions R2 and R3, so that the density of the bonding pads 38a in region R1 is greater than the density of the bonding pads 38a in regions R2 and R3, which will be described in detail later.

[0086] Reference Figure 1A , Figure 2A and Figure 4A , providing a second wafer 100W. The second wafer 100W includes a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 may include regions R1′ and R2′. The region R1′ is also called a memory array region, and the region R2′ is also called a step region. The region R1′ may include a first sub-region SR1′ and a second sub-region SR2′ (such as Figure 4A See Figure 3 and Figure 4A , after the subsequent bonding process, the first sub-region SR1′ of the region (memory array region) R1′ of the second wafer 100W will overlap with the region (page buffer region) R1 of the first wafer 10W. The second sub-region SR2′ of the region (memory array region) R1′ of the second wafer 100W will overlap with the region (peripheral circuit region) R2 of the first wafer 10W. The region (step region) R2′ of the second wafer 100W will overlap with the region (row decoder and column decoder) R3 of the first wafer 10W.

[0087] Reference Figure 1A , an insulating layer 101 and a stop layer 103 are formed on the substrate 100 in the regions R1′ and R2′. The insulating layer 101 is, for example, silicon oxide. The stop layer 103 is formed on the insulating layer 101. The stop layer 103 may include a plurality of conductor layers 94 and insulating layers 92 stacked alternately and an insulating structure 105. The conductor layer 94 includes polysilicon, and the insulating layer 92 and the insulating structure 105 include silicon oxide.

[0088] Reference Figure 1A and Figure 2A, a stacked structure SK1 is formed on the stop layer 103 in the regions R1′ and R2′. The stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 that are alternately stacked. In some embodiments, the material of the insulating layer 102 includes silicon oxide, and the material of the intermediate layer 104 includes silicon nitride. The intermediate layer 104 can be used as a sacrificial layer, which will be partially or completely removed in subsequent processes.

[0089] Reference Figure 1A and Figure 2A Then, the middle layer 104 and the insulating layer 102 of the stacked structure SK1 in the region R2′ are patterned to form a stepped structure SC (shown in FIG. Figure 1A A dielectric layer 107 is formed on the substrate 100 to cover the step structure SC. The material of the dielectric layer 107 is, for example, silicon oxide.

[0090] Reference Figure 1A and Figure 2A , a patterning process is performed to remove a portion of the stacked structure SK1 to form one or more openings 106 extending through the stacked structure SK1. A charge storage structure 108 is then formed in the opening 106. The charge storage structure 108 is in contact with the insulating layer 102 and the intermediate layer 104. In one embodiment, the charge storage structure 108 is an oxide / nitride / oxide (ONO) composite layer.

[0091] A vertical channel column VC is then formed in the remaining space of the opening 106. The vertical channel column VC includes a channel layer 110, an insulating column 112, and a channel plug 114. The material of the channel layer 110 includes undoped polysilicon. The material of the insulating column 112 includes silicon oxide. The material of the channel plug 114 includes a semiconductor material with dopants, such as doped polysilicon. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel column VC. Then, a dielectric layer 115 is formed above the substrate 100. The material of the dielectric layer 115 includes silicon oxide.

[0092] Reference Figure 1A and Figure 2A , forming a plurality of support structures PIC and a plurality of through holes TV. The support structure PIC and the plurality of through holes TV may extend from the top surface of the dielectric layer 115 through the stacked structure SK1 and the stop layer 103 to prevent the step structure SC from collapsing during the subsequent removal of the intermediate layer 104. The through holes TV will be connected to the internal connection in the subsequent process, so they are also called signal contacts.

[0093] Reference Figure 1B and Figure 2B, a dielectric layer 128 is formed on the dielectric layer 115. The dielectric layer 128 is, for example, silicon oxide. Thereafter, a patterning process is performed to form a plurality of separation trenches 116. The separation trenches 116 extend through the dielectric layer 128, the dielectric layer 115, and the stacked structure SK1, and divide the stacked structure SK1 into a plurality of blocks (not shown). The separation trenches 116 may have vertical sidewalls or slightly inclined sidewalls (not shown).

[0094] Reference Figure 1B and Figure 2B , a replacement process is performed to replace part of the middle layer 104 with the conductor layer 126. The conductor layer 126 can be used as a gate layer or a word line WL. The conductor layer 126, for example, includes a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the metal layer includes tungsten (W). Part of the middle layer 104 is replaced by the conductor layer 126, thereby forming a stacked structure SK2.

[0095] The stack structure SK2 includes a first portion P1 and a second portion P2. The first portion P1 of the stack structure SK2 includes a plurality of alternately stacked insulating layers 102 and a plurality of intermediate layers 104. The second portion P2 of the stack structure SK2 includes a plurality of alternately stacked insulating layers 102 and a plurality of conductive layers 126.

[0096] Reference Figure 1C and Figure 2C Then, the conductor layer (not shown) formed in the separation channel 116 is removed, and a spacer 117 is formed on the sidewall of the separation channel 116. The spacer 117 includes a dielectric material different from the insulating layer 102, such as silicon nitride or a silicon oxide / silicon nitride / silicon oxide composite layer. Afterwards, the middle conductor layer 94 and the insulating layers 92 above and below in the stop layer 103 are removed to form a horizontal channel 121. Then, the conductor layer 93, such as a doped polysilicon layer, is filled in the remaining space between the horizontal channel 121 and the separation channel 116. The conductor layer 93 in the horizontal channel 121 and the conductor layers 94 above and below it can form a common source line CSL together. The conductor layer 93 in the separation channel 116 and the spacer 117 together form a separation structure (slit structure) SLT. The conductor layer 93 of the separation structure SLT is isolated by the spacer 117 to avoid contact with the conductor layer 126. Thereafter, a stop layer 129 and a dielectric layer 130 are formed on the dielectric layer 128 to cover the top surface of the separation structure SLT. The stop layer 129 is, for example, silicon nitride, and the dielectric layer 130 is, for example, silicon oxide.

[0097] Reference Figure 1C and Figure 2CNext, a plurality of contact windows COA are formed in the dielectric layer 130 and the dielectric layer 107 to electrically connect the conductive layer 126 , the vertical channel pillars VC, and the through holes TV, respectively.

[0098] Reference Figure 1C , Figure 2C and Figure 4A , a second portion 30b of the interconnect structure 30 and the bit line BL are formed above the substrate 100. The interconnect structure 30 (shown in FIG. Figure 1G and Figure 2G ) may include a multi-layer dielectric layer 31b and an internal connection 33b formed in the multi-layer dielectric layer 31b. The internal connection 33b includes a plurality of plugs V2 and a plurality of conductors CL2. The dielectric layer 31b separates adjacent conductors CL2. The conductors CL2 may be connected to each other through the plugs V2, and the conductors CL2 may be connected to the contact window COA through the plugs V2. The second portion 30b of the internal connection structure 30 may be formed by a single metal damascene process, a dual metal damascene process, or any known method. The bit line BL is connected to the vertical channel column VC via the plugs V2 and the contact window COA.

[0099] Reference Figure 4A For brevity, Figure 4A Only the bit lines BL are shown in FIG. 1 . A plurality of bit lines BL are arranged in the region R1′, extending from the first sub-region SR1′ to the second sub-region SR2′. The plurality of bit lines BL in the first sub-region SR1′ will be connected to the first wafer 10W (shown in FIG. 1 ). Figure 3 ) is electrically connected to the page buffer PB set in area R1.

[0100] Reference Figure 1D and Figure 2D In the embodiment of the present invention, a via V3 and a connection feature 35b are further formed on the plurality of bit lines BL. The via V3 connects the bit lines BL and the connection feature 35b. The via V3 and the connection feature 35b can also be formed by a single metal damascene process, a dual metal damascene process or any known method. The connection relationship between the plurality of bit lines BL, the plurality of vias V3 and the plurality of connection features 35b can also be referred to. Figure 5C , Figure 6B as well as Figure 7B , which will be described in detail later.

[0101] Reference Figure 1E and Figure 2E , forming a bonding structure 32 (shown in FIG. 1 ) on the second portion 30 b of the interconnect structure 30. Figure 1G). The second portion 32b of the bonding structure 32 includes a bonding dielectric layer 34b and a bonding plug 36b and a bonding pad 38b buried in the bonding dielectric layer 34b. The bonding pad 38b is connected to the bit line BL via the bonding plug 36b and the connection feature 35b. The materials and forming methods of the bonding dielectric layer 34b, the bonding plug 36b and the bonding pad 38b may be the same or similar to the materials and forming methods of the bonding dielectric layer 34a, the bonding plug 36a and the bonding pad 38a. The first portion 30a of the interconnect structure and the second portion 30b of the interconnect structure will form the interconnect structure 30 (shown in FIG. 1 ) together after the bonding process. Figure 1H and Figure 2H ). The bonding structure 32 is buried in the interconnect structure 30 .

[0102] Reference Figure 4B In an embodiment of the present invention, the arrangement of the bonding pads 38b in the first sub-region SR1′ of the region R1′ is different from the arrangement of the bonding pads 38b in the second sub-region SR2′ of the region R1′ and the region R2′, so that the density of the bonding pads 38b in the first sub-region SR1′ of the region R1′ is greater than the density of the bonding pads 38b in the second sub-region SR2′ of the region R1′ and the region R2′, which will be described in detail later.

[0103] Reference Figure 1F and Figure 2F The substrate 100 is turned over so that the second wafer 100W faces the first wafer 10W. The step structure SC on the turned substrate 100 becomes an inverted step structure RSC. The contact window COA is below the inverted step structure RSC.

[0104] Reference Figure 1G and Figure 2G, and a bonding process is performed. In an embodiment of the present invention, the second chip 100W faces the first chip 10W, and therefore, the bonding process is a face-to-face bonding process. The second portion 32b of the bonding structure 32 is bonded to the first portion 32a of the bonding structure 32 to form the bonding structure 32. In the bonding structure 32, the bonding dielectric layer 34b corresponds to the bonding dielectric layer 34a and is bonded to form the bonding dielectric layer 34. The bonding pad 38b corresponds to the bonding pad 38a and is bonded to form the bonding pad 38. The bonding dielectric layer 34b and the bonding dielectric layer 34a can be bonded by dielectric-to-dielectric. The bonding pad 38b and the bonding pad 38a can be bonded by metal-to-metal. The bonding structure 32 is located in the interconnect structure 30, between the first portion 30a and the second portion 30b of the interconnect structure 30. The first portion 30a and the second portion 30b form an interconnect structure 30, and the bonding structure 32 is embedded in the interconnect structure 30. Next, the substrate 100 is removed to expose the insulating layer 101. The substrate 100 can be removed by grinding, polishing or etching.

[0105] Reference Figure 3 and Figure 4B After the bonding process, the first sub-region SR1′ of the region R1′ of the second wafer 100W will overlap with the region R1 of the first wafer 10W. The second sub-region SR2′ of the region R1′ of the second wafer 100W will overlap with the region R2 of the first wafer 10W. The region R2′ of the second wafer 100W will overlap with the region R3 of the first wafer 10W.

[0106] Reference Figure 1H and Figure 2H , and perform the back-end process. A contact window 46, a plurality of wires 48, and a dielectric layer 50 of the interconnect structure 40 are formed on the insulating layer 101. The contact window 46 is electrically connected to the through hole TV. The wire 48 can be connected to the contact window 46. The material of the wire 48 is, for example, copper or tungsten. The dielectric layer 50 can be a single layer or a multilayer. The material of the dielectric layer 50 can be silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. The interconnect structure 40 can be electrically connected to the interconnect structure 30 via the through hole TV.

[0107] In other embodiments, a portion of the substrate 100 of the second wafer 100W may be retained after thinning. Afterwards, a semiconductor through-hole (or silicon through-hole via) is formed in the substrate 100 to electrically connect with the through-hole TV, and then the back-end process is performed. The semiconductor through-hole (or silicon through-hole via) may include an insulating liner (not shown) and a conductor layer (not shown).

[0108] In the present embodiment, the word line WL may be electrically connected to the second portion 30 b of the interconnect structure 30 , the bonding structure 32 , the first portion 30 a and the connection device layer 20 via the contact window COA.

[0109] The bit line BL can be electrically connected to the upper channel pillar structure VC through the plug V2 and the contact window COA of the second portion 30b of the interconnect structure 30. The bit line BL can be electrically connected to the page buffer in the lower device layer 20 through the bonding structure 32 in the interconnect structure 30 and the first portion 30a.

[0110] Reference Figure 1H The bonding pad 38a in the bonding structure 32 is bonded to the bonding pad 38b, so the position of the bonding pad 38a corresponds to the position of the bonding pad 38b. In the embodiment of the present invention, the bonding pads 38a and 38b have different configurations and densities according to their locations.

[0111] For the sake of simplicity, the area (page cache area) R1 of the first chip 10W and the first sub-area SR1′ of the area (memory array area) R1′ of the second chip 100W are called the first area BR1, and the areas (peripheral circuit area, row decoder area, and column decoder area) R2, R3 of the first chip 10W and the second sub-area SR1′ of the area (memory array area) R1′ of the second chip 100W and the area (step area) R2′ are called the second area BR2.

[0112] Reference Figure 3 and Figure 4B In an embodiment of the present invention, the density of the bonding pads 38a and 38b in the first region BR1 is greater than the density of the bonding pads 38a and 38b in the second region BR2. In some embodiments, the bonding pad 38b in the first region BR1 is referred to as the first bonding pad 38b, and the bonding pad 38b in the second region BR2 is referred to as the second bonding pad 38b (e.g. Figure 4B The bonding pad 38a in the first region BR1 is called the third bonding pad 38a, and the bonding pad 38a in the second region BR2 is called the fourth bonding pad 38a (as shown in FIG. Figure 3 The first bonding pad 38b and the third bonding pad 38a may also be referred to as active bonding pads. The second bonding pad 38b and the fourth bonding pad 38a may also be referred to as dummy bonding pads.

[0113] The bonding pads 38a and 38b in the first region BR1 may be arranged in a first array AR1. The bonding pads 38a and 38b in the second region BR2 may be arranged in a second array AR2. The arrangement of the first array AR1 is different from that of the second array AR2.

[0114] The bonding pads 38a arranged in the first array AR1 are arranged in the same manner as the bonding pads 38b arranged in the first array AR1. The bonding pads 38a arranged in the second array AR2 are arranged in the same manner as the bonding pads 38b arranged in the second array AR2. For simplicity, only the bonding pads 38b are described below.

[0115] FIG. 5A to FIG. 5C The top view and the three-dimensional view of the bonding pads and the bit lines of two adjacent regions (the first region and the second region) are shown. Figure 5B and Figure 5C In the example, each group of bit lines St is represented by only a single bit line BL (ie, bit lines BLn, BLn+m, BLn+2m), where n and m are integers.

[0116] Reference FIG. 5A to FIG. 5C In the first region BR1, there are a plurality of bonding pads 38b in a first array AR1. Figure 5A and Figure 5B In the figure, the first array AR1 is represented by a plurality of bonding pads 38b of only 3 rows and 8 columns (C1-C3, Rw1-Rw8), but the present invention is not limited thereto. The first array AR1 may include more rows and more columns. In the first array AR1, the bonding pads 38b of two adjacent columns are arranged alternately, and the bonding pads 38b of two adjacent rows are arranged alternately. The first array AR is arranged, for example, in a closest packing manner. In addition, four adjacent bonding pads 38b in two adjacent rows, for example, the four centers of the bonding pads 38b11 and 38b12 of the first row C1 and the bonding pads 38b21 and 38b22 of the second row C2, form a diamond unit U1.

[0117] Reference Figure 5A , in the second region BR2, there are a plurality of bonding pads 38b of the second array AR1. In the figure, only a plurality of bonding pads 38b of 3 rows and 4 columns (C1-C3, Rw1-Rw4) are used to represent the second array AR2, but the present invention is not limited to this. The second array AR2 may include more rows and more columns. In the second array AR2, the bonding pads 38b of two adjacent columns are arranged opposite to each other, and the bonding pads 38a of two adjacent rows are arranged opposite to each other. In addition, four adjacent bonding pads 38b in two adjacent rows, for example, the four centers of the bonding pads 38b15 and 38b16 of the first row C1 and the bonding pads 38b25 and 38b26 of the second row C2 form a rectangular unit or a square unit U2.

[0118] Reference Figure 5AIn an embodiment of the present invention, a plurality of bit lines BL extend from the first region BR1 to the second region BR2. The plurality of bit lines BL can be divided into a plurality of groups of St bit lines. In the first region BR1, a group of St bit lines BL passes between the bonding pads 38b of two adjacent rows. Each group of St bit lines BL has m bit lines BL, where m is an integer, such as 24, 48, 96 or more. For ease of explanation, the following explanation assumes that m is 24. For example, 24 bit lines BL of the second group St2 cross between the bonding pad 38b of the first row C1 and the bonding pad 38b of the second row C2. 24 bit lines BL of the third group St3 cross between the bonding pad 38b of the second row C2 and the bonding pad 38b of the third row C3.

[0119] In an embodiment of the present invention, the m bit lines BL of each group St are connected to the plurality of bonding pads 38b of the same row. For example, the 24 bit lines BL of the first group St1 are connected to the plurality of bonding pads 38b of the first row C1. The 24 bit lines BL of the second group St2 are connected to the plurality of bonding pads 38b of the second row C2. The 24 bit lines BL of the third group St3 are connected to the plurality of bonding pads 38b of the third row C1. The 24 bit lines BL of the fourth group St4 are connected to the plurality of bonding pads 38b of the fourth row (not shown).

[0120] Reference Figure 5B and Figure 5C In an embodiment of the present invention, a plurality of bit lines BL are located above a plurality of bonding pads 38b of the first region BR1 and the second region BR2. However, the plurality of bit lines BL are only electrically connected to the plurality of bonding pads 38b of the first region BR1, but not to the bonding pads 38b of the second region BR2. Furthermore, in an embodiment of the present invention, each bonding pad 38b in the first region BR1 can be electrically connected to one of the plurality of bit lines BL. In other words, each bonding pad 38b in the first region BR1 is a functional active bonding pad, and no bonding pad 38b is dummy. Therefore, the present invention can effectively utilize each bonding pad 38b to avoid the bonding pad 38b being wasted.

[0121] FIG. 6A to FIG. 6B A top view and a perspective view are shown of a same group of bonding pads and a same region of a same region and a same group of bit lines.

[0122] Reference Figure 5B and Figure 5C as well as Fig. 6A and Figure 6B In the embodiment of the present invention, each bit line BL can be electrically connected to a plurality of (for example, more than three) bonding pads 38b in the first region BR1, and then electrically connected to the page buffer PB in the lower device layer 20 (as shown in FIG. Figure 3 in). FIG. 5B to FIG. 6BIn the embodiment, each bit line BL can be electrically connected to four bonding pads 38b. Since each bit line BL can be electrically connected to multiple bonding pads 38b, even if the bit line BL cannot be connected to one of the bonding pads 38b, the bit line BL can still be normally connected to other bonding pads 38b. Therefore, the present invention can make the memory element have better reliability.

[0123] Reference Figure 5B , a first distance D1 between two center lines CT11, CT12 of a plurality of bonding pads 38b in two adjacent rows (e.g., C1 and C2) in the first array AR1 is smaller than a second distance D2 between two center lines CT21, CT22 of a plurality of bonding pads 38b in two adjacent rows (e.g., C1 and C2) in the second array AR2. Therefore, the embodiment of the present invention allows the bit line BL to be connected to more bonding pads 38b without increasing the occupied chip area.

[0124] Reference Figure 5B and Figure 5C as well as Fig. 6A and Figure 6B In an embodiment of the present invention, the bit line BL in the first region BR1 can be electrically connected to the plurality of bonding pads 38b through the plurality of vias V3, the plurality of connection features 35b and the bonding plugs 36b. The plurality of connection features 35b are disposed between the plurality of bit lines BL and the plurality of bonding pads 38b. Each bit line BL is connected to the plurality of connection features 35b through the plurality of vias V3. The plurality of connection features 35b are connected to the plurality of bonding pads 38b through the plurality of bonding plugs 36b.

[0125] Each connection feature 35b may include a first connection portion CP1 and a second connection portion CP2 connected to each other. The first connection portion CP1 is connected to the bit line BL, and the second connection portion CP2 is connected to the bonding plug 36b. The first connection portion CP1 and the second connection portion CP2 extend in different directions. A plurality of first connection portions CP1 connected to the same bit line BL are arranged in a row and have substantially the same length and width. A plurality of second connection portions CP2 connected to the same bit line BL have substantially the same length L1 and width.

[0126] Reference Figure 5B and Figure 5C as well as Fig. 6A and Figure 6B In the embodiment of the present invention, the bit line BL in the second region BR2 is not connected to the bonding pad 38b. Therefore, the plurality of vias V3, the plurality of connection features 35b, and the bonding plug 36b are not provided in the second region BR2.

[0127] FIG. 7A to FIG. 7B A top view and a perspective view are shown of multiple groups of bonding pads and multiple bit lines in the same area.

[0128] Reference Fig. 7A and Figure 7B In some embodiments, the plurality of bonding pads 38b in the same row can be divided into a plurality of groups G of bonding pads 38b, such as a first group G1, a second group G2, and a third group G3. Each group G has a plurality of bonding pads 38b, such as more than 3. Fig. 7A and Figure 7B In the embodiment, each group G in the first row C1 or the second row C has four bonding pads 38b. However, the present invention is not limited thereto.

[0129] Reference Fig. 7A and Figure 7B In the present embodiment, in the first region BR1, the multiple connection features 35b of two adjacent rows are arranged alternately. The multiple first connection portions CP1 of the multiple connection features 35b connecting the multiple bonding pads 38b of the same group G of the same row are arranged in a row. For example, the multiple first connection portions CP1 of the multiple bonding pads 38b of the first group G1 connecting the first row C1 are arranged in a row. The multiple first connection portions CP1 of the multiple bonding pads 38b of the second group G2 connecting the first row C1 are arranged in another row. In other words, the multiple first connection CP1 portions of the bonding pads 38b of different groups connecting the same row are offset from each other by a distance d1. For example, the multiple first connection portions CP1 of the multiple bonding pads 38b of the first group G1 connecting the first row C1 and the multiple first connection portions CP1 of the bonding pads 38b of the second group G2 connecting the first row C1 are not arranged in a row, but are offset by a non-zero distance d1.

[0130] Reference Fig. 7A and Figure 7B , the plurality of connection features 35b connecting the plurality of bonding pads 38b of the same group in the same row have the same length. The plurality of connection features 35b connecting the plurality of bonding pads 38b of different groups in the same row have different lengths. In this embodiment, the plurality of first connection portions CP1 in the first region BR1 have the same length and width, and the bonding plugs 36b are connected by changing the lengths of the plurality of second connection portions CP2.

[0131] The second connection portions CP2 connecting the bonding pads 38b of the same group G in the same row have the same length. For example, the second connection portions CP2 connecting the bonding pads 38b of the first group G1 in the first row C1 have the same first length L1. The second connection portions CP2 connecting the bonding pads 38b of the second group G2 in the first row C1 have the same second length L2. The second connection portions CP2 connecting the bonding pads 38b of the third group G3 in the first row C1 have the same third length L3.

[0132] The second connection portions CP2 connecting the bonding pads 38b of different groups G in the same row have different lengths. For example, the first length L1 of the second connection portions CP2 connecting the bonding pads 38b of the first group G1 of the first row C1 is greater than the second length L2 of the second connection portions CP2 connecting the bonding pads 38b of the second group G2 of the first row C1, and is also greater than the third length L3 of the second connection portions CP2 connecting the bonding pads 38b of the third group G3 of the first row C1.

[0133] In the above embodiments, the bonding structure 32b is disposed on the front side of the second wafer 100W, and the second wafer 100W is bonded to the first wafer 10W in a face-to-face bonding manner. However, the present invention is not limited thereto. In other embodiments, the bonding structure of the first wafer 10W may also be disposed on the back side of the substrate 10, and the bonding structure of the second wafer 100W may also be disposed on the back side of the substrate 100. Therefore, the second wafer may be bonded to the first wafer in various ways. For example, the second wafer may be bonded to the first wafer in a face-to-back or back-to-face manner.

[0134] In addition, the above description is based on 3D NAND flash memory as an example, however, the present invention is not limited thereto, and the present invention can also be applied to other memories, such as 3D NOR flash memory or dynamic random access memory.

[0135] In summary, the memory element of the embodiment of the present invention increases the density of the bonding pads in the memory array area overlapping the page buffer area, which can increase the number of contact windows connecting the bit lines, thereby ensuring the electrical connection between the bit lines and the contact windows and improving the reliability of the element.

Claims

1. A memory element, characterized in that: include: A substrate, comprising a first region and a second region adjacent to each other; A bonding structure, disposed above the substrate, comprises: A bonding dielectric layer is formed over the substrate in the first region and the second region. a plurality of first bonding pads buried in the bonding dielectric layer above the substrate in the first region; and a plurality of second bonding pads buried in the bonding dielectric layer above the substrate in the second region; and A plurality of bit lines are disposed above the bonding structure and extend from the first region to the second region, and each of the plurality of first bonding pads is electrically connected to one of the bit lines. The density of the first bonding pads in the first region is greater than the density of the second bonding pads in the second region. 2 . The memory device according to claim 1 , wherein the first region comprises a first sub-region of a memory array region overlapping with a page buffer region, and the second region comprises a second sub-region of the memory array region overlapping with a peripheral circuit region.

3. The memory element according to claim 2, further comprising: a plurality of third bonding pads in the bonding dielectric layer of the page buffer region; as well as A plurality of fourth bonding pads are provided in the bonding dielectric layer between the decoding area and the peripheral circuit area. The plurality of third bonding pads are bonded to the corresponding plurality of first bonding pads, and the plurality of fourth bonding pads are bonded to the corresponding plurality of second bonding pads. 4 . The memory device according to claim 1 , wherein the plurality of first bonding pads are arranged in a first array, the plurality of second bonding pads are arranged in a second array, and an arrangement of the first array is different from an arrangement of the second array. 5 . The memory device according to claim 4 , wherein in the first array, a plurality of first bonding pads in two adjacent columns or two adjacent rows are arranged alternately with each other. 6 . The memory element according to claim 4 , wherein a plurality of centers connecting two adjacent first bonding pads in a first row and two adjacent first bonding pads in an adjacent second row in the first array form a diamond-shaped unit.

7. The memory device of claim 4, wherein a first distance between two center lines of a plurality of first bonding pads in two adjacent rows in the first array is smaller than a second distance between two center lines of a plurality of second bonding pads in two adjacent rows in the second array. 8 . The memory device according to claim 4 , wherein in the second array, the plurality of second bonding pads in two adjacent columns are disposed opposite to each other, and the plurality of second bonding pads in two adjacent rows are disposed opposite to each other. 9 . The memory element according to claim 8 , wherein a plurality of centers of two adjacent second bonding pads in a first row and a plurality of centers of two adjacent second bonding pads in an adjacent second row in the second array are connected to form a rectangular unit or a square unit.

10. The memory device according to claim 4, wherein the first bonding pads in each row in the first array include a plurality of groups of first bonding pads, and each group of the plurality of first bonding pads in the same row in the first array is electrically connected to one of the plurality of bit lines. 11 . The memory device according to claim 10 , wherein each group of first bonding pads in each row is electrically connected to a corresponding one of the plurality of bit lines. 12 . The memory device of claim 11 , wherein the group of first bonding pads includes at least three first bonding pads. 13 . The memory device of claim 10 , further comprising a plurality of connection features, wherein each connection feature connects one of the plurality of first bonding pads and one of the plurality of bit lines.

14. The memory element of claim 13, wherein the plurality of connection features comprises: A plurality of first connection portions electrically connecting the plurality of bit lines; as well as A plurality of second connection portions are electrically connected to the plurality of first bonding pads.

15. The memory element of claim 14, further comprising: A plurality of vias connecting the plurality of first connection portions and the plurality of bit lines; as well as A plurality of bonding plugs connect the plurality of second connection portions and the plurality of first bonding pads. 16 . The memory device according to claim 14 , wherein the plurality of second connection portions connecting the same group of first bonding pads in the same row have the same length. 17 . The memory device according to claim 14 , wherein the plurality of second connection portions connecting different groups of first bonding pads in the same row have different lengths. 18 . The memory device according to claim 14 , wherein the plurality of first connection portions connected to the same group of first bonding pads in the same row are arranged in a row. 19 . The memory device according to claim 14 , wherein the plurality of first connection portions connecting different groups of first bonding pads in the same row are offset from each other. 20 . The memory device according to claim 10 , wherein in the second region, the plurality of bit lines extend over the plurality of second bonding pads and are not electrically connected to the plurality of second bonding pads.

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