Wafer and preparation process thereof, laser device and preparation process thereof

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a wafer and a preparation process thereof, and a laser device and a preparation process thereof, the wafer comprises a P-surface electrode, a substrate, a metal reflective layer, an epitaxial layer and an N-surface electrode which are stacked; a CuSiC alloy base plate is adopted as the substrate; and the epitaxial layer is an AlGaInP epitaxial layer after the original substrate is removed, and is bonded on the metal reflective layer. According to the technical scheme provided by the invention, the substrate adopts the CuSiC alloy substrate and is provided with the metal reflective layer, so that the LED lamp has the advantages of high luminous efficiency, high percent of pass and low manufacturing cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and more particularly, to a wafer and a preparation process thereof, and a laser device and a preparation process thereof. BACKGROUND

[0002] At present, the wafer of AlGaInP quaternary chip generally uses a GaAs substrate. Since the band gap of the GaAs substrate is narrower than that of AlGaInP, the light photons generated by the active region and emitted downward will be absorbed, which greatly reduces the light emitting efficiency. In order to avoid the absorption of the substrate, a distributed Bragg reflector (DBR) is generally added between the substrate and the active layer to reflect the light emitted toward the substrate and reduce the absorption of GaAs. Since the DBR reflection layer can only effectively reflect the light within a small angle (usually DBR < 20) of the normal direction, most of the light far from the normal incidence is absorbed by the GaAs substrate, so the effect is not great.

[0003] In order to improve the light emitting efficiency, people have begun to study other substrates.

[0004] The transparent substrate is a GaP substrate transparent to visible light (TS) that replaces the GaAs substrate. That is, the die structure of a long and thick GaP window layer is etched and peeled off from the GaAs substrate, and then bonded on the GaP substrate. The light emitting efficiency can be improved by more than one time. However, the process has the disadvantages of low yield and high manufacturing cost. SUMMARY

[0005] The technical problem to be solved by the embodiments of the present application is how to design the wafer of the chip so as to have the advantages of high light emitting efficiency, high yield and low manufacturing cost.

[0006] In order to solve the above technical problem, the embodiments of the present application provide a wafer, which adopts the technical scheme as follows: A wafer includes a P-face electrode, a substrate, a metal light-reflecting layer, an epitaxial layer and an N-face electrode which are stacked. The substrate is a CuSiC alloy substrate. The epitaxial layer is an AlGaInP epitaxial layer after removing the original substrate, and is bonded to the metal light-reflecting layer.

[0007] Further, the metal light-reflecting layer is a multi-layer metal structure, and the bottom layer of the metal light-reflecting layer in contact with the CuSiC alloy substrate contains a metal material for forming a P-type ohmic contact.

[0008] Further, the metal light-reflecting layer is an AuBe / Au laminated structure, and the Au is arranged closer to the epitaxial layer (4) than the AuBe.

[0009] Further, the CuSiC alloy substrate is a single-side polished structure, and the metal light-reflecting layer is formed on the polished surface.

[0010] To solve the above technical problems, the application further provides a wafer preparation process for preparing the wafer, comprising the following preparation steps: S1, preparing a metal light-reflecting layer on the surface of a CuSiC alloy substrate; S2, providing an AlGaInP / GaAs epitaxial wafer with a P-side metal layer; S3, low-temperature alloy bonding the P-side metal layer of the epitaxial wafer and the metal light-reflecting layer on the CuSiC alloy substrate; S4, removing the original GaAs substrate of the epitaxial wafer to form an AlGaInP epitaxial layer; S5, making a P-side electrode on the side of the CuSiC alloy substrate away from the epitaxial layer, and making an N-side electrode on the surface of the AlGaInP epitaxial layer after removing the GaAs substrate.

[0011] Further, the low-temperature alloy bonding is performed under the protection of N2 / H2 mixed atmosphere, the bonding temperature of the low-temperature alloy bonding is 250-350℃, and an axial pressure is applied, the axial pressure is 1-10MPa.

[0012] Further, the way of removing the original GaAs substrate of the epitaxial wafer is wet chemical etching treatment, the etching solution used in the etching treatment is an NH4OH / H2O2 mixed aqueous solution, the volume ratio of NH4OH:H2O2:H2O is 1:(1-2):(20-50), the temperature of the etching treatment is 20-30℃, and the time of the etching treatment is 60-75min.

[0013] To solve the above technical problems, the application further provides a laser device comprising the wafer.

[0014] To solve the above technical problems, the application further provides a laser device preparation process for preparing the laser device, the laser device is a laser chip, comprising the following preparation steps: S1', preparation of the intermediate body of the wafer: the substrate, the metal light-reflecting layer and the epitaxial layer together constitute the intermediate body of the wafer, and the intermediate body of the wafer is prepared; S2', ridge waveguide formation: the transverse optical waveguide and the current limiting structure of the laser device are defined on the epitaxial layer of the intermediate body of the wafer through photolithography and etching processes to form the ridge waveguide; S3', P-side electrode making: a P-side electrode with a specified pattern is formed on the side of the substrate away from the epitaxial layer. S4', N surface processing and N electrode fabrication: processing the surface of the epitaxial layer away from the P surface electrode as a smooth back surface, forming an N surface electrode on the back surface, and obtaining an epitaxial wafer; S5', bar preparation and cavity surface processing: slicing / dicing the obtained epitaxial wafer to divide the wafer into a plurality of bars, and plating an optical film on the cavity surface of the bar slicing / dicing; S6', die separation: separating the bar with the plated optical film by dicing / slicing to obtain a single laser device.

[0015] Further, in the step S2', the width of the ridge waveguide is controlled to 2.5-5.0 μm by a photolithography process.

[0016] Compared with the prior art, the embodiments of the present application have the following beneficial effects: The CuSiC alloy substrate wafer of the present application uses a cheap and stable CuSiC sheet as a substrate, and the metal reflective layer forms a mirror surface structure, has a reflectivity of more than 90% for red light and yellow light, and can reflect light of all incident angles, so that the light output efficiency can be improved by nearly one time. In addition, the CuSiC substrate has high mechanical strength and high thermal conductivity, which can greatly improve the high temperature characteristics of the product and improve the reliability of the product.

[0017] Since the mirror surface structure does not require a thick GaP window layer and a DBR layer, the consumption of epitaxial material can be greatly reduced, the epitaxial cost is reduced by one time compared with ordinary GaAs substrates, the yield is high, and the manufacturing cost is low. The improvement of brightness can expand the application range of the wafer, such as the LED lighting field and the laser device field, which need such a super high brightness wafer, and has a wide application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the schemes in the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a structure schematic diagram of a wafer in a wafer preparation process in the embodiments of the present application.

[0020] Figure 2 is a process flow chart of a wafer preparation process in the embodiments of the present application.

[0021] Figure 3 is a structure schematic diagram of a laser chip in a laser device preparation process in the embodiments of the present application.

[0022] 1, P-face electrode; 2, substrate; 3, metal light-reflecting layer; 4, epitaxial layer; 5, N-face electrode; 6, P-type contact layer; 7, P-type AlGaInP upper cladding layer; 8, N-type confinement layer. DETAILED DESCRIPTION

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application; the present application will be described with reference to the drawings and detailed description, and the terminology used in the description and the claims of the present application and the above drawing description are intended to be interpreted by those skilled in the art in the ordinary sense.

[0024] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment.

[0025] In order to make the technical personnel in the art better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings.

[0026] Reference Figure 1 A wafer includes a P-face electrode 1, a substrate 2, a metal light-reflecting layer 3, an epitaxial layer 4, and an N-face electrode 5 arranged in a stack. The substrate 2 is a CuSiC alloy substrate. The epitaxial layer 4 is an AlGaInP epitaxial layer 4 after removal of the original substrate, and is bonded to the metal light-reflecting layer 3.

[0027] Further, the metal light-reflecting layer 3 is a multilayer metal structure, and a bottom layer of the metal light-reflecting layer 3 in contact with the CuSiC alloy substrate comprises a metal material for forming a P-type ohmic contact.

[0028] Further, the metal light-reflecting layer 3 is an AuBe / Au laminated structure, wherein the bottom layer of the metal light-reflecting layer 3 is AuBe, and AuBe is a metal material for forming a P-type ohmic contact; Au is arranged closer to the epitaxial layer 4 than AuBe.

[0029] Further, for preparing the wafer mentioned above, the CuSiC alloy substrate is a single-side polished structure, and the metal reflective layer 3 is formed on the polished surface. The single-side polished structure of the CuSiC alloy substrate provides an atomically flat, clean and defect-free substrate surface for depositing a high-performance metal reflective layer. This directly determines the reflectivity (optical performance) of the metal layer, the contact resistance between the metal and the substrate or epitaxial layer (electrical performance), and the quality of the subsequent bonding interface (mechanical and thermal reliability).

[0030] By the technical solution, the wafer of the application effectively solves the core problems of traditional wafers in terms of light efficiency, heat dissipation, reliability and cost by adopting a unique “CuSiC substrate / metal reflective layer / AlGaInP epitaxial layer without GaAs substrate” composite structure, and significant comprehensive performance improvement is achieved.

[0031] In the first aspect, super-high light extraction efficiency and full-angle reflection can be achieved. The core improvement of the wafer of the application is to completely abandon the light-absorbing GaAs substrate and replace it with a combination of a “metal reflective layer + CuSiC alloy substrate”. The traditional GaAs substrate will strongly absorb the photons (wavelength 645 nm and nearby red light) emitted downward from the active region, and the commonly used distributed Bragg reflector (DBR) can only effectively reflect small-angle incident light (θ<20°). The metal reflective layer (such as Au / AuBe) of the application has a reflectivity of up to 90% or more for the target wavelength band (such as 590-650 nm red light), and its reflection characteristics are close to ideal mirror reflection, with a reflection angle range of nearly 90°, which can effectively reflect almost all the downward emitted photons and emit them from the front of the device. This fundamental change can increase the overall light extraction efficiency by nearly one times compared to the traditional GaAs substrate structure, achieving a “high-brightness” effect.

[0032] In the second aspect, excellent heat management and high-temperature reliability can be achieved. Compared with the traditional GaAs or GaP substrate, CuSiC has extremely high thermal conductivity (usually >300 W / mK) and excellent mechanical strength. When the device is working, the heat generated by the active region can be quickly conducted to the CuSiC substrate and dissipated through the metal reflective layer. This feature brings multiple advantages: Lower operating junction temperature: significantly improves the heat accumulation problem of the device under high-current driving or high-temperature environment.

[0033] Improved power tolerance: allows the device to work stably at higher power, widening its application range in high-power lighting, pumping and other fields.

[0034] Enhanced long-term reliability: lower operating temperature and good thermal stress distribution effectively delay material aging and performance degradation, significantly improving the service life and stability of the device.

[0035] Thirdly, the manufacturing cost can be greatly reduced and the process can be simplified. The structure has a significant cost advantage: Low material cost: CuSiC substrate itself is an industrial material with relatively low price, much lower than GaP single crystal substrate of the same size.

[0036] Reduced epitaxial cost: Since the metal reflective layer can provide efficient and full-angle light reflection, there is no need to grow complex and expensive DBR reflective layer and thick GaP window layer in the AlGaInP epitaxial layer, which simplifies the epitaxial structure and reduces the direct cost of the epitaxial layer.

[0037] Reference Figure 1 and Figure 2 To solve the above technical problems, the application also provides a wafer preparation process for preparing the above wafer, comprising the following preparation steps: S1, preparing a metal reflective layer 3 on the surface of a CuSiC alloy substrate; S2, providing an AlGaInP / GaAs epitaxial wafer with a P-face metal layer; S3, low-temperature alloy bonding the P-face metal layer of the epitaxial wafer with the metal reflective layer 3 on the CuSiC alloy substrate; S4, removing the original GaAs substrate of the epitaxial wafer to form an AlGaInP epitaxial layer 4; S5, making a P-face electrode 1 on the side of the CuSiC alloy substrate away from the epitaxial layer 4, and making an N-face electrode 5 on the surface of the AlGaInP epitaxial layer 4 after removing the GaAs substrate.

[0038] Further, in the step S3, the low-temperature alloy bonding is carried out under the protection of N2 / H2 mixed atmosphere, the bonding temperature of the low-temperature alloy bonding is 250-350℃, for example, it can be 250℃, 300℃ or 350℃, and an axial pressure is applied, the axial pressure is 1-10MPa, which ensures that the bonding surfaces can be fully contacted under the action of temperature and atmosphere, and the atomic diffusion and alloying reaction starts to occur, forming a continuous bonding interface. At the same time, while ensuring the bonding quality, it avoids the problems caused by excessive pressure, such as cracks or dislocations in the AlGaInP epitaxial layer, warping or breaking of the CuSiC substrate or the epitaxial wafer, and excessive extrusion of the metal layer at the bonding interface, flowing into the non-bonding area or changing the preset interface structure.

[0039] Further, the GaAs substrate is removed by wet chemical etching in the step S4, and the etching solution used in the etching process is NH4OH / H2O2 mixed aqueous solution, which has high selectivity to GaAs and very low etching rate to AlGaInP. NH4OH provides OH- Ion, is the main component of GaAs corrosion; H2O2 as an oxidizing agent, and GaAs reaction to generate soluble in alkaline solution of oxide; H2O adjust the corrosion rate and solution stability; The mass fraction of NH4OH is 28%, the mass fraction of H2O2 is 30%, and the volume ratio of NH4OH:H2O2:H2O is 1:(1-2):(20-50). By adjusting the proportion of H2O2, the rate can be fine-tuned. With the increase of the proportion of H2O2, the corrosion rate will first increase and then decrease, and the surface morphology will be affected. The H2O2 proportion range of the application can control better effect. By adjusting the proportion of H2O, the corrosion rate can be significantly changed. The higher the proportion of H2O, the slower the corrosion rate. The H2O2 proportion range of the application can control better uniformity and selectivity. The temperature of the corrosion treatment is 20-30℃. Temperature has a significant effect on corrosion rate. For every 10℃ increase in temperature, the corrosion rate may increase by more than 2 times. High temperature may lead to uneven corrosion or aggravate the slight erosion of AlGaInP epitaxial layer. The temperature of the corrosion treatment of the application can obtain stable and controllable process. The corrosion treatment time is 60-75min, which helps to obtain good corrosion effect.

[0040] After the corrosion is completed, immediately put into a large amount of flowing deionized water to completely terminate the reaction and dilute and wash away the residual corrosion liquid. Then, a standard cleaning process is carried out to remove possible residual organic matter and metal ions on the surface.

[0041] Through the above technical solutions, the low-temperature alloy bonding and selective wet etching processes adopted are compatible with existing semiconductor manufacturing infrastructure, easy to realize the transformation from laboratory to large-scale production, and the industrialization threshold is relatively low. At the same time, the quality and performance stability of the epitaxial material are guaranteed: the CuSiC alloy substrate is introduced by "bonding" rather than "epitaxial growth". The completed epitaxial layer structure is transferred to the CuSiC alloy substrate by low-temperature (such as about 300℃) alloy bonding process, which completely avoids the extreme difficulties of lattice mismatch and high-temperature thermal stress faced by direct epitaxial growth of high-quality III-V compound semiconductors on CuSiC. This makes the epitaxial layer grow on the optimized GaAs substrate to obtain the highest crystal quality and internal quantum efficiency, and then transferred to the high-performance CuSiC substrate in the subsequent process, thereby ensuring the optimal and stable core performance of the light emitting at the source.

[0042] In addition, a compact and robust mechanical structure is formed: after the removal of the brittle and thick GaAs substrate, the main structure of the wafer is composed of the solid CuSiC substrate and the AlGaInP epitaxial layer thereon. This structure has high mechanical strength, strong bending and vibration resistance, and reduces the risk of chip breakage caused by mechanical stress in subsequent chip dicing, packaging and terminal use, thereby improving production yield and product durability.

[0043] With reference to Figure 3 In order to solve the above technical problems, the embodiment of the present application also provides a laser device comprising the wafer, further comprising an N-type confinement layer 8, a P-type AlGaInP upper cladding layer 7 and a P-type contact layer 6, and a P-face electrode 1, a substrate 2, a metal light-reflecting layer 3, the P-type contact layer 6, the P-type AlGaInP upper cladding layer 7, an epitaxial layer 4, the N-type confinement layer 8 and an N-face electrode 5 are sequentially stacked from bottom to top.

[0044] The wafer has the advantages of high luminous efficiency, high yield and low manufacturing cost, and the laser device comprising the wafer also has the same effects.

[0045] In order to solve the above technical problems, the embodiment of the present application also provides a preparation process of a laser device, which is used for preparing the above laser device, and the laser device is a laser chip, and the preparation process comprises the following preparation steps: S1', preparation of the intermediate main body of the wafer: the substrate 2, the metal light-reflecting layer 3 and the epitaxial layer 4 jointly constitute the intermediate main body of the wafer, and the intermediate main body of the wafer is prepared, and specifically comprises the following steps: A multi-layer structure is epitaxially grown on an N-type original substrate (such as GaAs) by using an MOCVD or MBE device, and an AlGaInP / GaAs epitaxial wafer is obtained; The multi-layer structure comprises, from bottom to top, sequentially: N-type substrate: GaAs original substrate (growth substrate, which will be removed later); N-type confinement layer 8: N-type AlGaInP lower cladding layer, which confines carriers and optical fields; Active layer: AlGaInP epitaxial layer 4 (multi-quantum well), which is the core of light emission; P-type AlGaInP upper cladding layer 7: which confines carriers and optical fields; P-type contact layer 6: P-type GaP or high-aluminum-component AlGaInP top layer, which is a window layer or a contact layer, and is used for improving ohmic contact and reducing surface recombination.

[0046] The metal light-reflecting layer 3 is prepared on the surface of the CuSiC alloy substrate (substrate 2); Low-temperature alloy bonding of the P-face metal layer (P-type contact layer 6) of the AlGaInP / GaAs epitaxial wafer to the metal reflective layer 3 on the CuSiC alloy substrate; Removing the GaAs substrate 2 of the epitaxial wafer to form an AlGaInP epitaxial layer 4; An intermediate body of a wafer with a flat surface and complete structure is obtained.

[0047] S2', Ridge waveguide formation: On the epitaxial layer 4 (active layer) of the intermediate body of the wafer, the transverse optical waveguide and current limiting structure of the laser device are defined by photolithography and etching process to form the ridge waveguide. The intermediate body of the wafer provides the "material" and "longitudinal structure" required for the laser device, and the ridge waveguide formation is to create the "transverse structure" for controlling light and current through microfabrication technology, which includes the following steps: (1) Pre-treatment before epitaxial lithography: First cleaning: Thoroughly clean the wafer with organic solvents (acetone, ethanol) and acid / alkali solutions to remove organic matter, particles and metal ion contamination; Second dehydration baking: Remove water vapor from the wafer surface to enhance the adhesion of the photoresist; (2) Ridge etching (first lithography - define ridge waveguide): Photoresist coating: Spin-coat positive photoresist on the surface of the P-type contact layer 6 of the above intermediate body of the wafer, with a thickness of about 1-2 µm; Pre-baking: Evaporate the photoresist solvent and solidify the photoresist film; Exposure: Align and expose on the lithography machine using a "ridge waveguide pattern" mask, which is a series of parallel, specified width stripes; Developing: Dissolve the photoresist in the exposed area with alkaline developer to expose the semiconductor material under the stripes; Post-baking: Hardening (baking the glue), to improve the etching resistance of the photoresist; Etching: Use inductively coupled plasma (ICP) or reactive ion etching (RIE) with Cl2 / BCl3 gas to accurately etch away the P-type AlGaInP upper cladding layer 7 not protected by the photoresist. The etching depth needs to be accurately controlled, for example, etching to a depth of about 0.1-0.3 µm from the active layer to stop, forming a "ridge"; Photoresist removal: Use oxygen plasma ashing or special stripping solution to completely remove the residual photoresist; At this time, a clear ridge waveguide array appears on the wafer surface; (3) PECVD growth of passivation layer: Use plasma enhanced chemical vapor deposition (PECVD) to grow a layer of silicon dioxide (SiO2) or silicon nitride (Si3N4) on the entire wafer surface (including the ridge top and both sides); The effect is: Surface passivation: reduce surface states, lower non-radiative recombination; current confinement: as an insulating layer, force current to inject only from the subsequent windowed area; optical protection: prevent contamination and scratching; (4) 15 µm window lithography (second lithography - define electrode injection window): Glueing / exposure / development: use "P-face electrode window" mask (strip window width about 15 µm, slightly wider than 4 µm ridge to ensure complete coverage of the ridge top and alignment margin), window on the passivation layer; Etching: use buffered hydrofluoric acid wet etching or CF4-based dry etching to remove the passivation layer in the ridge top area, expose the P-type contact layer, and form a current injection channel; Glue removal and cleaning; S3', P-face electrode fabrication: form a designated pattern of P-face electrodes 1 on the side of the substrate 2 away from the epitaxial layer 4, which includes the following steps: (5) P-face electrode evaporation (titanium gold): Metallization: use electron beam evaporation or magnetron sputtering to deposit the following layer structure in sequence: Adhesion layer: includes titanium (Ti) or chromium (Cr), about 20-50 nm; enhances the adhesion of metal to semiconductor; Main conductive layer: includes platinum (Pt) or gold (Au), about 100-200 nm; forms a good ohmic contact.

[0048] Bonding thickening layer: gold (Au), about 200-500 nm, for subsequent wire bonding.

[0049] The overall effect is to form a low-resistance, high-stability ohmic contact electrode on the P-face; (6) Third lithography (define P-face electrode pattern): Glueing / exposure / development: use "P-face electrode pattern" mask (usually a wider strip than the window, with larger bonding pads at both ends) to form a photoresist mask; Wet etching of metal: use a specific acid / alkali solution (such as KI / I2 solution to etch gold, HF / HNO3 to etch titanium) to remove the metal layer not protected by the photoresist, forming independent electrode strips; Glue removal: get patterned P-face electrodes 1; S4', N-face processing and N-face electrode 5 fabrication: process the side of the epitaxial layer 4 away from the P-face electrodes 1 into a smooth back surface, and form N-face electrodes 5 on the back surface, which includes the following steps: (7) N-face thinning: Mechanical grinding: grind the wafer N-face with diamond abrasive to the target thickness (80-150 µm), reduce the series resistance, facilitate heat dissipation and subsequent cleavage; Chemical mechanical polishing: polish the ground surface, remove the damage layer, and obtain a smooth back surface; (8) Evaporate N-face alloy: Metallization: evaporate N-face ohmic contact metal (such as AuGeNi / Au or Ti / Pt / Au) on the back surface of the wafer; Rapid thermal annealing: anneal at about 400-450°C for 10 seconds in a nitrogen atmosphere. Alloy the metal with the N-type semiconductor to form a low-resistance ohmic contact; obtain an epitaxial wafer; S5', bar preparation and cavity surface treatment: slice / dice the obtained epitaxial wafer to divide it into multiple bars, and coat optical films on the sliced / diced cavity surfaces of the bars, specifically including the following steps: (9) Bar dicing: Slicing / dicing: use a precision scribe machine to scribe a deep groove in a direction perpendicular to the ridge waveguide, or use a dicing technique to break the wafer into bars along the natural cleavage plane of the crystal; Bar: each bar contains tens to hundreds of laser units (chips) arranged side by side, and the width is the cavity length of the final chip (250 µm-2000 µm); (10) Evaporate cavity surface film: Cleaning: clean the end surface of the diced bar in an ultra-clean environment.

[0050] Coating: in a high-vacuum coating machine, use electron beam evaporation to coat optical films on the two sliced / diced cavity surfaces of the bar: Back surface (high-reflection film HR): evaporate SiO2 / TiO2 multilayer film alternately, with a reflectivity >95%; Front surface (antireflection film AR): reflectivity about 1-10%, to output high-efficiency laser; S6', die separation and test packaging: separate the bar coated with optical films by dicing / cutting, to obtain individual laser devices, and test and package the laser devices, specifically including the following steps: (11) Die dicing / cutting: Secondly scribe or dice the bar coated with films in a direction parallel to the ridge waveguide (i.e., between individual laser chips), to separate into individual independent laser chips; (12) Pin testing: In-situ testing / pin testing: use a precision probe station to apply a pulsed current to the electrodes of each laser chip, quickly test its threshold current, slope efficiency, output power, and other key parameters, and preliminarily sort according to performance; (13) Cleaning, counting, packaging, and warehousing, to obtain laser chip finished products: Cleaning: remove the debris left over from dicing; Microscopy: check for appearance defects under a microscope; Counting and grading: according to the test data, the laser chips are divided into different boxes according to the performance level.

[0051] Vacuum packaging: put into anti-static, nitrogen-filled or vacuum packaging bag, mark clearly, store in warehouse waiting for packaging, finally get the finished laser chip.

[0052] Further, in the step S2, the specified width of the ridge waveguide is controlled to 2.5-5.0 μm by a photolithography process. The ridge waveguide corresponds to the "channel" of light. When this channel (width) is very narrow, it can only accommodate the most basic light wave mode for stable transmission. Wider light wave modes are suppressed because they cannot form a stable light field distribution in the narrow waveguide.

[0053] The width of the ridge waveguide is controlled to 2.5-5.0 μm, which balances single mode and low loss. High beam quality can be obtained, and the output laser spot is a regular circular or elliptical Gaussian spot without distortion. The far-field divergence angle is small and symmetrical, the spot diffuses slowly during propagation, has good directivity, and is easy to couple with single-mode fiber with a coupling efficiency of more than 70%. The spectral purity is high, the spectral linewidth is narrower; the threshold current is significantly reduced, which can be reduced by several to tens of milliamperes compared with the wide ridge structure; the slope efficiency is higher, and the optical power generated per unit current is larger. It is more suitable for low-power applications, such as for devices that consume electronics (laser radar, sensing) or need to work for a long time.

[0054] If the ridge is too wide, it will allow multiple transverse modes to oscillate simultaneously, resulting in poor beam quality, spot distortion, and huge fiber coupling loss. If the ridge is too narrow, although the mode is more restricted, it will bring the side effects of too strong light field restriction, part of the light field will "overflow" to the flat plate area on both sides, causing additional optical loss; and the series resistance increases sharply, the current channel cross-sectional area is too small, resulting in voltage rise, and the electrical-optical conversion efficiency is actually decreased.

[0055] The content of the present application will be described in more detail and further illustrated by specific embodiments, but these embodiments are by no means limiting to the present application.

[0056] Reference Figure 1 and Figure 2 The embodiment provides a wafer, which comprises the following preparation steps: S1, preparing a metal light-reflecting layer 3 on the polished surface of a single-side polished CuSiC alloy substrate, the metal light-reflecting layer 3 is an AuBe / Au laminated structure, the Au is arranged close to the epitaxial layer 4, and the AuBe is located between the CuSiC alloy substrate and the Au; S2, providing an AlGaInP / GaAs epitaxial wafer with a P-face metal layer; S3, alloy bonding the P face metal layer of the epitaxial wafer and the metal reflective layer 3 on the CuSiC alloy substrate at 300℃, and applying axial pressure, the axial pressure being 5MPa; S4, removing the GaAs substrate by wet chemical etching treatment to form an AlGaInP epitaxial layer 4. The etching solution used in the etching treatment is an NH4OH / H2O2 mixed aqueous solution, the mass fraction of the NH4OH being 28%, the mass fraction of the H2O2 being 30%, and the volume ratio of NH4OH:H2O2:H2O being 1:1.5:30; the etching treatment temperature is 25℃, and the etching treatment time is 60min.

[0057] After the etching is completed, the wafer is immediately and quickly put into a large amount of flowing deionized water to completely terminate the reaction and dilute and flush away the residual etching solution. Subsequently, a standard cleaning process is performed to remove possible residual organic matter and metal ions on the surface.

[0058] S5, making a P face electrode 1 on the side of the CuSiC alloy substrate away from the epitaxial layer 4, and making an N face electrode 5 on the surface of the AlGaInP epitaxial layer 4 after the GaAs substrate is removed, to obtain a wafer.

[0059] Since the mirror surface structure of the metal reflective layer does not need a thick GaP window layer and a DBR layer, the consumption of epitaxial material can be greatly reduced, and the epitaxial cost is reduced by one half compared with that of a common GaAs substrate. The increase in brightness can expand the application range and increase the product's superior rate, and the average sales unit price of such a wafer is increased by 50% compared with that of a traditional wafer, and the economic benefits are very significant.

[0060] The AlGaInP / Au / AuBe / CuSiC mirror surface substrate wafer is subjected to wavelength, brightness, voltage, saturation current, and reverse voltage tests according to the standard, and the test results are shown in Table 1 below:

[0061] Wafer Comparative Example 1 The AlGaInP / GaAs substrate wafer of the prior art is selected as Comparative Example 1 of the wafer of the present application, and the AlGaInP / GaAs substrate wafer is subjected to wavelength, brightness, voltage, saturation current, and reverse voltage tests according to the standard, and the test results are shown in Table 2 below:

[0062] From the comparison of Tables 1 and 2 above, it can be seen that the wafer of the present application has excellent comprehensive performance.

[0063] Meanwhile, the wafer of the present application has the following advantages: The use of CuSiC substrate material can improve the mechanical strength of the die, while the metal reflective layer with good thermal conductivity can provide light reflection at all angles; it improves thermal stability and can achieve high ambient temperature and high current operation; in addition, CuSiC substrate material is inexpensive, which can reduce costs; the bonding process between the substrate and AlGaInP material does not require high temperature, which can ensure the stability of the epitaxial material performance.

[0064] Reference Figure 3 This embodiment provides a laser device, which is a laser chip. The laser chip includes the following fabrication steps: S1', Epitaxial wafer preparation: Using MOCVD equipment, a multilayer structure is epitaxially grown on N-type substrate 2 (GaAs) to obtain AlGaInP / GaAs epitaxial wafer; The multi-layered structure, from bottom to top, includes: N-type substrate: GaAs substrate (growth substrate, which will be removed later); N-type confinement layer 8: namely, the N-type AlGaInP lower cladding layer, which confines charge carriers and optical field; Active layer: namely AlGaInP epitaxial layer 4 (multiple quantum wells), which serves as the core for luminescence; 7. Cladding layer on P-type AlGaInP: confines charge carriers and optical field; P-type contact layer 6: namely, the top layer of P-type GaP component AlGaInP, which serves as a window layer or contact layer to improve ohmic contact and reduce surface recombination.

[0065] A metal reflective layer 3 is prepared on the polished surface of a single-sided polished CuSiC alloy substrate. The metal reflective layer 3 is an AuBe / Au stacked structure, wherein the Au phase is disposed closer to the epitaxial layer 4 than the AuBe phase, and the AuBe phase is located between the CuSiC alloy substrate and the Au phase. The AlGaInP / GaAs epitaxial wafer is flipped over, and the P-side metal layer (P-type contact layer 6) of the AlGaInP / GaAs epitaxial wafer is alloy bonded to the metal reflective layer 3 on the CuSiC alloy substrate at a low temperature of 300°C, and an axial pressure of 5 MPa is applied. A wet chemical etching process was used to remove the GaAs substrate and form an AlGaInP epitaxial layer. The etching solution used was a mixed aqueous solution of NH4OH / H2O2, wherein the mass fraction of NH4OH was 28%, the mass fraction of H2O2 was 30%, and the volume ratio of NH4OH:H2O2:H2O was 1:1.5:30; the etching temperature was 25°C, and the etching time was 60 min.

[0066] After etching, immediately put the wafer into a large amount of flowing deionized water to completely terminate the reaction and dilute and flush away the residual etching solution. Then, perform a standard cleaning process to remove possible residual organic matter and metal ions on the surface, obtaining a piece of epitaxial wafer with a smooth surface and complete structure.

[0067] S2', ridge waveguide formation: (1) Pre-etching treatment: First cleaning: use organic solvents (acetone) and acid solutions to thoroughly clean the wafer and remove organic matter, particles, and metal ion contamination; Second dehydration baking: remove water vapor on the wafer surface to enhance the adhesion of the photoresist; (2) Etching 4µm ridge (first photoetching - define ridge waveguide): Photoresist coating: spin-coat positive photoresist with a thickness of about 1-2µm; Pre-baking: volatilize the photoresist solvent and solidify the photoresist film; Exposure: use a "ridge waveguide pattern" mask to align and expose on the photoetching machine, and the pattern is a series of parallel strips with a width of 4µm; Development: use alkaline developer to dissolve the photoresist in the exposed area, exposing the semiconductor material under the strips; Post-baking: harden the film (bake the glue), and improve the etching resistance of the photoresist; Etching: use inductively coupled plasma (ICP) or reactive ion etching (RIE) and Cl2 gas to accurately etch away the P-type AlGaInP upper cladding layer not protected by the photoresist, and the etching depth needs to be accurately controlled, for example, etching to about 0.2µm away from the active layer to stop, forming a "ridge"; Photoresist removal: use oxygen plasma ashing or special stripping solution to completely remove the residual photoresist; at this time, the wafer surface appears a clear ridge waveguide array; (3) PECVD growth of passivation layer: Use plasma enhanced chemical vapor deposition (PECVD) to grow a layer of silicon dioxide (SiO2) or silicon nitride (Si3N4) on the entire wafer surface (including the ridge top and both sides); (4) Photoetching 15µm window (second photoetching - define electrode injection window): Photoresist coating / exposure / development: use a "P-face electrode window" mask (the strip window width is about 15µm, slightly wider than the 4µm ridge, to ensure complete coverage of the ridge top and have an alignment margin), to open a window on the passivation layer; Etching: use buffered hydrofluoric acid wet etching to remove the passivation layer in the ridge top area, exposing the P-type contact layer and forming a current injection channel; Photoresist removal and cleaning; S3', P-face electrode 1 fabrication: (5) Evaporate P-face electrode 1 (TiAu): Metallization: Electron beam evaporation, deposit the following layer structure in sequence: Adhesion layer: Ti or Cr, about 30 nm; Main conductive layer: Pt or Au, about 150 nm; Bonding thickening layer: Au, about 350 nm.

[0068] (6) Third photoetching (define P-face electrode pattern): Glue coating / exposure / development: Use "P-face electrode pattern" mask to form photoresist mask; Wet etching metal: Use specific acid / alkali solution (such as KI / I2 solution to etch gold, HF / HNO3 to etch titanium), remove the metal layer not protected by photoresist, form independent electrode strips; Glue removal: Get patterned P-face electrode 1; S4', substrate processing and N-face electrode 5 production: (7) Thin N-face: Mechanical grinding: Grind the wafer N-face with diamond grinding plate to the target thickness of 100 µm; Chemical mechanical polishing: Polish the ground surface to eliminate damage layer and obtain smooth back surface; (8) Evaporate N-face alloy: Metallization: Evaporate N-face ohmic contact metal (AuGeNi / Au) on the wafer back surface; Rapid thermal annealing: Anneal at about 400 ℃ for 10 seconds in nitrogen atmosphere. Alloy the metal with N-type semiconductor to form low-resistance ohmic contact; get epitaxial wafer plate.

[0069] S5', bar preparation and cavity surface treatment: (9) Bar cleavage: Scribing / cleaving: Use a precision scribing machine to scribe a deep groove perpendicular to the ridge waveguide on the prepared epitaxial wafer plate, or use cleaving technology to break the wafer along the natural cleavage plane of the crystal into bars; Bar: Each bar contains 80 laser units (chips) arranged side by side, and the width is the cavity length of the final chip (1000 µm); (10) Evaporate cavity surface film: Cleaning: Clean the end face of the cleaved bar in ultra-clean environment.

[0070] Coating: In a high vacuum coating machine, use electron beam evaporation to coat optical film on both cleaved cavity surfaces of the bar: Back surface (high reflection film HR): Evaporate SiO2 / TiO2 multilayer film alternately, reflectivity > 95%; Front end surface (anti-reflection film AR): reflectivity of about 1-10%, to output laser with high efficiency; S6', die separation and test packaging: (11) Die cleaving / dicing: The film-coated bar is subjected to a second dicing or cleaving along a direction parallel to the ridge waveguide (i.e. between the individual laser chips), to separate into individual laser chips; (12) Probing: In-situ testing / probing: using a precision probe station, a pulsed current is applied to the electrodes of each laser chip to quickly test its threshold current, slope efficiency, output power and other key parameters, and a preliminary sorting is performed according to the performance; (13) Cleaning, counting, packaging, and warehousing, to obtain laser chip products: Cleaning: removing dicing debris; Microscopy: checking for appearance defects under a microscope; Counting and grading: according to the probing data, the laser chips are divided into different bins according to the performance level.

[0071] Vacuum packaging: placed in an anti-static, nitrogen-filled or vacuum packaging bag, with clear labeling, stored in a warehouse for packaging, and finally obtained ridge waveguide structure 645nm laser chip products.

[0072] The threshold current, slope efficiency and output power of the above laser chips were tested according to the standard, and the test results are shown in Table 3 below:

[0073] Comparative Example 1 of the Laser Device The laser chip of the prior art GaAs substrate, i.e. AlGaInP / GaAs substrate laser chip, was selected as Comparative Example 1 of the laser device of the present application. The threshold current, slope efficiency and output power of the AlGaInP / GaAs substrate laser chip were tested according to the standard, and the test results are shown in Table 4 below:

[0074] From the comparison of Tables 3 and 4 above, it can be seen that the laser chip of the present application has excellent overall performance.

[0075] The design and manufacture of the ridge waveguide structure 645nm chip have very high requirements on the process, and the integrity of the structure and the guarantee ability of the process are the key to good laser chips.

[0076] For the photoetching process, the ridge waveguide structure 645nm laser chip requires high quality photoetching, which requires complete pattern, accurate size, neat edge and steep line. The photoetching quality determines the shape of the ridge, affects the longitudinal and lateral structure of the device to meet the design requirements, and affects the threshold current and other electrical parameters of the device, which is mainly determined by the photoetching level.

[0077] The photoetching process involves many factors such as reagents, equipment, environment, process and personnel. From the epitaxial wafer to the glue coating, pre-baking, exposure, development, film hardening, etching and degumming, cleaning each work link should be strictly operated according to the procedure. Any mistake in any link will cause serious quality problems.

[0078] For the ridge waveguide structure 645nm laser chip, the cavity cleaving technology and the cavity coating technology are particularly important. Laser must have a pair of very complete resonant cavity to form laser oscillation. The natural cleaving surface of the semiconductor laser provides a resonant cavity for laser amplification. In order to improve the output power, high reflection film and antireflection film are deposited at both ends of the laser, which greatly improves the reflectivity.

[0079] Obviously, the above described embodiments are only part of the embodiments of the present application, not all the embodiments, and the preferred embodiments of the present application are given in the drawings, but do not limit the patent scope of the present application. The present application can be realized in many different forms, and on the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for part of the technical features. Any equivalent structure made by using the content of the specification and drawings, directly or indirectly used in other related technical fields, is also within the scope of the patent protection of the present application.

Claims

1. A wafer, characterized in that, It includes a stacked P-side electrode, a substrate, a metallic reflective layer, an epitaxial layer, and an N-side electrode; The substrate is a CuSiC alloy substrate; The epitaxial layer is an AlGaInP epitaxial layer after the original substrate has been removed, and it is bonded to the metal reflective layer.

2. The wafer according to claim 1, characterized in that, The metal reflective layer has a multi-layer metal structure, and the bottom layer of the metal reflective layer in contact with the CuSiC alloy substrate contains a metal material for forming a P-type ohmic contact.

3. The wafer according to claim 2, characterized in that, The metallic reflective layer has an AuBe / Au stack structure, with the Au layer positioned closer to the epitaxial layer than the AuBe layer.

4. The wafer according to any one of claims 1-3, characterized in that, The CuSiC alloy substrate has a single-sided polished structure, and the metal reflective layer is formed on the polished surface.

5. A wafer fabrication process, characterized in that, The method for preparing the wafer according to any one of claims 1-4 comprises the following preparation steps: S1. Prepare a metallic reflective layer on the surface of a CuSiC alloy substrate; S2. Provide an AlGaInP / GaAs epitaxial wafer with a P-plane metal layer; S3. The P-side metal layer of the epitaxial wafer is bonded to the metal reflective layer on the CuSiC alloy substrate using a low-temperature alloy bonding process. S4. Remove the original GaAs substrate of the epitaxial wafer to form an AlGaInP epitaxial layer; S5. A P-side electrode is fabricated on the side of the CuSiC alloy substrate away from the epitaxial layer, and an N-side electrode is fabricated on the surface of the AlGaInP epitaxial layer after the GaAs substrate has been removed.

6. The wafer fabrication process according to claim 5, characterized in that, The cryogenic alloy bonding is carried out under a N2 / H2 mixed atmosphere, the bonding temperature of the cryogenic alloy bonding is 250-350℃, and an axial pressure of 1-10MPa is applied.

7. The wafer fabrication process according to claim 5, characterized in that, The method for removing the original GaAs substrate of the epitaxial wafer is wet chemical etching; the etching solution used for the etching process is a mixed aqueous solution of NH4OH / H2O2, the volume ratio of NH4OH:H2O2:H2O is 1:(1-2):(20-50), the etching temperature is 20-30℃, and the etching time is 60-75min.

8. A laser device, characterized in that, Includes the wafer as described in any one of claims 1-4.

9. A fabrication process for a laser device, characterized in that, The preparation method for the laser device according to claim 8, wherein the laser device is a laser chip, includes the following preparation steps: S1' Preparation of the intermediate body of the wafer: The substrate, the metal reflective layer and the epitaxial layer together constitute the intermediate body of the wafer, and the intermediate body of the wafer is prepared. S2', Ridge waveguide formation: On the epitaxial layer of the central body of the wafer, the lateral optical waveguide and current confinement structure of the laser device are defined by photolithography and etching processes to form the ridge waveguide; S3', P-side electrode fabrication: A P-side electrode with a specified pattern is formed on the side of the substrate away from the epitaxial layer; S4', N-side processing and N-side electrode fabrication: The side of the epitaxial layer away from the P-side electrode is processed into a smooth and flat back surface, and an N-side electrode is formed on the back surface to obtain an epitaxial crystal plate. S5', Bar preparation and cavity surface treatment: The prepared epitaxial wafer is diced / cleaved to divide the epitaxial wafer into multiple bars, and an optical thin film is deposited on the cavity surface of the diced / cleaved bars; S6', Die Separation: The laser strips coated with optical thin films are cleaved / sliced ​​to separate them and obtain individual laser devices.

10. The fabrication process of the laser device according to claim 9, characterized in that, In step S2', the width of the ridge waveguide is controlled to be 2.5-5.0 μm by photolithography.

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