Multilayer ceramic capacitor and method of manufacturing same

Abstract

The invention provides a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes: a capacitor body including a plurality of dielectric layers and a plurality of inner electrode layers stacked with the dielectric layers interposed between the plurality of inner electrode layers; and an outer electrode disposed on an outer surface of the capacitor body, in which the inner electrode layer includes an inner region and an interface region disposed on at least one surface of the inner region in a stacking direction and including an interface with the dielectric layer, the inner region and the interface region including germanium (Ge), the average content of germanium (Ge) in the interface region is higher than the average content of germanium (Ge) in the inner region.

Description

Technical Field

[0001] This disclosure relates to a multilayer ceramic capacitor and a method for manufacturing the same. Background Technology

[0002] Electronic components that use ceramic materials include capacitors, inductors, piezoelectric elements, varistors, and thermistors. Among these ceramic-based electronic components, multilayer ceramic capacitors (MLCCs) are used in various electronic devices due to their advantages such as small size, high capacitance, and ease of installation.

[0003] For example, a multilayer ceramic capacitor (MLCC) can be a chip capacitor mounted on a printed circuit board of various electronic products, such as imaging devices (e.g., liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diodes (OLEDs), etc.), computers, personal portable terminals, smartphones, etc.) for charging or discharging from them.

[0004] Recently, with the development of electronic devices and autonomous vehicles, the demand for miniaturizing and increasing the capacitance of multilayer ceramic capacitors has been growing. To achieve higher capacitance within the same volume, it is necessary to thin the dielectric layer and inner electrode layer. However, thinning the dielectric layer and inner electrode layer may increase the electric field strength per unit area, leading to a deterioration in reliability. Summary of the Invention

[0005] The embodiment provides a multilayer ceramic capacitor with excellent reliability.

[0006] Another embodiment provides a method for manufacturing a multilayer ceramic capacitor.

[0007] An embodiment provides a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: a capacitor body including a plurality of stacked dielectric layers and a plurality of inner electrode layers, wherein the dielectric layers are located between adjacent inner electrode layers; and an outer electrode disposed on the outer surface of the capacitor body, wherein at least one of the plurality of inner electrode layers includes an internal region and an interface region, the interface region being disposed on at least one surface of the internal region in a stacking direction, the interface region including an interface with an adjacent dielectric layer among the plurality of dielectric layers, the internal region and the interface region comprising germanium (Ge), and the average content of germanium (Ge) in the interface region being higher than the average content of germanium (Ge) in the internal region.

[0008] The ratio of the average content of germanium (Ge) in the interface region to the average content of germanium (Ge) in the inner region may be greater than about 1 and less than or equal to about 5.

[0009] The interface region can be a region with a depth of 2 nm extending from the interface of the adjacent dielectric layer to the interior of the at least one inner electrode layer.

[0010] In transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) images, the interface region may have the maximum molar percentage of germanium (Ge) when a line segment from a point in the at least one inner electrode layer to a point in the adjacent dielectric layer is analyzed.

[0011] The interface region may also include germanium oxide (GeO2).

[0012] The internal region and the interface region may also include nickel (Ni).

[0013] In transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) images, the internal region may have the maximum molar percentage of nickel (Ni) when a line segment is analyzed from a point in the adjacent dielectric layer to a point in the at least one inner electrode layer.

[0014] In a transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) image, when a line segment is analyzed from a point in the adjacent dielectric layer to a point in the at least one inner electrode layer, the interface region can be a region extending 2 nm from the point where the molar percentage of nickel (Ni) is 1 / 3 of the maximum molar percentage of nickel (Ni) into the interior of the at least one inner electrode layer.

[0015] Based on 100 moles of nickel (Ni) in the interface region, the average content of germanium (Ge) in the interface region can be from about 0.4 moles to about 12 moles.

[0016] The interface region may also include at least one selected from titanium (Ti) and barium (Ba).

[0017] Based on 100 moles of nickel (Ni) in the inner region, the average content of germanium (Ge) in the inner region can be from about 0.2 moles to about 10 moles.

[0018] The thickness of the interface region can be from about 0.05% to about 3% of the total thickness of the at least one inner electrode layer.

[0019] The plurality of dielectric layers may include barium (Ba), titanium (Ti), and germanium (Ge).

[0020] The average thickness of the at least one inner electrode layer can be from about 0.1 μm to about 2 μm.

[0021] The average thickness of at least one of the plurality of dielectric layers may be from about 0.2 μm to about 10 μm.

[0022] Another embodiment provides a method for manufacturing a multilayer ceramic capacitor, the method comprising: mixing nickel (Ni) and germanium (Ge) based raw materials to prepare a conductive paste; manufacturing a dielectric green sheet from a dielectric paste, and coating the conductive paste on the surface of the dielectric green sheet to form a conductive paste layer; stacking a plurality of the dielectric green sheets on which the conductive paste layer is formed to manufacture a dielectric green sheet stack; firing the dielectric green sheet stack to manufacture a capacitor body including a dielectric layer and an inner electrode layer; and forming an outer electrode on the outer surface of the capacitor body, wherein the inner electrode layer includes an internal region and an interface region, the interface region being disposed on at least one surface of the internal region in a stacking direction, the interface region including an interface with the dielectric layer, the internal region and the interface region comprising germanium (Ge), and the average content of germanium (Ge) in the interface region being higher than the average content of germanium (Ge) in the internal region.

[0023] The germanium (Ge)-based raw material may include at least one selected from germanium (Ge), germanium oxide (GeO2), and Ni-Ge alloys.

[0024] Based on 100 moles of nickel (Ni), the germanium (Ge)-based raw material can be mixed with about 0.3 moles to about 10 moles of germanium (Ge).

[0025] Available in approximately 10 -12 atm to approximately 10 -8 Firing is performed under oxygen partial pressure conditions atm.

[0026] In another embodiment, a method for manufacturing a multilayer ceramic capacitor includes: mixing a barium titanate-based compound with a germanium (Ge)-based raw material to prepare a dielectric paste; manufacturing a dielectric green sheet from the dielectric paste and printing a conductive paste on the surface of the dielectric green sheet to form a conductive paste layer; stacking a plurality of the dielectric green sheets on which the conductive paste layer is formed to manufacture a dielectric green sheet stack; firing the dielectric green sheet stack to manufacture a capacitor body including a dielectric layer and an inner electrode layer; and forming an outer electrode on the outer surface of the capacitor body, wherein the inner electrode layer includes an internal region and an interface region, the interface region being disposed on at least one surface of the internal region in a stacking direction, the interface region including an interface with the dielectric layer, the internal region and the interface region comprising germanium (Ge), and the average content of germanium (Ge) in the interface region being higher than the average content of germanium (Ge) in the internal region.

[0027] An embodiment provides a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: a capacitor body including a plurality of stacked dielectric layers and a plurality of inner electrode layers, wherein the dielectric layers are located between adjacent inner electrode layers; and an outer electrode disposed on the outer surface of the capacitor body, wherein at least one of the plurality of inner electrode layers includes an internal region and an interface region, the interface region being disposed on at least one surface of the internal region in a stacking direction, the interface region including an interface with an adjacent dielectric layer among the plurality of dielectric layers, the internal region and the interface region comprising both germanium (Ge) and nickel (Ni), and based on 100 moles of nickel (Ni) in the interface region, the average content of germanium (Ge) in the interface region is from 0.4 moles to 12 moles.

[0028] The average content of germanium (Ge) in the interface region may differ from the average content of germanium (Ge) in the inner region.

[0029] The interface region can be a region with a depth of 2 nm extending from the interface of the adjacent dielectric layer to the interior of the at least one inner electrode layer.

[0030] The average content of germanium (Ge) in the interface region may be higher than the average content of germanium (Ge) in the inner region.

[0031] Another embodiment provides a method for manufacturing the multilayer ceramic capacitor disclosed herein. The method includes: mixing nickel (Ni) with germanium oxide (GeO2) to prepare a conductive paste; manufacturing a dielectric green sheet from a dielectric paste, and coating the surface of the dielectric green sheet with the conductive paste to form a conductive paste layer; stacking a plurality of the dielectric green sheets on which the conductive paste layer is formed to manufacture a dielectric green sheet stack; firing the dielectric green sheet stack to manufacture the capacitor body; and forming the external electrode on the outer surface of the capacitor body.

[0032] The firing process can be carried out under conditions of hydrogen volume concentration of less than or equal to 1.0% and temperature of less than or equal to 1300°C.

[0033] Available in 10 -12 atm to 10 -8 Firing is performed under oxygen partial pressure conditions atm.

[0034] Based on 100 moles of nickel (Ni), germanium oxide (GeO2) can be mixed with 0.3 to 10 moles of germanium (Ge).

[0035] An embodiment provides a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: a capacitor body including a plurality of stacked dielectric layers and a plurality of inner electrode layers, wherein the dielectric layers are located between adjacent inner electrode layers; and an outer electrode disposed on the outer surface of the capacitor body, wherein at least one of the plurality of inner electrode layers includes an internal region and an interface region, the interface region being disposed on at least one surface of the internal region in a stacking direction, the interface region including an interface with an adjacent dielectric layer among the plurality of dielectric layers, the internal region and the interface region comprising germanium (Ge), and the average content of germanium (Ge) in the interface region being different from the average content of germanium (Ge) in the internal region.

[0036] The inner region and the interface region may further include nickel (Ni), and based on 100 moles of nickel (Ni) in the interface region, the average content of germanium (Ge) in the interface region may be from 0.4 moles to 12 moles, and based on 100 moles of nickel (Ni) in the inner region, the average content of germanium (Ge) in the inner region may be from 0.2 moles to 10 moles.

[0037] The ratio of the average content of germanium (Ge) in the interface region to the average content of germanium (Ge) in the inner region can be greater than 1 and less than or equal to 5.

[0038] The interface region can be a region with a depth of 2 nm extending from the interface of the adjacent dielectric layer to the interior of the at least one inner electrode layer.

[0039] The multilayer ceramic capacitor according to the embodiment has improved reliability due to its high interface resistance. Attached Figure Description

[0040] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0041] Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'.

[0042] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II'.

[0043] Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure of the capacitor body.

[0044] Figure 5 Ellingham diagrams for nickel (Ni) and germanium (Ge) are shown.

[0045] Figure 6 It is based on the transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) surface scan analysis of the effective region in Example 5.

[0046] Figure 7 It is based on the transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) surface scan analysis of the effective region in Example 5.

[0047] Figure 8 yes Figure 7 Energy dispersive spectroscopy (EDS) line analysis diagram of the straight segment. Detailed Implementation

[0048] The present disclosure will now be described in detail with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. The drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In the drawings, some components are exaggerated, omitted, or shown schematically, and the dimensions of each component do not perfectly reflect actual dimensions.

[0049] The accompanying drawings are intended only to facilitate understanding of the embodiments disclosed in this specification, and it will be understood that the technical concepts disclosed herein are not limited to the drawings, and all variations, equivalents or alternatives within the scope of the technical concepts of this disclosure are included within the scope of this disclosure.

[0050] Although terms such as "first," "second," etc., are used to describe various components, the component is not limited by these terms. These terms are only used to distinguish one component from another.

[0051] Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be an intermediate element present. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element present. Additionally, when an element is referred to as being "on" or "above" a reference element, it may be located "above" or "below" the reference element, and does not necessarily mean that it is located "on" or "above" the reference element in a direction opposite to the direction of gravity.

[0052] Throughout this specification, the terms “comprising” or “having” are intended to specify the presence of the stated features, quantities, steps, operations, constituent elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, constituent elements, components, and / or combinations thereof. Therefore, unless explicitly stated otherwise, the words “comprising” and variations such as “including” or “having” will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0053] Furthermore, throughout the specification, the phrase "in plan view" or "on a plane" indicates the target portion as viewed from the top, and the phrase "in section view" or "on a section" indicates the section formed by vertically cutting the target portion as viewed from the side.

[0054] Throughout this specification, the term "connection" may mean not only a direct connection between two or more constituent elements, but also an indirect connection between two or more constituent elements through another constituent element, a physical and / or electrical connection between two or more constituent elements, or two or more constituent elements that are represented by different names according to their location or function but are integrated as one unit.

[0055] In the following text, reference will be made to Figures 1 to 4 A multilayer ceramic capacitor according to an embodiment is described.

[0056] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'. Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II', and Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure of the capacitor body.

[0057] Figures 1 to 4 The L-axis, W-axis, and T-axis directions shown represent the length, width, and thickness directions of the capacitor body 110, respectively. Here, the thickness direction (T-axis) can be perpendicular to the wide surface (main surface) of the sheet assembly; for example, it can be used as the same concept as the stacking direction along which the stacked dielectric layers 111 are aligned. The length direction (L-axis) can be parallel to the wide surface (main surface) of the sheet assembly and can be approximately perpendicular to the thickness direction (T-axis). For example, the length direction (L-axis) can be the direction along which the first external electrode 131 and the second external electrode 132 are positioned relative to each other. The width direction (W-axis) can be parallel to the wide surface (main surface) of the sheet assembly and can be approximately perpendicular to both the thickness direction (T-axis) and the length direction (L-axis). The length of the sheet assembly in the length direction (L-axis) can be longer than its width in the width direction (W-axis).

[0058] Reference Figures 1 to 4According to an embodiment, the multilayer ceramic capacitor 100 includes a capacitor body 110 and external electrodes 131 and 132 disposed on the outer surface of the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposite ends of the capacitor body 110 in the longitudinal direction (L-axis direction).

[0059] For example, the capacitor body 110 may have a generally hexahedral shape.

[0060] For ease of description of the embodiments, the two surfaces of the capacitor body 110 that are opposite to each other in the thickness direction (T-axis direction) are referred to as the first surface and the second surface, the two surfaces of the capacitor body 110 that are connected to the first surface and the second surface and are opposite to each other in the length direction (L-axis direction) are referred to as the third surface and the fourth surface, and the two surfaces of the capacitor body 110 that are connected to the first surface and the second surface, connected to the third surface and the fourth surface and are opposite to each other in the width direction (W-axis direction) are referred to as the fifth surface and the sixth surface.

[0061] As an example, the first surface (the lower surface of the capacitor body 110) can be a mounting surface. Alternatively, the first to sixth surfaces can be flat, but the embodiment is not limited to this. For example, the first to sixth surfaces can be curved surfaces with a convex central portion, and the edges of each surface (the boundaries between the surfaces) can be rounded.

[0062] The shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 are not limited to the shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 shown in the accompanying drawings of the embodiment.

[0063] The capacitor body 110 includes a plurality of dielectric layers 111 and a plurality of internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and a first internal electrode layer 121 and a second internal electrode layer 122, the first internal electrode layer 121 and the second internal electrode layer 122 are alternately arranged in the thickness direction (T-axis direction), and the dielectric layer 111 is located between the first internal electrode layer 121 and the second internal electrode layer 122.

[0064] At this point, the adjacent dielectric layers 111 of the capacitor body 110 can be integrated to such an extent that the boundaries between them are difficult to identify without using a scanning electron microscope (SEM).

[0065] The capacitor body 110 may include an effective area and coverage areas 112 and 113.

[0066] The effective region is the area where the dielectric layer 111 and the inner electrode layers 121 and 122 are alternately disposed in the thickness direction (T-axis direction), which contributes to the capacitance of the multilayer ceramic capacitor 100. Specifically, the effective region may be the area where the first inner electrode layer 121 and the second inner electrode layer 122 are stacked on top of each other along the thickness direction (T-axis direction).

[0067] Cover regions 112 and 113 are thickness-direction edges and can be respectively disposed on the upper and lower surfaces of the effective region in the thickness direction (T-axis direction). Cover regions 112 and 113 can be a single dielectric layer or two or more dielectric layers stacked on the upper and lower surfaces of the effective region, respectively.

[0068] Additionally, the capacitor body 110 may also include a side edge region.

[0069] The side edge region is the edge portion in the width direction and can be respectively provided on the side surfaces of the effective region that are opposite to each other in the width direction (W-axis direction) (i.e., on the surfaces corresponding to the fifth and sixth surfaces). The side edge region can be formed as follows: when a conductive paste for the inner electrode layer is coated on the surface of the dielectric green sheet, the conductive paste is only coated on a portion of the surface of the dielectric green sheet, and not on both sides of the surface of the dielectric green sheet in the width direction. Then the obtained dielectric green sheets are stacked and fired, but the formation method is not limited to this.

[0070] Coverage areas 112 and 113, as well as side edge areas, are used to prevent damage to the first inner electrode layer 121 and the second inner electrode layer 122 due to physical stress and / or chemical stress.

[0071] Each of the inner electrode layer, dielectric layer, and outer electrode is described in detail below.

[0072] Inner electrode layer The inner electrode layers 121 and 122 (i.e., the first inner electrode layer 121 and the second inner electrode layer 122) are electrodes with different polarities and are alternately arranged to be opposite each other along the T-axis direction with the dielectric layer 111 between them, and one end of the first inner electrode layer 121 and one end of the second inner electrode layer 122 can be exposed through the third surface and the fourth surface of the capacitor body 110, respectively.

[0073] The first inner electrode layer 121 and the second inner electrode layer 122 are electrically insulated from each other by a dielectric layer 111 disposed between them.

[0074] One end of the first inner electrode layer 121 and one end of the second inner electrode layer 122, which are alternately exposed through the third and fourth surfaces of the capacitor body 110, can be electrically connected to the first outer electrode 131 and the second outer electrode 132, respectively.

[0075] Reference Figure 2 According to the embodiment, the inner electrode layers 121 and 122 may include internal regions 10 and 30 and interface regions 20 and 40. Interface regions 20 and 40 are disposed on at least one surface of the internal regions 10 and 30 in the stacking direction and include an interface with the dielectric layer 111. In other words, the first inner electrode layer 121 may include a first internal region 10 and a first interface region 20. The first interface region 20 is disposed on at least one surface of the first internal region 10 in the stacking direction and includes an interface with the dielectric layer 111. Additionally, the second inner electrode layer 122 may include a second internal region 30 and a second interface region 40. The second interface region 40 is disposed on at least one surface of the second internal region 30 in the stacking direction and includes an interface with the dielectric layer 111.

[0076] The internal regions 10 and 30 of the inner electrode layers 121 and 122, as well as the interface regions 20 and 40, may include germanium (Ge). Specifically, the average germanium (Ge) content of the interface regions 20 and 40 may be higher than the average germanium (Ge) content of the internal regions 10 and 30.

[0077] Figure 5 Ellingham diagrams for nickel (Ni) and germanium (Ge) are shown.

[0078] During the manufacturing of multilayer ceramic capacitors, the sintering process can cause the oxidation of nickel (Ni) (the material of the inner electrode layer), thus forming nickel oxide. The formation of nickel oxide reduces the high-temperature reliability of multilayer ceramic capacitors.

[0079] like Figure 5 As shown, germanium (Ge) is an element with a stronger oxidation tendency than nickel (Ni). If such germanium (Ge) is applied to the inner electrode layer of a multilayer ceramic capacitor, it oxidizes before nickel (Ni), thus preventing nickel oxidation. During the extrusion of GeO2 into the dielectric layer, it can be partially confined at the interface between the dielectric layer and the inner electrode layer, but it can also partially remain in the reduced state of Ge and exist within the inner electrode layer. Here, the GeO2 disposed at the interface between the dielectric layer and the inner electrode layer can form a thin layer. GeO2 has a band gap energy of 6.6 eV, higher than that of BaTiO3 (3.4 eV), therefore the GeO2 insulating layer has the effect of improving interface resistance, which hinders the movement of interface electrons between the dielectric layer and the inner electrode layer, thereby improving the high-temperature reliability of the multilayer ceramic capacitor.

[0080] In other words, according to the embodiment, if germanium (Ge) is present not only in the inner electrode layers 121 and 122, but also in the interface regions 20 and 40 at a higher average content than in the internal regions 10 and 30, the interface resistance between the dielectric layer 111 and the inner electrode layers 121 and 122 can be increased, thereby ensuring the excellent reliability of the multilayer ceramic capacitor. Conversely, if the average germanium (Ge) content in the interface regions of the inner electrode layers is lower than the average germanium (Ge) content in the internal regions of the inner electrode layers, a GeO2 insulating layer capable of increasing the interface resistance may not be formed, thus degrading the reliability of the multilayer ceramic capacitor.

[0081] In each region, the average germanium (Ge) content can be based on the molar amount of Ge in 100 molar amounts of nickel (Ni).

[0082] Interface regions 20 and 40 are both regions with a depth of 2 nm extending from the interface between the inner electrode layers 121 and 122 and the dielectric layer 111 toward the interior of the inner electrode layers 121 and 122.

[0083] Specifically, when a transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) line analysis is performed on a straight line segment from a point in dielectric layer 111 to a point in inner electrode layers 121 and 122 adjacent to dielectric layer 111, the interface regions 20 and 40 of inner electrode layers 121 and 122 may have the maximum molar percentage of germanium (Ge).

[0084] More specifically, when performing transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) line analysis on a straight line segment from a point in dielectric layer 111 to a point in inner electrode layers 121 and 122 adjacent to dielectric layer 111, the interface between inner electrode layers 121 and 122 and dielectric layer 111 is defined as a point where the molar percentage of nickel (Ni) is approximately 1 / 3 of the maximum molar percentage of nickel (Ni), and interface regions 20 and 40 are defined as regions extending 2 nm from the point where the molar percentage of nickel (Ni) is approximately 1 / 3 of the maximum molar percentage of nickel (Ni) toward the interior of inner electrode layers 121 and 122.

[0085] In some embodiments of the specification, the thickness of interface regions 20 and 40 can be 2 nm.

[0086] Transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) line analysis can be performed as follows: After the multilayer ceramic capacitor 100 is placed in an epoxy mixture and cured, the W-axis and T-axis surfaces (WT surfaces) of the capacitor body 110 are polished to a position at half the length of the capacitor body 110 in the L-axis direction. After polishing, the polished surface is treated by ion polishing, and then the capacitor body 110 is fixed and held in a vacuum chamber to obtain a cross-sectional sample for detecting the effective area in which the dielectric layer 111 and the inner electrode layers 121 and 122 are stacked on top of each other. Subsequently, the effective area of ​​the cross-sectional sample is measured by taking images using transmission electron microscopy (TEM) such that at least one dielectric layer and at least one inner electrode layer in the effective area are visible. For example, when the effective area of ​​the cross-sectional sample is divided into three regions (such as an upper region, a central region, and a lower region) along the stacking direction, each region is measured by TEM such that at least one dielectric layer and at least one inner electrode layer in each region are visible. For example, in each of the upper, central, and lower regions of the effective region, in an approximately 80 nm × 80 nm region where at least one dielectric layer and at least one inner electrode layer are visible, TEM measurements are performed using a focused ion beam (Xe-FIB) at an accelerating voltage of 200 kV. Subsequently, in each of the measured TEM images of the cross-sectional sample, energy-dispersive spectroscopy (EDS) line analysis is performed on a straight line segment from a point in any dielectric layer to a point in the inner electrode layer adjacent to that dielectric layer. EDS line analysis allows not only the differentiation of internal regions 10 and 30 from interface regions 20 and 40, but also the comparison of germanium (Ge) content in these two regions. Other methods and / or other tools understood by those skilled in the art, even if not described in this disclosure, can be used.

[0087] Additionally, the average germanium (Ge) content in each region can be obtained using the following method: In the TEM images of each of the upper, central, and lower regions in the effective region, at least one inner electrode layer 121 and 122 can be randomly selected for each region to specify multiple points located in interface regions 20 and 40 and multiple points located in internal regions 10 and 30 for each inner electrode layer 121 and 122 in each region, and the Ge content is measured by EDS to calculate the average (X) of the Ge content in interface regions 20 and 40 and the average (Y) of the Ge content in internal regions 10 and 30. For example, after selecting an inner electrode layer in each of the upper, central, and lower regions in the effective region, any 3 points in the interface region and any 12 points in the internal region of each inner electrode layer are specified to measure the Ge content at each corresponding point by EDS to calculate the average Ge content in the respective interface region and internal region. In other words, the average Ge content (X) at a total of 9 points in the interface region (3 points × 3 inner electrode layers within the interface region) and the average Ge content (Y) at a total of 36 points in the internal region (12 points × 3 inner electrode layers within the internal region) were calculated. The measured average Ge content was based on 100 moles of Ni in the corresponding region. Other methods and / or other tools as understood by those skilled in the art may be used, even if not described in this disclosure.

[0088] Specifically, the average molar ratio (i.e., X / Y) of germanium (Ge) in interface regions 20 and 40 to germanium (Ge) in internal regions 10 and 30 can be greater than about 1 and less than or equal to about 5, for example, about 1.2 to about 4.8 or about 1.4 to about 4.6. If the average molar ratio of germanium (Ge) in the interface regions to germanium (Ge) in the internal regions is within this range, the interface resistance between the dielectric layer and the inner electrode layer can be increased, thereby improving the reliability of the multilayer ceramic capacitor. The average molar ratio of Ge can be the ratio of the average Ge content (X) in the interface regions to the average Ge content (Y) in the internal regions, as measured by the method described above.

[0089] Interface regions 20 and 40 may also include germanium oxide (GeO2). Here, the interface region acts as an insulating layer, thus further increasing the interface resistance between the dielectric layer and the inner electrode layer.

[0090] The germanium (Ge) in the inner electrode layers 121 and 122 may be derived from germanium (Ge)-based raw materials mixed with nickel (Ni) main components during the formation of the inner electrode layers, or from germanium (Ge)-based raw materials mixed with barium titanate-based compounds, which are the main components used to form the dielectric layer.

[0091] The internal regions 10 and 30 of the inner electrode layers 121 and 122, as well as the interface regions 20 and 40, may also include nickel (Ni).

[0092] In transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) line analysis of a straight line segment from a point in dielectric layer 111 to a point in the inner electrode layers 121 and 122 adjacent to dielectric layer 111, the inner regions 10 and 30 may have the maximum molar percentage of nickel (Ni).

[0093] Specifically, the average germanium (Ge) content (i.e., X) in interface regions 20 and 40 based on 100 moles of nickel (Ni) can be from about 0.4 moles to about 12 moles, for example, from about 0.45 moles to about 11 moles or from about 0.5 moles to about 10 moles. If the average germanium (Ge) content in the interface regions of the inner electrode layer is within this range, the melting point of the Ni-Ge alloy formed in the inner electrode layer can be maintained at an appropriate level, minimizing the spheroidization of the electrodes and thus improving the reliability of the multilayer ceramic capacitor.

[0094] Furthermore, based on 100 moles of nickel (Ni) in internal regions 10 and 30, the average germanium (Ge) content (i.e., Y) in internal regions 10 and 30 can be from about 0.2 moles to about 10 moles, for example, from about 0.3 moles to about 9 moles or from about 0.5 moles to about 8 moles. If the average germanium (Ge) content in the internal regions of the inner electrode layer is within this range, the interface resistance between the dielectric layer and the inner electrode layer can be increased, thereby improving the reliability of the multilayer ceramic capacitor.

[0095] In addition to germanium (Ge) and nickel (Ni), interface regions 20 and 40 may also include at least one selected from titanium (Ti) and barium (Ba). Titanium (Ti) and barium (Ba) may be derived from barium titanate-based compounds used as main components to form the dielectric layer, or from barium titanate powder added as a co-material to the inner electrode layer when needed.

[0096] In the stacking direction, the thickness of interface regions 20 and 40 can be from about 0.05% to about 3% of the total thickness of the inner electrode layers 121 and 122 having inner regions 10 and 30 and interface regions 20 and 40, for example, from about 0.07% to about 2.8% or from about 0.1% to about 2.5% of the total thickness of the inner electrode layers 121 and 122. If the thickness of the interface regions is within this range, the interface resistance between the dielectric layer and the inner electrode layer can be increased, thereby improving the reliability of the multilayer ceramic capacitor.

[0097] The total thickness of the inner electrode layers 121 and 122 can be used to represent the average thickness of the inner electrode layers 121 and 122.

[0098] The average thickness of the inner electrode layers 121 and 122 can be from about 0.1 μm to about 2 μm. If the average thickness of the inner electrode layers is within this range, the multilayer ceramic capacitor can have excellent reliability.

[0099] The thicknesses of interface regions 20 and 40, as well as the thicknesses of inner electrode layers 121 and 122, can be measured using the following method.

[0100] After immersing and curing the multilayer ceramic capacitor 100 in an epoxy mixture, the W-axis and T-axis surfaces (WT surfaces) of the capacitor body 110 are polished to half the length of the capacitor body 110 in the L-axis direction. A cross-sectional sample is then obtained by fixing and holding it in a vacuum chamber, allowing observation of the effective region where the dielectric layer 111 is stacked with the inner electrode layers 121 and 122. The effective region of this cross-sectional sample can then be measured using a scanning electron microscope (SEM) so that at least one (e.g., one to five) of the dielectric and inner electrode layers is visible. For example, a Verios G4 product from Thermofisher Scientific can be used to perform SEM measurements in an approximately 400 nm × 400 nm region of the effective region (where at least one dielectric layer and one inner electrode layer are visible) at 10 kV.

[0101] In the SEM image of the cross-sectional sample, after designating the center point of the inner electrode layers 121 and 122 in the width direction (W-axis direction) as a reference point, ten points spaced apart from the reference point at predetermined intervals are marked to calculate the arithmetic mean of the thicknesses of the inner electrode layers 121 and 122. The interval between any two adjacent points among the ten points can be adjusted according to the scale of the scanning electron microscope (SEM) image, for example, it can be adjusted to 1 μm to 100 μm, 1 μm to 50 μm, or 1 μm to 10 μm. In this document, all ten points should be located within the inner electrode layers 121 and 122; however, if not all ten points are located within the inner electrode layers 121 and 122, the reference point can be repositioned, or the interval between any two adjacent points among the ten points can be adjusted. In some embodiments of this disclosure, the thicknesses of the interface regions 20 and 40 can be obtained from the TEM-EDS line analysis described herein. Other methods and / or other tools understood by those skilled in the art may be used, even if not described herein.

[0102] dielectric layer The dielectric layer 111 may include a barium titanate-based compound containing barium (Ba) and titanium (Ti) as the main component.

[0103] Barium titanate-based compounds are dielectric matrix materials with high dielectric constants and contribute to the capacitance of multilayer ceramic capacitors 100.

[0104] For example, barium titanate-based compounds may include at least one selected from BaTiO3, Ba(Ti, Zr)O3, Ba(Ti, Sn)O3, (Ba, Ca)TiO3, (Ba, Ca)(Ti, Zr)O3, (Ba, Ca)(Ti, Sn)O3, (Ba, Sr)TiO3, (Ba, Sr)(Ti, Zr)O3, and (Ba, Sr)(Ti, Sn)O3.

[0105] In addition to barium (Ba) and titanium (Ti), dielectric layer 111 may also include germanium (Ge).

[0106] The germanium (Ge) in dielectric layer 111 may be derived from germanium (Ge)-based raw materials mixed with nickel (Ni) main components during the formation of the inner electrode layer, or from germanium (Ge)-based raw materials mixed with barium titanate-based compounds as main components during the formation of the dielectric layer.

[0107] The dielectric layer 111 may also include secondary components. For example, the secondary components may include at least one selected from manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), and vanadium (V).

[0108] The average thickness (average dimension in the T-axis direction) of the dielectric layer 111 can be from about 0.2 μm to about 10 μm, for example, from about 0.2 μm to about 8.0 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor can be improved.

[0109] The average thickness of the dielectric layer 111 can be an arithmetic mean obtained by taking the center point of the dielectric layer 111 in the width direction (W-axis direction) as a reference point in a scanning electron microscope (SEM) image of the cross-sectional sample obtained as described above, and calculating the arithmetic mean of the thickness of the dielectric layer 111 at 10 points spaced apart from the reference point at predetermined intervals. The interval between any two adjacent points among the 10 points can be adjusted according to the scale of the SEM image, for example, it can be about 1 μm to about 100 μm, about 1 μm to about 50 μm, or about 1 μm to about 10 μm. In this case, all 10 points must be located within the dielectric layer 111, and if not all 10 points are located within the dielectric layer 111, the position of the reference point can be changed, or the interval between any two adjacent points among the 10 points can be adjusted. Other methods and / or other tools understood by those skilled in the art may be used even if not described in this disclosure.

[0110] The capacitor body 110 can be formed by firing a stacked structure in which multiple dielectric layers 111 and multiple internal electrode layers 121 and 122 are stacked.

[0111] external electrode The first external electrode 131 and the second external electrode 132 are provided with voltages of different polarities and can be electrically connected to the exposed portions of the first inner electrode layer 121 and the second inner electrode layer 122, respectively.

[0112] According to the above structure, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge accumulates between the first inner electrode layer 121 and the second inner electrode layer 122, which are opposite to each other. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the stacked area of ​​the first inner electrode layer 121 and the second inner electrode layer 122 stacked together along the T-axis in the effective region.

[0113] The first external electrode 131 may include a first connecting portion disposed on the third surface of the capacitor body 110 and connected to the first inner electrode layer 121, and a first strip portion disposed on the edge where the third surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface. The second external electrode 132 may include a second connecting portion disposed on the fourth surface of the capacitor body 110 and connected to the second inner electrode layer 122, and a second strip portion disposed on the edge where the fourth surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface.

[0114] The first strip may extend from the first connecting portion to a portion of the first surface, a portion of the second surface, and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The second strip may extend from the second connecting portion to a portion of the first surface, a portion of the second surface, and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The first strip and the second strip may be used to improve the bonding strength between the first external electrode 131 and the second external electrode 132 and the capacitor body 110, respectively.

[0115] The external electrodes 131 and 132 may include a sintered metal layer in contact with the capacitor body 110, a conductive resin layer configured to cover the sintered metal layer, and a plating layer configured to cover the conductive resin layer.

[0116] The sintered metal layer may include conductive metals and glass.

[0117] The conductive metal may include at least one selected from copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, "conductive metal includes copper (Cu)" may mean that the conductive metal includes elemental copper (Cu) or an alloy of copper (Cu). When the conductive metal includes copper (Cu), other metals may be included in an amount of less than or equal to about 5 moles of copper (Cu) based on 100 moles of copper (Cu).

[0118] The glass may comprise a composition of mixed oxides (e.g., one or more selected from the group consisting of silicon oxides, boron oxides, aluminum oxides, transition metal oxides, alkali metal oxides, and alkaline earth metal oxides). The transition metal may be at least one selected from zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni); the alkali metal may be at least one selected from lithium (Li), sodium (Na), and potassium (K); and the alkaline earth metal may be at least one selected from magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0119] Optionally, the conductive resin layer may be formed on the sintered metal layer, for example, it may be formed in a shape that completely covers the sintered metal layer. Furthermore, the external electrodes 131 and 132 may not include the sintered metal layer, and in this case, the conductive resin layer may directly contact the capacitor body 110.

[0120] The conductive resin layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the strip portion) in which the conductive resin layer extends and is disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 may be longer than the length of the region (i.e., the strip portion) in which the sintered metal layer extends and is disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. That is, the conductive resin layer may be formed on the sintered metal layer and may be formed in a shape that completely covers the sintered metal layer.

[0121] The conductive resin layer may include resin and conductive metal.

[0122] The resin included in the conductive resin layer can be, but is not limited to, a material that has adhesive and shock-absorbing properties and can form a paste when mixed with conductive metal powder. For example, the resin may include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0123] The conductive metal included in the conductive resin layer is used to electrically connect the inner electrode layers 121 and 122 or the sintered metal layer to the plating described below.

[0124] The conductive metal included in the conductive resin layer may have a spherical shape, a sheet shape, or a combination thereof. That is, the conductive metal may be formed only as a sheet shape, or only as a spherical shape, or a mixture of sheet and spherical shapes.

[0125] Here, "spherical shape" can also include shapes that are not perfect spheres. For example, a spherical shape can refer to a shape whose length ratio of the major axis to the minor axis (major axis / minor axis) is less than or equal to about 1.45. A sheet shape refers to a flat and elongated shape, and there are no particular limitations. For example, a sheet shape can refer to a shape whose length ratio of the major axis to the minor axis (major axis / minor axis) is greater than or equal to about 1.95.

[0126] The external electrodes 131 and 132 may also include a plating layer disposed on the outer surface of the conductive resin layer.

[0127] The coating may include at least one of nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, the coating may be a nickel (Ni) coating or a tin (Sn) coating, or a coating in which nickel (Ni) and tin (Sn) coatings are stacked sequentially, or a coating in which tin (Sn), nickel (Ni), and tin (Sn) coatings are stacked sequentially. Additionally, the coating may include multiple nickel (Ni) coatings and / or multiple tin (Sn) coatings.

[0128] The coating can improve the mountability, structural reliability, external durability, heat resistance and equivalent series resistance (ESR) of the multilayer ceramic capacitor 100 on the substrate.

[0129] Methods for manufacturing multilayer ceramic capacitors The method of manufacturing the aforementioned multilayer ceramic capacitor 100 according to an embodiment will be described below.

[0130] A multilayer ceramic capacitor 100 can be manufactured by: mixing nickel (Ni) and germanium (Ge) based raw materials to prepare a conductive paste; manufacturing dielectric green sheets from a dielectric paste, and printing or coating conductive paste on the surface of the dielectric green sheets to form a conductive paste layer; stacking multiple dielectric green sheets on which the conductive paste layer is formed to manufacture a dielectric green sheet stack; firing the dielectric green sheet stack to manufacture a capacitor body including a dielectric layer and an inner electrode layer; and forming an outer electrode on the outer surface of the capacitor body.

[0131] Germanium (Ge)-based raw materials may include at least one selected from germanium (Ge), germanium oxide (GeO2), and Ni-Ge alloys.

[0132] Based on 100 molar parts of nickel (Ni), germanium (Ge)-based raw materials can be mixed in an amount of about 0.3 molar parts to about 10 molar parts (e.g., about 0.4 molar parts to about 9 molar parts or about 0.5 molar parts to about 8 molar parts) of germanium (Ge). When germanium (Ge)-based raw materials are mixed within the above-mentioned content range, the content of germanium (Ge) distributed at the interface with the dielectric layer is higher than the content of germanium (Ge) distributed inside the inner electrode layer. Therefore, a multilayer ceramic capacitor with excellent reliability and high interface resistance between the dielectric layer and the inner electrode layer can be obtained.

[0133] In addition to nickel (Ni), conductive paste can be prepared by further mixing one or more of copper (Cu), silver (Ag), palladium (Pd), gold (Au) and their alloys (such as Ag-Pd alloys).

[0134] Alternatively, conductive paste can be prepared by further mixing conductive powder, binder, and solvent. Additionally, if desired, barium titanate-based powder can be incorporated into the conductive paste as a co-material. The co-material can be used to suppress the sintering of the conductive powder during the firing process.

[0135] Dielectric pastes can be prepared by mixing a barium titanate-based compound as the main component powder with optional secondary component powders. The secondary component powders can be in the form of oxides or salt compounds, or in the form of a sol dispersed in an organic solvent.

[0136] Alternatively, dielectric pastes can be prepared by mixing additional additives (such as dispersants, binders, plasticizers, lubricants, and antistatic agents) and solvents.

[0137] For example, the dispersant may include at least one selected from phosphate ester dispersants and polycarboxylic acid dispersants. Based on 100 parts by weight of barium titanate-based compound powder, the dispersant can be mixed in an amount of about 0.1 parts by weight to about 5 parts by weight (e.g., about 0.3 parts by weight to about 3 parts by weight). When the dispersant is mixed within the above-mentioned content range, the dispersibility of the dielectric paste is excellent, and the amount of impurities included in the manufactured dielectric layer can be reduced.

[0138] For example, the binder can be acrylic resin, polyvinyl butyral resin, polyvinyl acetal resin, ethyl cellulose resin, etc. Based on 100 parts by weight of barium titanate compound powder, the binder can be added in amounts from about 0.1 parts by weight to about 50 parts by weight (e.g., from about 3 parts by weight to about 30 parts by weight). When the binder is mixed within the above content range, the dielectric paste exhibits excellent dispersibility and reduces the amount of impurities included in the manufactured dielectric layer.

[0139] For example, plasticizers can be: phthalic acid compounds (such as dioctyl phthalate, butyl benzyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, and di(2-ethylbutyl) phthalate); adipate compounds (such as dihexyl adipate and di(2-ethylhexyl) adipate); glycol compounds (such as ethylene glycol, diethylene glycol, and triethylene glycol); glycol ester compounds (such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), and triethylene glycol di(2-ethylhexanoate)). Based on 100 parts by weight of barium titanate-based compound powder, a plasticizer can be added in an amount of about 0.1 parts by weight to about 20 parts by weight (e.g., about 1 part by weight to about 10 parts by weight). When plasticizers are mixed within the above-mentioned content range, the dielectric paste exhibits excellent dispersibility and reduces the amount of impurities included in the manufactured dielectric layer.

[0140] Solvents can be: aqueous solvents (such as water); alcohol solvents (such as ethanol, methanol, benzyl alcohol, and methoxyethanol); glycol solvents (such as ethylene glycol and diethylene glycol); ketone solvents (such as acetone, methyl ethyl ketone, methyl isobutyl ketone, and cyclohexanone); ester solvents (such as butyl acetate, ethyl acetate, carbitol acetate, and butyl carbitol acetate); ether solvents (such as methyl cellosolve, ethyl cellosolve, butyl ether, and tetrahydrofuran); aromatic solvents (such as benzene, toluene, and xylene), etc. For example, considering the solubility or dispersibility of the various additives included in the dielectric paste, the solvent can be an alcohol solvent or an aromatic solvent. Based on 100 parts by weight of barium titanate compound powder, the solvent can be mixed in an amount of about 50 parts by weight to about 1000 parts by weight (e.g., about 100 parts by weight to about 500 parts by weight). When the solvent is mixed within the above-mentioned content range, the various components of the dielectric paste can be sufficiently mixed, and the solvent can be easily removed subsequently.

[0141] The aforementioned dielectric slurry can be mixed using a wet ball mill or a stirred mill. When using zirconia balls in a wet ball mill, multiple zirconia balls with a diameter of about 0.1 mm to about 10 mm can be used for wet mixing for about 8 hours to about 48 hours, for example, about 10 hours to about 24 hours.

[0142] The prepared dielectric paste forms a dielectric layer after firing.

[0143] Methods such as strip forming (e.g., doctor blade forming) and calendering roll forming (e.g., using a roll forming coating machine with a coating head discharge type) can be used to form the prepared dielectric paste into a sheet-like molded body, which can then be dried to obtain a dielectric green sheet.

[0144] The conductive paste layer is formed by applying the conductive paste to the surface of the dielectric sheet in a predetermined pattern using various printing methods (such as screen printing) or transfer methods.

[0145] According to an embodiment, a germanium (Ge)-based raw material can be used to prepare a dielectric paste for forming a dielectric layer instead of a conductive paste for forming an inner electrode layer. In other words, the multilayer ceramic capacitor 100 can be manufactured by mixing a barium titanate-based compound with a germanium (Ge)-based raw material to prepare a dielectric paste, manufacturing the dielectric paste into a dielectric green sheet, and printing a conductive paste including nickel (Ni) onto the surface of the dielectric green sheet to form a conductive paste layer.

[0146] Next, a dielectric green sheet stack is prepared by stacking multiple dielectric green sheets on which conductive paste layers are formed, and then pressing multiple layers of dielectric green sheets in the stacking direction. At this time, dielectric green sheets without conductive paste layers can be stacked, such that the dielectric green sheets without conductive paste layers are disposed at the upper and lower parts of the dielectric green sheet stack in the stacking direction.

[0147] Optionally, the process of cutting the manufactured dielectric wafer stack into a predetermined size by means of cutting or the like can be performed.

[0148] Additionally, if necessary, the dielectric green sheet stack can be cured and dried to remove plasticizers, etc., and after curing and drying, the dielectric green sheet stack can be tumble polished using a horizontal centrifugal tumbler or similar device. During tumble polishing, the dielectric green sheet stack is placed in a tumbler container containing a dielectric and polishing fluid, and rotational motion or vibration is applied to the tumbler container to polish unwanted parts (such as burrs generated during cutting). After tumble polishing, the dielectric green sheet stack can be washed with a cleaning solution (such as water) and then dried.

[0149] Subsequently, the capacitor body can be obtained after adhesive removal and firing processes of the dielectric sheet stack.

[0150] The conditions for the adhesive removal process can be appropriately adjusted according to the composition of the dielectric layer and / or the composition of the internal electrode layer. For example, the heating rate during the adhesive removal process can be from about 5°C / hour to about 300°C / hour, the holding temperature can be from about 180°C to about 400°C, and the temperature holding time can be from about 0.5 hours to about 24 hours. The adhesive removal process can be carried out in an air atmosphere or a reducing atmosphere.

[0151] The firing conditions can be appropriately adjusted according to the main component composition of the dielectric layer and / or the main component composition of the inner electrode layer. For example, firing can be performed at a temperature of about 1100°C to about 1400°C, and firing can be performed at a temperature of about 1200°C to about 1350°C. Additionally, firing can be performed for about 0.5 hours to about 8 hours (e.g., about 1 hour to about 3 hours). Furthermore, firing can be performed in a reducing atmosphere (e.g., in an atmosphere humidified with a mixture of nitrogen and hydrogen). Additionally, firing can be performed for about 10... -12 atm to approximately 10 -8 The firing process is performed under oxygen partial pressure conditions within the above range. When the firing process is performed under oxygen partial pressure conditions within the above range, a multilayer ceramic capacitor with excellent reliability and high interfacial resistance between the dielectric layer and the inner electrode layer can be obtained. The oxygen partial pressure can be measured by an oxygen sensor. Other methods and / or other tools understood by those skilled in the art can be used even if not described in this disclosure.

[0152] After firing, annealing may be performed as needed. Annealing is a process that re-oxidizes the dielectric layer, and it can be performed if firing is carried out in a reducing atmosphere. The annealing conditions can also be appropriately adjusted according to the composition of the dielectric layer. For example, the annealing temperature can be from about 950°C to about 1150°C, the annealing time can be greater than 0 hours and less than or equal to about 20 hours, and the heating rate can be from about 50°C / hour to about 500°C / hour. The annealing atmosphere can be a moistened nitrogen (N2) atmosphere, and the oxygen partial pressure can be about 1.0 × 10⁻⁶. -9 MPa to approximately 1.0 × 10 -5 MPa.

[0153] In adhesive removal, firing, or annealing processes, a wetting agent may be used, for example, to wet nitrogen or a mixture of gases. In this case, the temperature of the wetting agent may be from about 5°C to about 75°C. Adhesive removal, firing, and annealing processes may be performed sequentially or independently.

[0154] Optionally, the third and fourth surfaces of the prepared capacitor body 110 can be surface-treated (such as by sandblasting, laser irradiation, or tumble polishing). By performing this surface treatment, the ends of the first inner electrode layer and the second inner electrode layer can be exposed to the third and fourth surfaces, respectively, thereby improving the electrical connection between the first outer electrode and the first inner electrode layer, as well as the electrical connection between the second outer electrode and the second inner electrode layer, and facilitating the formation of alloy portions.

[0155] Subsequently, an external electrode is formed on the surface of the manufactured capacitor body 110.

[0156] As an example, a paste for forming a sintered metal layer can be applied to the surface of the manufactured capacitor body and then sintered to form the sintered metal layer.

[0157] The paste used to form the sintered metal layer may include conductive metals and glass. Since the description of conductive metals and glass is the same as that described above, repeated descriptions will be omitted. Alternatively, the paste used to form the sintered metal layer may include binders, solvents, dispersants, plasticizers, oxide powders, etc. The binder may be, for example, ethyl cellulose resin, acrylic resin, butyral resin, etc., and the solvent may be, for example, an organic solvent (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0158] Methods for applying a paste for forming a sintered metal layer to the outer surface of the capacitor body 110 may include dipping, various printing methods (such as screen printing), coating methods using a dispenser, and spraying methods using a spray gun. The paste for forming the sintered metal layer may be applied to at least the third and fourth surfaces of the capacitor body 110, and optionally to portions of the first, second, fifth, and / or sixth surfaces on which the strips of the first and second external electrodes will be formed.

[0159] Subsequently, the capacitor body 110 coated with paste for forming a sintered metal layer is dried and sintered at a temperature of about 700°C to about 1000°C for about 0.1 hours to about 3 hours to form a sintered metal layer.

[0160] Optionally, a paste for forming a conductive resin layer is coated onto the outer surface of the obtained capacitor body 110 and then cured to form a conductive resin layer.

[0161] The paste used to form the conductive resin layer may include a resin and a conductive metal, and optionally, a non-conductive filler. Since the description of the conductive metal and resin is the same as that described above, repeated descriptions will be omitted. Additionally, the paste used to form the conductive resin layer may optionally include an adhesive, solvent, dispersant, plasticizer, oxide powder, etc. The adhesive may be, for example, ethyl cellulose resin, acrylic resin, butyral resin, etc., and the solvent may be an organic solvent (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, and toluene) or an aqueous solvent.

[0162] For example, the conductive resin layer can be formed by immersing the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or by printing the paste for forming the conductive resin layer onto the surface of the capacitor body 110 by screen printing or gravure printing and then curing it, or by applying the paste for forming the conductive resin layer onto the surface of the capacitor body 110 and then curing it.

[0163] Next, a plating layer is formed on the outer surface of the conductive resin layer.

[0164] For example, the coating can be formed by plating (e.g., electroplating (electrodeposition)) or sputtering.

[0165] In the following description, embodiments will be illustrated in more detail with reference to examples. However, these examples are exemplary, and the scope of the claims is not limited thereto.

[0166] (Manufacturing of multilayer ceramic capacitors) Examples 1 to 10, and Comparative Examples 1 and 2 Ni was mixed with GeO2 to prepare a conductive paste. Here, GeO2 was mixed based on 100 molar parts of Ni, including the amount of Ge as shown in Table 1.

[0167] Subsequently, barium titanate (BaTiO3) powder was used to prepare a dielectric paste. Here, the dielectric paste comprises ethanol / toluene, a dispersant, and a binder, and is mechanically milled using zirconia (ZrO2) balls as a dispersion medium.

[0168] Dielectric paste is discharged from the coating head onto the forming roller of the forming coating machine to manufacture a dielectric green sheet. The prepared conductive paste is then printed onto the surface of the dielectric green sheet to form a conductive paste layer.

[0169] Dielectric green sheets with conductive paste layers are stacked on top and pressed to form a dielectric green sheet stack.

[0170] Each dielectric sheet stack was calcined in a nitrogen atmosphere at 400°C or less, and 10 -12 atm to 10 -8 Each dielectric green sheet stack is fired within the oxygen partial pressure range of atm at a hydrogen (H2) concentration (volume concentration) of less than or equal to 1.0% and at a temperature of less than or equal to 1300°C to form the capacitor body.

[0171] Subsequently, external electrodes are formed on the surface of the capacitor body through processes such as plating, thereby obtaining a multilayer ceramic capacitor.

[0172] (Table 1)

[0173] Evaluation 1: TEM-EDS Analysis Each of the fabricated multilayer ceramic capacitors was analyzed by transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS), and the results are presented in... Figures 6 to 8 And in Table 2.

[0174] Specifically, the multilayer ceramic capacitor of Example 5 was placed in an epoxy mixture and cured. After polishing the W-axis and T-axis surfaces (WT surfaces) of the capacitor body to half the length of the capacitor body in the L-axis direction, the polished surfaces were ion-polished. The capacitor body was then fixed and held in a vacuum chamber to obtain a cross-sectional sample for examining the effective region where the dielectric layer and the inner electrode layer overlapped. Subsequently, the effective region of the cross-sectional sample was divided into three regions (e.g., upper region, central region, and lower region) along the stacking direction, and transmission electron microscopy (TEM) analysis was performed so that at least one dielectric layer and at least one inner electrode layer were observed in each region. In each of the upper, central, and lower regions of the effective region, TEM measurements were performed at an accelerating voltage of 200 kV using a focused ion beam (Xe-FIB) in an approximately 80 nm × 80 nm region showing at least one dielectric layer and at least one inner electrode layer to obtain a TEM image. Subsequently, energy-dispersive spectroscopy (EDS) analysis was performed on each TEM image of the cross-sectional sample.

[0175] Figure 6 It is based on the transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) surface scan analysis of the effective region in Example 5.

[0176] Reference Figure 6 Example 5 shows that the average Ge content at the interface between the inner electrode layer and the dielectric layer is greater than the average Ge content inside the inner electrode layer. In other words, the interface region including the interface with the dielectric layer (i.e., the region extending from the interface between the dielectric layer and the inner electrode layer to the interior of the inner electrode layer at a depth of about 2 nm) exhibits a greater average Ge content than the other regions (the interior regions).

[0177] In addition, energy-dispersive spectroscopy (EDS) line analysis was performed on the straight line segment from a point in any inner electrode layer to a point in the dielectric layer adjacent to that inner electrode layer in the TEM image of the cross-sectional sample, and the results are presented in... Figure 7 and Figure 8 middle.

[0178] Figure 7 It is based on the transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) surface scan analysis of the effective region in Example 5, and Figure 8 yes Figure 7 Energy dispersive spectroscopy (EDS) line analysis diagram of the straight segment.

[0179] Reference Figure 7 and Figure 8In Example 5, the inner electrode layer has the maximum molar percentage (or atomic percentage) of Ge in the interface region. Here, the interface between the dielectric layer and the inner electrode layer corresponds to a point where the molar percentage of Ni is approximately 1 / 3 of the maximum molar percentage of Ni, and the interface region is a region extending 2 nm from the point where the molar percentage of Ni is approximately 1 / 3 of the maximum molar percentage of Ni toward the interior of the inner electrode layer. Furthermore, in the inner electrode layer of Example 5, the average Ge content in the interface region is greater than the average Ge content in the interior region (the remaining regions).

[0180] Furthermore, in the TEM images of each of the upper, central, and lower regions of the effective area, after selecting an inner electrode layer in each region, arbitrary 3 points within the interface region and arbitrary 12 points within the internal region of each inner electrode layer were specified, and EDS analysis was performed to measure the Ge content at the corresponding points. This was used to calculate the average Ge content in the respective interface and internal regions. In other words, the average Ge content (X) at a total of 9 points (3 points × 3 inner electrode layers) in the interface region and the average Ge content (Y) at a total of 36 points (12 points × 3 inner electrode layers) in the internal region were calculated. The results are shown in Table 2. Here, the measured average Ge content in the corresponding region is expressed based on 100 moles of Ni.

[0181] Referring to Table 2, the inner electrode layers of Examples 1 to 10 exhibit a higher average Ge content in the interface region than in the inner region.

[0182] Evaluation 2: Reliability The mean time to failure (MTTF) of the multilayer ceramic capacitors according to Examples 1 to 10 and Comparative Examples 1 and 2 were measured using the following method, and the results are shown in Table 2.

[0183] The MTTF (Mean Time To Failure) was measured under the conditions of 9.45V, 125℃, and 48 hours.

[0184] Table 2 shows the MTTF values ​​in relative form, based on the results of Example 1.

[0185] (Table 2)

[0186] Referring to Table 2, the multilayer ceramic capacitors according to Examples 1 to 10 exhibit superior reliability compared to the multilayer ceramic capacitors according to Comparative Examples 1 and 2. Therefore, when the average Ge content in the interface region of the inner electrode layer according to the embodiment is greater than the average Ge content in the internal region, a high interface resistance is achieved, thereby ensuring excellent reliability.

[0187] Although this disclosure has been described in conjunction with embodiments now considered to be practical, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various variations and equivalents included within the spirit and scope of the appended claims.

Claims

1. A multilayer ceramic capacitor, comprising: A capacitor body includes a plurality of stacked dielectric layers and a plurality of inner electrode layers, wherein the dielectric layers are located between adjacent inner electrode layers. as well as External electrodes are disposed on the outer surface of the capacitor body. Wherein, at least one of the plurality of inner electrode layers includes: Internal area, and An interface region is disposed on at least one surface of the inner region in the stacking direction, the interface region including an interface with an adjacent dielectric layer among the plurality of dielectric layers. The internal region and the interface region include Ge, and The average content of Ge in the interface region is higher than the average content of Ge in the interior region.

2. The multilayer ceramic capacitor according to claim 1, wherein, The ratio of the average Ge content in the interface region to the average Ge content in the inner region is greater than 1 and less than or equal to 5.

3. The multilayer ceramic capacitor according to claim 1, wherein, The interface region is a region with a depth of 2 nm from the interface of the adjacent dielectric layer to the interior of the at least one inner electrode layer.

4. The multilayer ceramic capacitor according to claim 1, wherein, In transmission electron microscopy-energy dispersive spectroscopy images, when line analysis is performed on a straight line segment from a point in the at least one inner electrode layer to a point in the adjacent dielectric layer, The interface region has the maximum molar percentage of Ge.

5. The multilayer ceramic capacitor according to claim 1, wherein, The interface area also includes GeO2.

6. The multilayer ceramic capacitor according to claim 1, wherein, The internal region and the interface region also include Ni.

7. The multilayer ceramic capacitor according to claim 6, wherein, In transmission electron microscopy-energy dispersive spectroscopy images, when line analysis is performed on a straight line segment from a point in the adjacent dielectric layer to a point in the at least one inner electrode layer, The internal region has the maximum molar percentage of Ni.

8. The multilayer ceramic capacitor according to claim 6, wherein, In transmission electron microscopy-energy dispersive spectroscopy images, when line analysis is performed on a straight line segment from a point in the adjacent dielectric layer to a point in the at least one inner electrode layer, The interface region is a region extending 2 nm from the point where the molar percentage of Ni is 1 / 3 of the maximum molar percentage of Ni into the interior of the at least one inner electrode layer.

9. The multilayer ceramic capacitor according to claim 6, wherein, Based on 100 moles of Ni in the interface region, the average content of Ge in the interface region is from 0.4 moles to 12 moles.

10. The multilayer ceramic capacitor according to claim 6, wherein, The interface region also includes at least one selected from Ti and Ba.

11. The multilayer ceramic capacitor according to claim 6, wherein, Based on 100 moles of Ni in the inner region, the average content of Ge in the inner region is from 0.2 moles to 10 moles.

12. The multilayer ceramic capacitor according to claim 1, wherein, The thickness of the interface region is 0.05% to 3% of the total thickness of the at least one inner electrode layer.

13. The multilayer ceramic capacitor according to claim 1, wherein, The plurality of dielectric layers include Ba, Ti and Ge.

14. The multilayer ceramic capacitor according to claim 1, wherein, The average thickness of the at least one inner electrode layer is 0.1 μm to 2 μm.

15. The multilayer ceramic capacitor according to claim 1, wherein, The average thickness of at least one of the plurality of dielectric layers is from 0.2 μm to 10 μm.

16. A method for manufacturing a multilayer ceramic capacitor, comprising: Ni is mixed with Ge-based raw materials to prepare conductive paste; A dielectric green sheet is manufactured from a dielectric paste, and the conductive paste is coated on the surface of the dielectric green sheet to form a conductive paste layer; A plurality of dielectric sheets on which the conductive paste layer is formed are stacked to manufacture a dielectric sheet stack; The dielectric green sheet stack is fired to manufacture a capacitor body including a dielectric layer and an inner electrode layer; as well as An external electrode is formed on the outer surface of the capacitor body. The inner electrode layer includes: Internal area, and An interface region is disposed on at least one surface of the inner region in the stacking direction, the interface region including an interface with the dielectric layer. The inner region and the interface region include Ge, and the average content of Ge in the interface region is higher than the average content of Ge in the inner region.

17. The method according to claim 16, wherein, The Ge-based raw material includes at least one selected from Ge, GeO2, and Ni-Ge alloys.

18. The method according to claim 16, wherein, The Ge-based raw material is mixed with 0.3 to 10 molar parts of Ge based on 100 molar parts of Ni.

19. The method of claim 16, wherein, atm to 10 -12 atm to 10 -8 atm of oxygen partial pressure.

20. A method for manufacturing a multilayer ceramic capacitor, comprising: Barium titanate-based compounds are mixed with Ge-based raw materials to prepare dielectric pastes; A dielectric green sheet is manufactured from the dielectric paste, and a conductive paste is printed on the surface of the dielectric green sheet to form a conductive paste layer; A plurality of dielectric sheets on which the conductive paste layer is formed are stacked to manufacture a dielectric sheet stack; The dielectric green sheet stack is fired to manufacture a capacitor body including a dielectric layer and an inner electrode layer; as well as An external electrode is formed on the outer surface of the capacitor body. The inner electrode layer includes: Internal area, and An interface region is disposed on at least one surface of the inner region in the stacking direction, the interface region including an interface with the dielectric layer. The inner region and the interface region include Ge, and the average content of Ge in the interface region is higher than the average content of Ge in the inner region.

21. The method according to claim 20, wherein, The Ge-based raw material includes at least one selected from Ge, GeO2, and Ni-Ge alloys.

22. The method according to claim 20, wherein, atm to 10 -12 atm to 10 -8 atm of oxygen partial pressure.

23. A multilayer ceramic capacitor, comprising: A capacitor body includes a plurality of stacked dielectric layers and a plurality of inner electrode layers, wherein the dielectric layers are located between adjacent inner electrode layers. as well as External electrodes are disposed on the outer surface of the capacitor body. Wherein, at least one of the plurality of inner electrode layers includes: Internal area, and An interface region is disposed on at least one surface of the inner region in the stacking direction, the interface region including an interface with an adjacent dielectric layer among the plurality of dielectric layers. The internal region and the interface region include both Ge and Ni, and Based on 100 moles of Ni in the interface region, the average content of Ge in the interface region is from 0.4 moles to 12 moles.

24. The multilayer ceramic capacitor according to claim 23, wherein, The average content of Ge in the interface region is different from the average content of Ge in the interior region.

25. The multilayer ceramic capacitor according to claim 23, wherein, The interface region is a region with a depth of 2 nm from the interface of the adjacent dielectric layer to the interior of the at least one inner electrode layer.

26. The multilayer ceramic capacitor according to claim 25, wherein, The average content of Ge in the interface region is higher than the average content of Ge in the interior region.

27. A method of manufacturing a multilayer ceramic capacitor according to any one of claims 23 to 26, comprising: Ni was mixed with GeO2 to prepare a conductive paste; A dielectric green sheet is manufactured from a dielectric paste, and the conductive paste is coated on the surface of the dielectric green sheet to form a conductive paste layer; A plurality of dielectric sheets on which the conductive paste layer is formed are stacked to manufacture a dielectric sheet stack; Sintering the dielectric green sheet stack to manufacture the capacitor body; and The external electrode is formed on the outer surface of the capacitor body.

28. The method according to claim 27, wherein, The firing process is carried out under conditions of hydrogen volume concentration of less than or equal to 1.0% and temperature of less than or equal to 1300°C.

29. The method according to claim 28, wherein, atm to 10 -12 atm to 10 -8 atm of oxygen partial pressure.

30. The method according to claim 29, wherein, GeO2 is mixed with 0.3 to 10 moles of Ge based on 100 moles of Ni.

31. A multilayer ceramic capacitor, comprising: A capacitor body includes a plurality of stacked dielectric layers and a plurality of inner electrode layers, wherein the dielectric layers are located between adjacent inner electrode layers. as well as External electrodes are disposed on the outer surface of the capacitor body. Wherein, at least one of the plurality of inner electrode layers includes: Internal area, and An interface region is disposed on at least one surface of the inner region in the stacking direction, the interface region including an interface with an adjacent dielectric layer among the plurality of dielectric layers. The internal region and the interface region include Ge, and The average content of Ge in the interface region is different from the average content of Ge in the interior region.

32. The multilayer ceramic capacitor according to claim 31, wherein, The internal region and the interface region also include Ni. Based on 100 moles of Ni in the interface region, the average Ge content in the interface region is 0.4 moles to 12 moles, and Based on 100 moles of Ni in the inner region, the average content of Ge in the inner region is from 0.2 moles to 10 moles.

33. The multilayer ceramic capacitor according to claim 31, wherein, The ratio of the average Ge content in the interface region to the average Ge content in the inner region is greater than 1 and less than or equal to 5.

34. The multilayer ceramic capacitor according to claim 31, wherein, The interface region is a region with a depth of 2 nm from the interface of the adjacent dielectric layer to the interior of the at least one inner electrode layer.

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