Low dropout regulator

Abstract

The utility model provides a low dropout linear regulator, which comprises a flip voltage follower, the flip voltage follower comprises a cascode current mirror, a power tube and a voltage control circuit, the voltage control circuit comprises an error amplifier, the error amplifier forms a voltage follower and is connected to the power tube through the cascode current mirror, and the power tube is connected to the flip voltage follower through the cascode current mirror. The output voltage of the low-dropout linear voltage regulator is stabilized at the reference voltage, the flip voltage follower is adopted, an off-chip capacitor does not need to be arranged, and compared with a traditional low-dropout linear voltage regulator based on a resistor voltage division feedback structure, the low-dropout linear voltage regulator is higher in circuit stability and faster in transient response, so that the low-dropout linear voltage regulator has wider application scenes.

Description

Technical Field

[0001] The utility model belongs to the technical field of circuits and systems, and in particular relates to a low voltage difference linear regulator. Background Art

[0002] Low Dropout Regulator (LDO) is an important device in power management circuits. Its function is to achieve fast and accurate output voltage regulation between small voltage difference input and output voltage to meet circuit application scenarios with extremely high requirements for transient response and load change response. Early LDOs mainly focused on static stability and power consumption, and did not have high requirements for transient response and load change response. With the increasing complexity of LDO application scenarios and the continuous improvement of user-side requirements for power management chip performance, the industry has gradually focused on improving the transient response capability of LDO. Traditional LDO circuit designs mostly use a single-loop structure, which easily causes insufficient load stability of the LDO circuit. In order to maintain the stability of the circuit and enhance the transient response capability of the circuit, it is often necessary to add a large output capacitor to the voltage output end of the LDO circuit, and large capacitors often occupy a large chip area, which does not conform to the development trend of miniaturization and dense integration of chip circuits. Utility Model Content

[0003] The purpose of the utility model is to provide a low voltage drop linear regulator, aiming to solve the problem that the transient response capability of the traditional LDO circuit in complex application scenarios cannot meet the requirements of high-performance power management chips.

[0004] A first aspect of an embodiment of the utility model provides a low voltage drop linear regulator, including a flip voltage follower;

[0005] The flip voltage follower includes a cascode current mirror, a power tube and a voltage control circuit, wherein the source of the power tube is used to input the input voltage of the low voltage difference linear regulator, and the drain of the power tube is used to output the output voltage of the low voltage difference linear regulator; the input end of the cascode current mirror is connected to the output end of the voltage control circuit, and the output end of the cascode current mirror is connected to the drain of the power tube and constitutes the output end of the flip voltage follower; the voltage control circuit includes an error amplifier, the non-inverting input end of the error amplifier is used to input a reference voltage, and the inverting input end of the error amplifier, the output end of the error amplifier and the input end of the cascode current mirror are connected.

[0006] Optionally, the power tube includes a field effect transistor.

[0007] Optionally, the voltage control circuit further includes a current source bias circuit, and the current source bias circuit is used to replicate a reference current;

[0008] The cascode current mirror comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first resistor;

[0009] The source of the first transistor is connected to the drain of the power tube, the drain of the first transistor is connected to the source of the second transistor, the drain of the second transistor is connected to the current source bias circuit, the gate of the first transistor, the gate of the third transistor, the drain of the fourth transistor and the first end of the first resistor are connected, the source of the third transistor is connected to the output end of the error amplifier, the drain of the third transistor is connected to the source of the fourth transistor, and the gate of the second transistor, the gate of the fourth transistor, the second end of the first resistor and the current source bias circuit are connected.

[0010] Optionally, the error amplifier includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;

[0011] The source of the fifth transistor, the source of the sixth transistor and the source of the seventh transistor are connected in common and receive the input voltage, the gate of the fifth transistor, the drain of the seventh transistor and the drain of the ninth transistor are connected, the drain of the fifth transistor and the gate of the eighth transistor are connected in common to form the output end of the error amplifier, the gate of the sixth transistor, the drain of the sixth transistor, the gate of the seventh transistor and the drain of the eighth transistor are connected, the gate of the ninth transistor is used to input the reference voltage, the source of the eighth transistor, the source of the ninth transistor and the drain of the tenth transistor are connected, the gate of the tenth transistor is used to input the bias voltage, and the source of the tenth transistor is grounded.

[0012] Optionally, the low voltage dropout linear regulator further comprises a peak detection circuit, the peak detection circuit is connected to the output end of the low voltage dropout linear regulator, and the peak detection circuit is used to detect the peak voltage output by the low voltage dropout linear regulator and dynamically adjust the bias current in the circuit;

[0013] The flip voltage follower further includes an eleventh transistor and a first capacitor;

[0014] The drain of the eleventh transistor, the first end of the first capacitor and the gate of the power tube are connected, the gate of the eleventh transistor is used to input the reference voltage, the source of the eleventh transistor, the drain of the second transistor and the current source bias circuit are connected, and the second end of the first capacitor is connected to the drain of the power tube.

[0015] A second aspect of the embodiment of the utility model provides a low voltage drop linear regulator, including a first feedback circuit, a power tube and a second feedback circuit;

[0016] The source of the power tube is used to input the input voltage of the low-voltage difference linear regulator, the drain of the power tube is connected to the input end of the first feedback circuit and is used to output the output voltage of the low-voltage difference linear regulator; the output end of the first feedback circuit is connected to the gate of the power tube, and the first feedback circuit is used to negatively feedback and adjust the output voltage of the low-voltage difference linear regulator;

[0017] The second feedback circuit includes an error amplifier and a voltage feedback circuit, the input end of the voltage feedback circuit is connected to the drain of the power tube, the output end of the voltage feedback circuit is connected to the non-inverting input end of the error amplifier, the inverting input end of the error amplifier is used to input a reference voltage, and the output end of the error amplifier is connected to the gate of the power tube; the voltage feedback circuit is used to sample the output voltage of the low-dropout linear regulator and output it as a feedback voltage, and feed the feedback voltage back to the gate of the power tube; the error amplifier is used to negatively feedback and adjust the output voltage of the low-dropout linear regulator according to the feedback voltage and the reference voltage.

[0018] Optionally, the first feedback circuit includes a thirteenth transistor, a fourteenth transistor and a second capacitor;

[0019] The first end of the second capacitor, the source of the thirteenth transistor, the gate of the thirteenth transistor and the drain of the power tube are connected, the drain of the thirteenth transistor, the source of the fourteenth transistor and the current source bias circuit are connected, the gate of the fourteenth transistor is used to input the reference voltage, and the drain of the fourteenth transistor, the gate of the power tube and the second end of the second capacitor are connected.

[0020] Optionally, the voltage feedback circuit includes a second resistor and a third resistor;

[0021] The first end of the second resistor is connected to the drain of the power tube, the second end of the second resistor and the first end of the third resistor are connected to form the output end of the voltage feedback circuit, and the second end of the third resistor is grounded.

[0022] Optionally, the error amplifier includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor;

[0023] The source of the fifteenth transistor and the source of the sixteenth transistor are used to receive the input voltage, the gate of the fifteenth transistor, the gate of the sixteenth transistor, the drain of the sixteenth transistor and the drain of the eighteenth transistor are connected, the drain of the fifteenth transistor and the drain of the seventeenth transistor are connected to form the output end of the error amplifier, the gate of the seventeenth transistor is used to input the reference voltage, the gate of the eighteenth transistor is used to input the feedback voltage, the source of the seventeenth transistor, the source of the eighteenth transistor and the drain of the nineteenth transistor are connected, the gate of the nineteenth transistor is used to input the bias voltage, and the source of the nineteenth transistor is grounded.

[0024] Optionally, the low voltage dropout linear regulator further includes a peak detection circuit, which is connected to the output end of the low voltage dropout linear regulator, and is used to detect the peak voltage output by the low voltage dropout linear regulator and dynamically adjust the bias current in the circuit.

[0025] Compared with the prior art, the beneficial effects of the embodiments of the utility model are: the above-mentioned low-voltage difference linear regulator adopts a flip voltage follower, or adopts a first feedback circuit and a second feedback circuit. Compared with the traditional low-voltage difference linear regulator based on a resistor voltage divider feedback structure, there is no need to set an off-chip capacitor. While reducing the circuit layout area, a better current regulation capability of the circuit is achieved through different control methods, so that the low-voltage difference linear regulator circuit has higher stability and faster transient response, so that the low-voltage difference linear regulator has a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the utility model, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0027] Figure 1 A circuit structure block diagram of a low voltage dropout linear regulator provided in Embodiment 1 of the present utility model;

[0028] Figure 2 A circuit diagram of a low voltage dropout linear regulator provided in Embodiment 1 of the present utility model;

[0029] Figure 3 The low voltage difference linear regulator provided in the first embodiment of the utility model is not using the first capacitor C The simulated loop gain and phase curves at 100 μA and 10 mA load current respectively at 1 time;

[0030] Figure 4 The low voltage difference linear regulator provided in the first embodiment of the utility model uses first capacitors of different sizes. C The simulated loop gain and phase curves at 100 μA load current at 1 time;

[0031] Figure 5 The low voltage difference linear regulator provided in the first embodiment of the utility model uses first capacitors of different sizes. C The simulated loop gain and phase curves at 10 mA load current at 1 time;

[0032] Figure 6 The transient response curve diagram of the low voltage drop linear regulator provided in the first embodiment of the utility model at room temperature (27°C) and different load currents is simulated and measured;

[0033] Figure 7 The transient response curve diagram of the low voltage drop linear regulator provided in the first embodiment of the utility model under different ambient temperatures and 10 mA load current is simulated and measured;

[0034] Figure 8 A circuit structure block diagram of a low voltage dropout linear regulator provided in Embodiment 2 of the present utility model;

[0035] Fig. 9 A circuit diagram of a low voltage dropout linear regulator provided in Embodiment 2 of the present utility model;

[0036] Fig.10 The low voltage difference linear regulator provided in the second embodiment of the utility model does not use the second capacitor C The simulated loop gain and phase curves at 100 μA and 10 mA load current respectively at 2:00;

[0037] Fig.11 The low voltage difference linear regulator provided in the second embodiment of the utility model uses second capacitors of different sizes. C The simulated loop gain and phase curves at 100 μA load current at 2:

[0038] Fig.12 The low voltage difference linear regulator provided in the second embodiment of the utility model uses second capacitors of different sizes. C The simulated loop gain and phase curves at 10 mA load current at 2:

[0039] Fig.13 A Monte Carlo simulation result diagram of a low voltage dropout linear regulator provided in the second embodiment of the present utility model;

[0040] Fig.14The transient response curve diagram of the low voltage drop linear regulator provided in the second embodiment of the utility model at room temperature (27°C) and different load currents;

[0041] Fig.15 The transient response curve diagram of the low voltage dropout linear regulator provided in the second embodiment of the utility model under different ambient temperatures and 10 mA load current is simulated and measured.

[0042] Among them, the reference numerals in the figure are:

[0043] 110-flip voltage follower; 111-power tube; 112-common source and common gate current mirror; 113-first feedback circuit; 120-voltage control circuit; 121-voltage feedback circuit; 130-second feedback circuit; U1-error amplifier;

[0044] M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; M 10 - tenth transistor; M 11 - eleventh transistor; M 12 - twelfth transistor; M 13 -Thirteenth transistor; M 14 - Fourteenth transistor; M 15 - Fifteenth transistor; M 16 - sixteenth transistor; M 17 - Seventeenth transistor; M 18 - Eighteenth transistor; M 19 - 19th transistor; M 20 - 20th transistor; M 21 -21st transistor; M 22 - 22nd transistor; M 23 - Twenty-third transistor; M 24 - 24th transistor; M 25 -25th transistor; M 26 -26th transistor; M 27 -27th transistor; M 28 - 28th transistor; M 29 - 29th transistor; M 30 - 30th transistor; M 31 -31st transistor; M 32 -32nd transistor; M 33 -Thirty-third transistor; MP-field effect transistor;

[0045] C 1- first capacitor;C 2- Second capacitor; C 3- The third capacitor; C 4- the fourth capacitor; C 5- fifth capacitor;

[0046] R 1- first resistor; R 2- Second resistor; R 3- the third resistor; R 4- the fourth resistor; R 5- The fifth resistor. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] It should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly indicate the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0049] The low voltage drop linear regulator provided by the embodiment of the utility model is now described.

[0050] A first aspect of an embodiment of the utility model provides a low voltage drop linear regulator.

[0051] like Figure 1 As shown, Figure 1 This is a circuit structure block diagram of a low voltage dropout linear regulator provided in Embodiment 1 of the present utility model.

[0052] The low voltage dropout linear regulator includes a flip voltage follower 110. The flip voltage follower 110 includes a common source and common gate current mirror 112, a power tube 111 and a voltage control circuit 120. The source of the power tube 111 is used to input the input voltage of the low voltage dropout linear regulator. V IN The drain of the power tube 111 is used to output the output voltage of the low voltage drop linear regulator V OUTThe input end of the cascode current mirror 112 is connected to the output end of the voltage control circuit 120, and the output end of the cascode current mirror 112 is connected to the drain of the power tube 111 and constitutes the output end of the flip voltage follower 110; the voltage control circuit 120 includes an error amplifier U1, and the non-inverting input end of the error amplifier U1 is used to input a reference voltage V ref The inverting input terminal of the error amplifier U1, the output terminal of the error amplifier U1 and the input terminal of the common-source common-gate current mirror 112 are connected.

[0053] In this embodiment, the non-inverting input terminal of the error amplifier U1 is connected to the reference voltage V ref , the inverting input of the error amplifier U1 is connected to the output of the error amplifier U1, and the error amplifier U1 forms a voltage follower, that is, a unity gain amplifier with an amplification factor of 1. At this time, the output voltage of the error amplifier U1 is the reference voltage V ref Since the voltages at both ends of the common-source and common-gate current mirror 112 are equal, the output voltage of the low-dropout linear regulator V OUT is the reference voltage V ref .

[0054] Compared with the low voltage dropout linear regulator without the cascode current mirror 112, the output voltage of the low voltage dropout linear regulator with the cascode current mirror 112 is V OUT The amplitude fluctuation is smaller, which effectively reduces the influence of the channel length modulation effect and improves the copy (or mirror) reference current I bias accuracy.

[0055] A low-voltage-difference linear regulator provided by an embodiment of the utility model adopts a flip voltage follower 110. Compared with a traditional low-voltage-difference linear regulator based on a resistor voltage-divider feedback structure, it does not need to set an off-chip capacitor, and achieves a better current regulation capability of the circuit while reducing the circuit layout area, so that the low-voltage-difference linear regulator circuit has higher stability and faster transient response, and the low-voltage-difference linear regulator has a wider range of application scenarios. Among them, the power tube 111, the common-source and common-gate current mirror 112 and the voltage control circuit 120 in the flip voltage follower 110 can be implemented using structures such as bipolar transistors and metal oxide semiconductor field effect transistors. In an optional embodiment, such as Figure 2 As shown, Figure 2 This is a circuit diagram of a low voltage dropout linear regulator provided in the first embodiment of the present utility model, wherein the power tube 111 is a P-channel field effect transistor MP.

[0056] Please continue reading Figure 1 and Figure 2 In an optional embodiment, the voltage control circuit 120 further includes a current source bias circuit, which is used to replicate the reference current I bias ;

[0057] The cascode current mirror 112 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a first resistor R 1;

[0058] The source of the first transistor M1 is connected to the drain of the power tube 111, the drain of the first transistor M1 is connected to the source of the second transistor M2, the drain of the second transistor M2 is connected to the current source bias circuit, the gate of the first transistor M1, the gate of the third transistor M3, the drain of the fourth transistor M4 and the first resistor R 1, the source of the third transistor M3 is connected to the output end of the error amplifier U1, the drain of the third transistor M3 is connected to the source of the fourth transistor M4, the gate of the second transistor M2, the gate of the fourth transistor M4, the first resistor R The second terminal of 1 is connected to a current source bias circuit.

[0059] The error amplifier U1 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M 10 ;

[0060] The source of the fifth transistor M5, the source of the sixth transistor M6 and the source of the seventh transistor M7 are connected in common and receive the input voltage V IN The gate of the fifth transistor M5, the drain of the seventh transistor M7 and the drain of the ninth transistor M9 are connected, the drain of the fifth transistor M5 and the gate of the eighth transistor M8 are connected together to form the output end of the error amplifier U1, the gate of the sixth transistor M6, the drain of the sixth transistor M6, the gate of the seventh transistor M7 and the drain of the eighth transistor M8 are connected, and the gate of the ninth transistor M9 is used to input a reference voltage V ref , the source of the eighth transistor M8, the source of the ninth transistor M9 and the source of the tenth transistor M 10 The drain of the tenth transistor M 10 The gate of the tenth transistor M is used to input bias voltage. 10 The source is grounded.

[0061] The current source bias circuit includes a twelfth transistor M 12 and the twenty-ninth transistor M 29 ;

[0062] The twelfth transistor M 12 The drain of the second transistor M2 and the drain of the eleventh transistor M 11 The source of the twelfth transistor M 12 The gate of the twenty-ninth transistor M 29 The gate of the twenty-ninth transistor M 29 The drains of the twelfth transistor M are connected together and used for inputting bias voltage. 12 The source of the twenty-ninth transistor M 29 The source is grounded.

[0063] The current source bias circuit further includes a thirty-first transistor M 31 and the thirty-second transistor M 32 ;

[0064] The thirty-first transistor M 31 The drain of the thirty-first transistor M 31 The gate of the thirty-second transistor M 32 The gates of the thirty-second transistor M are connected in common and used for inputting bias voltage. 32 The drain and the first resistor R 1 is connected to the second end of the thirty-first transistor M 31 The source of the thirty-second transistor M 32 The source is grounded.

[0065] Furthermore, if Figure 2 As shown, in an optional embodiment, the low voltage dropout linear regulator further includes a peak detection circuit, which is connected to the output end of the low voltage dropout linear regulator. The peak detection circuit is used to detect the peak voltage output by the low voltage dropout linear regulator and dynamically adjust the bias current in the circuit. V OUT When fluctuations occur, the output voltage is reduced by feedback regulating the bias current in the circuit V OUT fluctuation.

[0066] The peak detection circuit includes a fourth resistor R 4. Fifth resistor R 5. The fourth capacitor C 4 and the fifth capacitor C 5.

[0067] The low voltage drop linear regulator further includes a current mirror circuit including a tenth transistor M 10 , the twelfth transistor M 12 , the twenty-first transistor M 21 , the twenty-second transistor M 22 , the twenty-third transistor M 23, the twenty-fourth transistor M 24 25th transistor M 25 , the twenty-sixth transistor M 26 , the twenty-seventh transistor M 27 , the twenty-eighth transistor M 28 , the twenty-ninth transistor M 29 , the 30th transistor M 30 , the thirty-first transistor M 31 and the thirty-second transistor M 32 .

[0068] Current mirror circuit is used to realize reference current I bias The mirror transmission includes a plurality of the above-mentioned current source bias circuits. Among them, the twelfth transistor M 12 The twenty-ninth transistor M 29 The current source bias circuit is formed, and the twenty-seventh transistor M 27 The twenty-fifth transistor M 25 The current source bias circuit is composed of the twenty-fifth transistor M 25 The twenty-sixth transistor M 26 The twenty-third transistor M forms a current source bias circuit. 23 and the twenty-fourth transistor M 24 The current source bias circuit is formed, the twenty-eighth transistor M 28 and the thirtieth transistor M 30 The current source bias circuit is composed of the twenty-first transistor M 21 and the twenty-second transistor M 22 The current source bias circuit is composed of the thirty-first transistor M 31 and the tenth transistor M 10 The current source bias circuit is composed of the thirty-first transistor M 31 and the thirty-second transistor M 32 Form a current source bias circuit.

[0069] The twenty-first transistor M 21 The source of the twenty-second transistor M 22 The source of the twenty-fifth transistor M 25 The source of the twenty-sixth transistor M 26 The source of the twenty-seventh transistor M 27 The source is used to receive the input voltage V IN ; The twenty-first transistor M 21 The gate of the twenty-second transistor M 22 The gate of the twenty-second transistor M 22 The drain of the thirtieth transistor M 30 The drain of the twenty-first transistor M is connected21 The drain of the twenty-seventh transistor M is connected to the gate of the power tube 111. 27 The drain of the twenty-ninth transistor M 29 The drain of the twenty-ninth transistor M 29 The gate of the twelfth transistor M 12 The gate of the twenty-sixth transistor M is connected 26 The drain of the twenty-eighth transistor M 28 The drain of the twenty-eighth transistor M 28 The gate and fifth resistor R 5 is connected to the first end of the twenty-fifth transistor M 25 The drain of the twenty-fifth transistor M 25 The gate of the twenty-fourth transistor M 24 The drain of the twenty-sixth transistor M 26 The gate and the fourth resistor R 4 is connected to the first end of the twenty-seventh transistor M 27 The gate and the fourth capacitor C 4 and the first terminal of the fourth resistor R 4 is connected to the second end of the thirtieth transistor M 30 The gate and the fifth capacitor C 5 first terminal and fifth resistor R 5 is connected to the second end of the fourth capacitor C The second terminal of 4 and the fifth capacitor C The second end of 5 is connected to the output end of the low voltage drop linear regulator, and the twenty-third transistor M 23 The drain of the twenty-third transistor M 23 The gate of the twenty-fourth transistor M 24 The gates of the thirty-first transistor M are connected in common and used for inputting bias voltage. 31 The drain of the thirty-first transistor M 31 The gate of the thirty-second transistor M 32 The gate of the tenth transistor M 10 The gates of the thirty-second transistor M are connected in common and used for inputting bias voltage. 32 The drain and the first resistor R The second end of the tenth transistor M is connected to 10 The source of the twelfth transistor M 12 The source of the twenty-third transistor M 23 The source of the twenty-fourth transistor M 24 The source of the twenty-eighth transistor M 28 The source of the twenty-ninth transistor M 29 The source of the thirtieth transistor M 30 The source of the thirty-first transistor M 31The source of the thirty-second transistor M 32 The source is grounded.

[0070] The output voltage of the low dropout linear regulator V OUT Through the fourth capacitor C 4 and the fifth capacitor C 5 are fed back to the twenty-seventh transistor M 27 The gate and the thirtieth transistor M 30 The gate of the twenty-seventh transistor M 27 , the twenty-ninth transistor M 29 Adjust the twelfth transistor M 12 The gate voltage of the 30th transistor M 30 , the twenty-second transistor M 22 and the twenty-first transistor M 21 The voltage is fed back to the gate of the power tube 111 .

[0071] The flip voltage follower 110 further includes an eleventh transistor M 11 and the first capacitor C 1;

[0072] The eleventh transistor M 11 The drain, first capacitor C The first end of the transistor 1 is connected to the gate of the power transistor 111. 11 The gate is used to input the reference voltage V ref , the eleventh transistor M 11 The source of the second transistor M2, the drain of the second transistor M2 and the twelfth transistor M 12 The drain connection of the first capacitor C 1, the drain of the power tube 111 and the output end of the low voltage difference linear regulator are connected.

[0073] like Figures 3 to 5 As shown, Figure 3 The low voltage difference linear regulator provided in the first embodiment of the utility model is not using the first capacitor C The simulated loop gain and phase curves at 100 μA and 10 mA load current respectively. Figure 4 The low voltage difference linear regulator provided in the first embodiment of the utility model uses first capacitors of different sizes. C The simulated loop gain and phase curves at 100 μA load current are shown in Figure 1. Figure 5 The low voltage difference linear regulator provided in the first embodiment of the utility model uses first capacitors of different sizes. C 1 at 10 mA load current.

[0074] In the utility model, the low voltage drop linear regulator circuit uses Miller capacitors for frequency compensation. Figure 3 As shown in the figure, the simulated phase margins of the low-dropout linear regulator without Miller capacitor at 100 μA and 10 mA load currents are 37.6° and 40.74° respectively. In general, the loop phase margin must be at least 45° for the loop to be stable. Excessive phase margin can make the loop more stable, but its response rate will drop significantly. When the phase margin is 60°, the loop can take into account the response rate and achieve rapid stability. Therefore, in the present invention, the design target of the loop phase margin is 60°. In order to further increase the phase margin, the first capacitor is used. C 1 acts as a Miller capacitor to compensate the circuit frequency. Figure 4 and Figure 5 As shown, the circuit adds a first capacitor C 1, the phase margin increases significantly. At a load current of 100 μA, the first capacitor C When 1 is 2 pF, 4 pF, and 8 pF, the phase margin of the loop is 51.2°, 58.2°, and 73.9°, respectively. Under a load current of 10 mA, the first capacitor C When 1 is 2 pF, 4 pF and 8 pF respectively, the phase margin of the loop is 75.7°, 83.7° and 94.9° respectively. Considering the phase margin, transient response, capacitor area and the effect of capacitance change caused by processing error on the phase margin under different load currents, the first capacitor is selected. C The capacitance value of 1 is 4 pF.

[0075] In order to experimentally verify the circuit performance of the low-dropout linear regulator provided by the embodiment of the utility model, a low-dropout linear regulator chip was manufactured using a 65-nm SOI CMOS process, a test circuit board for the low-dropout linear regulator chip was manufactured using a printed circuit board (PCB) process, and the bare die of the low-dropout linear regulator chip was flip-chip soldered on the test circuit board for its circuit performance test.

[0076] like Figure 6 As shown, Figure 6 The transient response curves of the low-dropout linear regulator provided in the first embodiment of the utility model at room temperature (27°C) and different load currents are simulated and measured. The low-dropout linear regulator chip test system is powered by a DC power supply, and a signal generator is used to provide a square wave with a falling edge / rising edge time of 500 ns to the low-dropout linear regulator chip, and an oscilloscope is used to display the output voltage. V OUT The waveform of Figure 6 It can be seen that the simulation and measurement results are in good agreement. Under a load current of 10 mA, the measured output voltageV OUT The overshoot amplitude is 381 mV, the recovery time is 470 ns, the undershoot amplitude is 450 mV, and the recovery time is 970 ns. The transient response performance indicators at 1 mA and 5 mA load currents are better than the above indicators.

[0077] like Figure 7 As shown, Figure 7 The transient response curves of the low voltage drop linear regulator provided in the first embodiment of the utility model under different ambient temperatures and 10 mA load current are simulated and measured. Figure 7 It can be seen that the simulation and measurement results are in good agreement. When the temperature is 100 °C, the measured output voltage V OUT The overshoot amplitude is 325 mV, the recovery time is 700 ns, the undershoot amplitude is 406.2 mV, and the recovery time is 920 ns. When the temperature is −40 °C, the measured output voltage V OUT The overshoot amplitude is 400 mV with a recovery time of 740 ns, and the undershoot amplitude is 437.5 mV with a recovery time of 900 ns.

[0078] A second aspect of the embodiments of the present invention provides a low voltage drop linear regulator.

[0079] like Figure 8 As shown, Figure 8 The circuit structure block diagram of the low voltage drop linear regulator provided in the second embodiment of the utility model includes a power tube 111 , a first feedback circuit 113 and a second feedback circuit 130 .

[0080] The source of the power tube 111 is used to input the input voltage of the low voltage drop linear regulator V IN The drain of the power tube 111 is connected to the input end of the first feedback circuit 113 and is used to output the output voltage of the low voltage drop linear regulator. V OUT The output end of the first feedback circuit 113 is connected to the gate of the power tube 111, and the first feedback circuit 113 is used for negative feedback to adjust the output voltage of the low-dropout linear regulator. V OUT The second feedback circuit 130 includes an error amplifier U1 and a voltage feedback circuit 121. The input end of the voltage feedback circuit 121 is connected to the drain of the power tube 111. The output end of the voltage feedback circuit 121 is connected to the positive input end of the error amplifier U1. The negative input end of the error amplifier U1 is used to input a reference voltage. V refThe output end of the error amplifier U1 is connected to the gate of the power tube 111; the voltage feedback circuit 121 is used to convert the output voltage of the low voltage drop linear regulator V OUT The sampling output is a feedback voltage, and the feedback voltage is fed back to the gate of the power tube 111; the error amplifier U1 is used to generate a voltage according to the feedback voltage and the reference voltage. V ref Negative feedback regulates the output voltage of a low dropout linear regulator V OUT .

[0081] In this embodiment, the first feedback circuit 113 constitutes an inner loop feedback regulation circuit for adjusting the output voltage of the low voltage drop linear regulator V OUT Negative feedback is given to the gate of the power tube 111 to reduce the output voltage V OUT The second feedback circuit 130 constitutes an outer loop feedback regulation circuit so that the output voltage V OUT The voltage is stabilized at a preset voltage and forms a dual-loop structure together with the first feedback circuit 113 .

[0082] A low-voltage dropout linear regulator provided by an embodiment of the utility model adopts a dual-loop structure composed of a first feedback circuit 113 and a second feedback circuit 130. Compared with a traditional low-voltage dropout linear regulator based on a resistor voltage divider feedback structure, it does not need to set an off-chip capacitor, and achieves better current regulation capability of the circuit while reducing the circuit layout area, so that the low-voltage dropout linear regulator circuit has higher stability and faster transient response, so that the low-voltage dropout linear regulator has a wider range of application scenarios. Among them, the power tube 111, the first feedback circuit 113 and the second feedback circuit 130 in the dual-loop structure can be implemented using structures such as bipolar transistors and metal oxide semiconductor field effect transistors. In an optional embodiment, such as Fig. 9 As shown, Fig. 9 This is a circuit diagram of a low voltage dropout linear regulator provided in the first embodiment of the present utility model, wherein the power tube 111 is a P-channel field effect transistor MP.

[0083] Please continue reading Figure 8 and Fig. 9 In an optional embodiment, the first feedback circuit 113 includes a thirteenth transistor M 13 , the fourteenth transistor M 14 and the second capacitor C 2;

[0084] Second capacitor C 2, the first terminal of the thirteenth transistor M 13 The source of the thirteenth transistor M 13The gate of the thirteenth transistor M is connected to the drain of the power tube 111. 13 The drain of the fourteenth transistor M 14 The source of the fourteenth transistor M is connected to the current source bias circuit. 14 The gate is used to input the reference voltage V ref , the fourteenth transistor M 14 The drain of the power tube 111, the gate of the power tube 111 and the second capacitor C 2 second end connection.

[0085] The voltage feedback circuit 121 can be implemented by using a mutual inductor, a resistor voltage divider circuit, etc. In an optional embodiment, the voltage feedback circuit 121 includes a second resistor R 2 and the third resistor R 3;

[0086] Second resistor R The first end of 2 is connected to the drain of the power tube 111, and the second resistor R 2 and the second terminal of the third resistor R The first end of the third resistor 3 is connected to the output end of the voltage feedback circuit 121. R The second end of 3 is grounded.

[0087] In this embodiment, the feedback voltage is equal to V OUT × R 3 / ( R 2+ R 3) Through the feedback regulation of the error amplifier U1 on the power tube 111, the voltage at the non-inverting input terminal of the error amplifier U1 is equal to the voltage at the inverting input terminal, that is, V ref = V OUT × R 3 / ( R 2+ R 3) Therefore, V OUT = V ref × ( R 2+ R 3) / R 3, and through the dual-loop feedback circuit, the output voltage of the low-dropout linear regulator is realized V OUT Stable V ref × ( R 2+ R 3) / R 3.

[0088] Please continue reading Figure 8and Fig. 9 In an optional embodiment, the error amplifier U1 includes a fifteenth transistor M 15 , the sixteenth transistor M 16 , the seventeenth transistor M 17 , the eighteenth transistor M 18 and the nineteenth transistor M 19 ;

[0089] The fifteenth transistor M 15 The source of the sixteenth transistor M 16 The source is used to receive the input voltage V IN , the fifteenth transistor M 15 The gate of the sixteenth transistor M 16 The gate of the sixteenth transistor M 16 The drain of the eighteenth transistor M 18 The drain of the fifteenth transistor M is connected 15 The drain of the seventeenth transistor M 17 The drain of the seventeenth transistor M is connected to the output terminal of the error amplifier U1. 17 The gate is used to input the reference voltage V ref , the eighteenth transistor M 18 The gate of the seventeenth transistor M is used to input the feedback voltage. 17 The source of the eighteenth transistor M 18 The source of the nineteenth transistor M 19 The drain of the nineteenth transistor M is connected 19 The gate of the nineteenth transistor M is used to input bias voltage. 19 The source is grounded.

[0090] In this embodiment, the thirteenth transistor M 13 , the fourteenth transistor M 14 and the second capacitor C 2 constitutes an inner loop feedback regulation circuit, which is used to adjust the output voltage of the low voltage drop linear regulator V OUT Negative feedback is given to the gate of the power tube 111 to reduce the output voltage V OUT The amplitude fluctuates; the fifteenth transistor M 15 , the sixteenth transistor M 16 , the seventeenth transistor M 17 , the eighteenth transistor M 18 , the nineteenth transistor M 19 , the second resistor R 2 and the third resistor R 3 constitutes an outer loop feedback regulation circuit to make the output voltage VOUT It stabilizes at a preset voltage and forms a dual-loop structure together with the inner-loop feedback regulation circuit.

[0091] Furthermore, if Fig. 9 As shown, the low voltage dropout linear regulator also includes a peak detection circuit, which is connected to the output end of the low voltage dropout linear regulator. The peak detection circuit is used to detect the peak voltage output by the low voltage dropout linear regulator and dynamically adjust the bias current in the circuit. V OUT When fluctuations occur, the output voltage is reduced by feedback regulating the bias current in the circuit V OUT fluctuation.

[0092] The peak detection circuit includes a fourth resistor R 4. Fifth resistor R 5. The fourth capacitor C 4 and the fifth capacitor C 5.

[0093] The low voltage drop linear regulator further includes a current mirror circuit, which includes a nineteenth transistor M 19 , the twentieth transistor M 20 , the twenty-first transistor M 21 , the twenty-second transistor M 22 , the twenty-third transistor M 23 , the twenty-fourth transistor M 24 25th transistor M 25 , the twenty-sixth transistor M 26 , the twenty-seventh transistor M 27 , the twenty-eighth transistor M 28 , the twenty-ninth transistor M 29 , the 30th transistor M 30 and the thirty-third transistor M 33 .

[0094] Current mirror circuit is used to realize reference current I bias The mirror transmission includes a plurality of the above-mentioned current source bias circuits. Among them, the nineteenth transistor M 19 The thirty-third transistor M 33 The current source bias circuit is composed of the twentieth transistor M 20 The twenty-ninth transistor M 29 The current source bias circuit is composed of the twenty-first transistor M 21 The twenty-second transistor M 22 The twenty-third transistor M forms a current source bias circuit. 23 and the twenty-fourth transistor M 24The current source bias circuit is composed of the twenty-fifth transistor M 25 and the twenty-sixth transistor M 26 The current source bias circuit is composed of the twenty-fifth transistor M 25 and the twenty-seventh transistor M 27 The current source bias circuit is formed, the twenty-eighth transistor M 28 and the thirtieth transistor M 30 Form a current source bias circuit.

[0095] The twenty-first transistor M 21 The source of the twenty-second transistor M 22 The source of the twenty-fifth transistor M 25 The source of the twenty-sixth transistor M 26 The source of the twenty-seventh transistor M 27 The source is used to receive the input voltage V IN ; The twenty-first transistor M 21 The gate of the twenty-second transistor M 22 The gate of the twenty-second transistor M 22 The drain of the thirtieth transistor M 30 The drain of the twenty-first transistor M is connected 21 The drain of the twenty-seventh transistor M is connected to the gate of the power tube 111. 27 The drain of the twenty-ninth transistor M 29 The drain of the twenty-ninth transistor M 29 The gate of the 20th transistor M 20 The gate of the twenty-sixth transistor M is connected 26 The drain of the twenty-eighth transistor M 28 The drain of the twenty-eighth transistor M 28 The gate and fifth resistor R 5 is connected to the first end of the twenty-fifth transistor M 25 The drain of the twenty-fifth transistor M 25 The gate of the twenty-fourth transistor M 24 The drain of the twenty-sixth transistor M 26 The gate and the fourth resistor R 4 is connected to the first end of the twenty-seventh transistor M 27 The gate and the fourth capacitor C 4 and the first terminal of the fourth resistor R 4 is connected to the second end of the thirtieth transistor M 30 The gate and the fifth capacitor C 5 first terminal and fifth resistor R 5 is connected to the second end of the fourth capacitor C The second terminal of 4 and the fifth capacitor C5 is connected to the output terminal of the low voltage drop linear regulator, and the twenty-third transistor M 23 The drain of the twenty-third transistor M 23 The gate of the twenty-fourth transistor M 24 The gates of the thirty-third transistor M are connected in common and used for inputting bias voltage. 33 The drain of the thirty-third transistor M 33 The gate of the nineteenth transistor M 19 The gates of the nineteenth transistor M are connected in common and used for inputting bias voltage; 19 The source of the twentieth transistor M 20 The source of the twenty-third transistor M 23 The source of the twenty-fourth transistor M 24 The source of the twenty-eighth transistor M 28 The source of the twenty-ninth transistor M 29 The source of the thirtieth transistor M 30 The source of the thirty-third transistor M 33 The source is grounded.

[0096] The output voltage of the low dropout linear regulator V OUT Through the fourth capacitor C 4 and the fifth capacitor C 5 are fed back to the twenty-seventh transistor M 27 The gate and the thirtieth transistor M 30 The gate of the twenty-seventh transistor M 27 , the twenty-ninth transistor M 29 Adjust the twentieth transistor M 20 The gate voltage of the 30th transistor M 30 , the twenty-second transistor M 22 and the twenty-first transistor M 21 The voltage is fed back to the gate of the power tube 111 .

[0097] See also Figures 10 to 12 , Fig.10 The low voltage difference linear regulator provided in the second embodiment of the utility model does not use the second capacitor C The simulated loop gain and phase curves at 100 μA and 10 mA load currents are shown in Figure 2. Fig.11 The low voltage difference linear regulator provided in the second embodiment of the utility model uses second capacitors of different sizes. C The simulated loop gain and phase curves at 100 μA load current at 2, Fig.12 The low voltage difference linear regulator provided in the second embodiment of the utility model uses second capacitors of different sizes. C2 at 10 mA load current for the simulated loop gain and phase curves.

[0098] In the utility model, the low voltage drop linear regulator circuit uses Miller capacitors for frequency compensation. Fig.10 As shown in the figure, the simulated phase margins of the low-dropout linear regulator without Miller capacitor at 100 μA and 10 mA load current are 45.22° and 73.71° respectively. In order to further increase the phase margin, a second capacitor is used. C 2 acts as Miller capacitor to compensate the frequency of the circuit. Fig.11 and Fig.12 As shown, the circuit adds a second capacitor C 2, the phase margin increases significantly. At a load current of 100 μA, the second capacitor C When the second capacitor is 2 pF, 4 pF, and 8 pF, the phase margin of the loop is 73.1°, 81.1°, and 92.3°, respectively. C When the capacitance 2 is 2 pF, 4 pF and 8 pF respectively, the phase margin of the loop is 82.4°, 89.6° and 98.5° respectively. Considering the phase margin, transient response, capacitance area and the effect of capacitance change caused by processing error on the phase margin under different load currents, the second capacitor is selected. C The capacitance value of 2 is 4 pF.

[0099] In the above LDO linear regulator circuit configuration, see Fig.13 , Fig.13 This is a Monte Carlo simulation result diagram of the low-dropout linear regulator provided by the second embodiment of the utility model. The Monte Carlo simulation results show that when the number of samples of the low-dropout linear regulator is 500, the output voltage of the low-dropout linear regulator V OUT The average value is 1.3009 V, and the output voltage V OUT The standard deviation of the low dropout linear regulator output voltage is 0.0294 V. V OUT In (−3 σ , 3 σ ) The number of samples within the confidence interval is 498, and the corresponding sample ratio is 99.60%. The output voltage V OUT In (− σ , σ )The relative deviation within the confidence interval is 2.26%.

[0100] In order to experimentally verify the circuit performance of the low-dropout linear regulator provided by the embodiment of the utility model, a low-dropout linear regulator chip was manufactured using a 65-nm SOI CMOS process, a test circuit board for the low-dropout linear regulator chip was manufactured using a PCB process, and the bare die of the low-dropout linear regulator chip was flip-chip soldered on the test circuit board for its circuit performance test.

[0101] See also Fig.14 , Fig.14 The transient response curves of the low-dropout linear regulator provided in the second embodiment of the utility model at room temperature (27°C) and different load currents are simulated and measured. The low-dropout linear regulator chip test system is powered by a DC power supply, and a signal generator is used to provide a square wave with a falling edge / rising edge time of 500 ns to the low-dropout linear regulator chip, and an oscilloscope is used to display the output voltage. V OUT The waveform of Fig.14 It can be seen that the simulation and measurement results are in good agreement. Under a load current of 10 mA, the measured output voltage V OUT The overshoot amplitude is 177.5 mV, the recovery time is 930 ns, the undershoot amplitude is 182.5 mV, and the recovery time is 690 ns. The transient response performance indicators at 1 mA and 5 mA load currents are better than the above indicators.

[0102] See also Fig.15 , Fig.15 The transient response curves of the low voltage drop linear regulator provided in the second embodiment of the utility model under different ambient temperatures and 10 mA load current are simulated and measured. Fig.15 It can be seen that the simulation and measurement results are in good agreement. When the temperature is 100 °C, the measured output voltage V OUT The overshoot amplitude is 195 mV, the recovery time is 920 ns, the undershoot amplitude is 194 mV, and the recovery time is 640 ns. When the temperature is −40 °C, the measured output voltage V OUT The overshoot amplitude is 187.5 mV with a recovery time of 940 ns, and the undershoot amplitude is 186.5 mV with a recovery time of 660 ns.

[0103] In the embodiments provided by the present invention, it should be understood that, first, the circuit structure of the low-voltage dropout linear regulator is only schematic, not unique, and is only an achievable circuit structure. The circuit structure, circuit layout, and transistor parameters can also be optimized according to different application environments to achieve a low-voltage dropout linear regulator chip with better circuit performance and smaller circuit size; second, the circuit design scheme can be improved to achieve a low-voltage dropout linear regulator with other functions. In the description of the embodiments of the present invention, the circuit structure given is a preferred structure. With reference to one of the embodiments of the present invention, the circuit structure of each part can be modified to further obtain the actual required performance.

[0104] The above-mentioned embodiments are only used to illustrate the technical solutions of the utility model, rather than to limit it. Those skilled in the art should understand that the technical solutions described in the above-mentioned embodiments can be modified, or some of the technical features can be replaced by equivalents; these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and principles of the utility model, and should be included in the protection scope of the utility model.

Claims

1. A low voltage dropout linear regulator, characterized in that: Including flip voltage follower; The flip voltage follower includes a cascode current mirror, a power tube and a voltage control circuit, wherein the source of the power tube is used to input the input voltage of the low voltage difference linear regulator, and the drain of the power tube is used to output the output voltage of the low voltage difference linear regulator; the input end of the cascode current mirror is connected to the output end of the voltage control circuit, and the output end of the cascode current mirror is connected to the drain of the power tube and constitutes the output end of the flip voltage follower; the voltage control circuit includes an error amplifier, the non-inverting input end of the error amplifier is used to input a reference voltage, and the inverting input end of the error amplifier, the output end of the error amplifier and the input end of the cascode current mirror are connected.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The power tube includes a field effect transistor.

3. The low voltage dropout linear regulator according to claim 1, characterized in that: The voltage control circuit further comprises a current source bias circuit, wherein the current source bias circuit is used to replicate a reference current; The cascode current mirror comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first resistor; The source of the first transistor is connected to the drain of the power tube, the drain of the first transistor is connected to the source of the second transistor, the drain of the second transistor is connected to the current source bias circuit, the gate of the first transistor, the gate of the third transistor, the drain of the fourth transistor and the first end of the first resistor are connected, the source of the third transistor is connected to the output end of the error amplifier, the drain of the third transistor is connected to the source of the fourth transistor, and the gate of the second transistor, the gate of the fourth transistor, the second end of the first resistor and the current source bias circuit are connected.

4. The low voltage dropout linear regulator according to claim 2, characterized in that: The error amplifier includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The source of the fifth transistor, the source of the sixth transistor and the source of the seventh transistor are connected in common and receive the input voltage, the gate of the fifth transistor, the drain of the seventh transistor and the drain of the ninth transistor are connected, the drain of the fifth transistor and the gate of the eighth transistor are connected in common to form the output end of the error amplifier, the gate of the sixth transistor, the drain of the sixth transistor, the gate of the seventh transistor and the drain of the eighth transistor are connected, the gate of the ninth transistor is used to input the reference voltage, the source of the eighth transistor, the source of the ninth transistor and the drain of the tenth transistor are connected, the gate of the tenth transistor is used to input the bias voltage, and the source of the tenth transistor is grounded.

5. The low voltage dropout linear regulator according to claim 3, characterized in that: The low voltage dropout linear regulator further comprises a peak detection circuit, the peak detection circuit is connected to the output end of the low voltage dropout linear regulator, and the peak detection circuit is used to detect the peak voltage output by the low voltage dropout linear regulator and dynamically adjust the bias current in the circuit; The flip voltage follower further includes an eleventh transistor and a first capacitor; The drain of the eleventh transistor, the first end of the first capacitor and the gate of the power tube are connected, the gate of the eleventh transistor is used to input the reference voltage, the source of the eleventh transistor, the drain of the second transistor and the current source bias circuit are connected, and the second end of the first capacitor is connected to the drain of the power tube.

6. A low voltage dropout linear regulator, characterized in that: It includes a first feedback circuit, a power tube and a second feedback circuit; The source of the power tube is used to input the input voltage of the low-voltage difference linear regulator, the drain of the power tube is connected to the input end of the first feedback circuit and is used to output the output voltage of the low-voltage difference linear regulator; the output end of the first feedback circuit is connected to the gate of the power tube, and the first feedback circuit is used to negatively feedback and adjust the output voltage of the low-voltage difference linear regulator; The second feedback circuit includes an error amplifier and a voltage feedback circuit, the input end of the voltage feedback circuit is connected to the drain of the power tube, the output end of the voltage feedback circuit is connected to the non-inverting input end of the error amplifier, the inverting input end of the error amplifier is used to input a reference voltage, and the output end of the error amplifier is connected to the gate of the power tube; The voltage feedback circuit is used to sample the output voltage of the low voltage drop linear regulator and output it as a feedback voltage, and feed the feedback voltage back to the gate of the power tube; The error amplifier is used for negatively feedback regulating the output voltage of the low voltage dropout linear regulator according to the feedback voltage and the reference voltage.

7. The low voltage dropout linear regulator according to claim 6, characterized in that: The first feedback circuit includes a thirteenth transistor, a fourteenth transistor and a second capacitor; The first end of the second capacitor, the source of the thirteenth transistor, the gate of the thirteenth transistor and the drain of the power tube are connected, the drain of the thirteenth transistor, the source of the fourteenth transistor and the current source bias circuit are connected, the gate of the fourteenth transistor is used to input the reference voltage, and the drain of the fourteenth transistor, the gate of the power tube and the second end of the second capacitor are connected.

8. The low voltage dropout linear regulator according to claim 6, characterized in that: The voltage feedback circuit includes a second resistor and a third resistor; The first end of the second resistor is connected to the drain of the power tube, the second end of the second resistor and the first end of the third resistor are connected to form the output end of the voltage feedback circuit, and the second end of the third resistor is grounded.

9. The low dropout linear regulator according to claim 6, characterized in that: The error amplifier includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor; The source of the fifteenth transistor and the source of the sixteenth transistor are used to receive the input voltage, the gate of the fifteenth transistor, the gate of the sixteenth transistor, the drain of the sixteenth transistor and the drain of the eighteenth transistor are connected, the drain of the fifteenth transistor and the drain of the seventeenth transistor are connected to form the output end of the error amplifier, the gate of the seventeenth transistor is used to input the reference voltage, the gate of the eighteenth transistor is used to input the feedback voltage, the source of the seventeenth transistor, the source of the eighteenth transistor and the drain of the nineteenth transistor are connected, the gate of the nineteenth transistor is used to input the bias voltage, and the source of the nineteenth transistor is grounded.

10. The low dropout linear regulator according to claim 7, characterized in that: The low voltage difference linear regulator also includes a peak detection circuit, which is connected to the output end of the low voltage difference linear regulator. The peak detection circuit is used to detect the peak voltage output by the low voltage difference linear regulator and dynamically adjust the bias current in the circuit.

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