Low-power-consumption energy storage management circuit for fitting temperature measuring device

Abstract

The low-power-consumption energy storage management circuit comprises an input end Vin and an output end Vout, the input end Vin is respectively connected with a source electrode of a PMOS (P-channel Metal Oxide Semiconductor) tube Q1, a drain electrode of an NMOS (N-channel Metal Oxide Semiconductor) tube Q2 and a drain electrode of an NMOS tube Q3, a grid electrode of the PMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2, and a grid electrode of the NMOS tube Q3 is connected with the output end Vout. The drain electrode of the PMOS tube Q1 is respectively connected with the positive electrode of the polar capacitor C26, the VDD port of the voltage detection chip U1 and the output end Vout, the negative electrode of the polar capacitor C26 and the GND port of the voltage detection chip U1 are both grounded, the VOUT port of the voltage detection chip U1 is connected with the grid electrode of the NMOS tube Q3, the drain electrode of the NMOS tube Q3 is connected with the grid electrode of the NMOS tube Q2, and the source electrode of the NMOS tube Q3 and the source electrode of the NMOS tube Q2 are both grounded; according to the utility model, the production, installation and maintenance costs are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of energy storage, in particular to a low-power energy storage management circuit for a hardware temperature measuring device. Background Art

[0002] There are many metal parts used in transmission lines, such as suspension clamps, tension clamps, conductor connection fittings, etc., which are prone to heat and burns under long-term high-temperature and high-load operation. Among them, surface oxidation of drainage plates, fittings, loose fastening bolts, poor contact of contacts, and poor contact of fitting lap joints are all causes of heating failures of wire clamps, and serious ones may even cause power outages. The operating temperature of conductor fittings is an important parameter for the healthy operation of transmission lines. At present, the methods for fitting temperature detection are divided into drone infrared sampling and installation of fitting temperature online monitoring devices. Drone infrared temperature measurement cannot achieve real-time monitoring, and operation and maintenance personnel are required to go to the site to measure each tower one by one. Due to geographical location and time constraints, the data accuracy is low and the work efficiency is not high. At present, important load lines have installed fitting temperature online monitoring devices. Fitting temperature online monitoring devices are generally powered by solar energy. In order to ensure stable and sufficient power supply, most of them cannot be designed as an integrated online monitoring device, or they are bulky, which increases the production cost of the product and causes many inconveniences for installation and later maintenance.

[0003] The online temperature monitoring devices for hardware fittings are generally powered by solar energy. In order to ensure stable and sufficient power supply, most of them cannot be designed to be integrated, or they are bulky, which increases the production cost of the product and causes many inconveniences for installation and subsequent maintenance. Utility Model Content

[0004] In order to ensure the stability and reliability of solar power generation of hardware temperature monitoring devices, the purpose of the utility model is to provide a low-power energy storage management circuit for hardware temperature measuring devices. The utility model greatly reduces the volume of the hardware temperature measuring device and reduces the production, installation and maintenance costs.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a low-power energy storage management circuit for a hardware temperature measuring device, including an input terminal Vin and an output terminal Vout, the solar panel inlet line is welded to the input terminal Vin, and also includes a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a polarity capacitor C26 and a voltage detection chip U1; the input terminal Vin is respectively connected to the source of the PMOS tube Q1, the drain of the NMOS tube Q2, and the drain of the NMOS tube Q3, and the gate of the PMOS tube Q1 is connected to the drain of the NMOS tube Q3. The gate of the NMOS tube Q3 is connected to the drain of the NMOS tube Q2, the drain of the PMOS tube Q1 is respectively connected to the positive electrode of the polarity capacitor C26, the VDD port of the voltage detection chip U1 and the output end Vout, the negative electrode of the polarity capacitor C26 and the GND port of the voltage detection chip U1 are both grounded, the VOUT port of the voltage detection chip U1 is connected to the gate of the NMOS tube Q3, the drain of the NMOS tube Q3 is connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q3 and the source of the NMOS tube Q2 are both grounded.

[0006] As a further improvement of the present invention, a Schottky diode D12 is connected in series between the input terminal Vin and the source of the PMOS tube Q1.

[0007] As a further improvement of the present invention, a filter capacitor C30 is connected in parallel between the two ends of the polarity capacitor C26.

[0008] As a further improvement of the present invention, a transient diode D10 is connected in parallel between the VDD port and the GND port of the voltage detection chip U1.

[0009] As a further improvement of the present invention, the model of the voltage detection chip U1 is BL8506-35CRM.

[0010] The beneficial effects of the utility model are:

[0011] The utility model designs an energy management circuit, which can be applied to ≥50cm 2 The solar panel has the function of providing stable and reliable electricity for the monitoring device when the illumination is 1 / 2 of that of the flat panel. It provides a new solution for the integrated appearance design of the monitoring device, greatly reduces the volume of the hardware temperature measuring device, reduces the production, installation and maintenance costs, and also effectively ensures the stability and reliability of the sensor's working energy. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The figure is a schematic diagram of the circuit structure of an embodiment of the utility model. DETAILED DESCRIPTION

[0013] The embodiments of the present utility model are described in detail below with reference to the accompanying drawings.

[0014] Example

[0015] like Figure 1 As shown, a low-power energy storage management circuit for a hardware temperature measuring device includes an input terminal Vin and an output terminal Vout, a solar panel inlet line is welded to the input terminal Vin, and also includes a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a polarity capacitor C26 and a voltage detection chip U1; the input terminal Vin is respectively connected to the source of the PMOS tube Q1, the drain of the NMOS tube Q2, and the drain of the NMOS tube Q3, the gate of the PMOS tube Q1 is connected to the drain of the NMOS tube Q2, the drain of the PMOS tube Q1 is respectively connected to the positive electrode of the polarity capacitor C26, the VDD port of the voltage detection chip U1 and the output terminal Vout, the negative electrode of the polarity capacitor C26 and the GND port of the voltage detection chip U1 are both grounded, the VOUT port of the voltage detection chip U1 is connected to the gate of the NMOS tube Q3, the drain of the NMOS tube Q3 is connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q3 and the source of the NMOS tube Q2 are both grounded.

[0016] In this embodiment, a Schottky diode D12 is connected in series between the input terminal Vin and the source of the PMOS transistor Q1.

[0017] In this embodiment, a filter capacitor C30 is connected in parallel between the two ends of the polarity capacitor C26.

[0018] In this embodiment, a transient diode D10 is connected in parallel between the VDD port and the GND port of the voltage detection chip U1.

[0019] In this embodiment, the model of the voltage detection chip U1 is BL8506-35CRM.

[0020] The principle of this embodiment is further described below:

[0021] The main function of the circuit of this embodiment is a storage management circuit. To ensure the stability of the wiring, the solar panel input line is welded to the input terminal Vin. When the voltage comes in, the gate voltage of the NMOS tube Q2 is very high, and the source voltage is zero, so at this time the NMOS tube Q2 is turned on first, thereby lowering the gate voltage of the PMOS tube Q1. At this time, the source voltage will be greater than the gate voltage, so that the PMOS tube Q1 will be turned on, and the voltage signal will flow from the top in sequence. The voltage will first pass through a Schottky diode D12, and then through a polar capacitor C26. This capacitor mainly stores energy for the voltage, and then a ceramic capacitor is connected in parallel to filter the signal, that is, the filter capacitor C30, so that part of the voltage enters the voltage detection chip U1, and a transient diode D10 is connected in parallel between the VDD port and the GND port of the voltage detection chip U1, so as to prevent surges through a TVS, and part of the voltage signal can be output to the output terminal Vout to power other modules. When this circuit is working, the voltage gradually increases. After a certain period of time, the VDD port of the voltage detection chip U1 is greater than the Vref of the module. At this time, the VOUT of the voltage detection chip U1 will output a high-level signal. The signal is transmitted to the NMOS tube Q3 through the wire, which will turn on the NMOS tube Q3, thereby lowering the gate voltage of the NMOS tube Q2, resulting in no voltage difference between the gate and source of the NMOS tube Q2, so that the NMOS tube Q2 will be turned off. After the NMOS tube Q2 is turned off, the gate voltage of the PMOS tube Q1 will be pulled up, and then the PMOS tube Q1 will be turned off. The subsequent polarity capacitor C26 stores a large amount of voltage, and the output voltage will slowly decrease at this time. When it drops to a voltage lower than the Vref voltage of the voltage detection chip U1, the Vout port of the voltage detection chip U1 will output a low level, causing the NMOS tube Q3 to turn off, and then the NMOS tube Q2 and the PMOS tube Q1 are turned on successively, thereby realizing the circuit shutdown cycle and overcurrent protection of the circuit.

[0022] The above-mentioned embodiments only express the specific implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the utility model. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model.

Claims

1. A low-power energy storage management circuit for a hardware temperature measuring device, comprising an input terminal Vin and an output terminal Vout, wherein a solar panel inlet line is welded to the input terminal Vin, and characterized in that: It also includes a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a polarity capacitor C26 and a voltage detection chip U1; the input terminal Vin is respectively connected to the source of the PMOS tube Q1, the drain of the NMOS tube Q2, and the drain of the NMOS tube Q3, the gate of the PMOS tube Q1 is connected to the drain of the NMOS tube Q2, the drain of the PMOS tube Q1 is respectively connected to the positive electrode of the polarity capacitor C26, the VDD port of the voltage detection chip U1 and the output terminal Vout, the negative electrode of the polarity capacitor C26 and the GND port of the voltage detection chip U1 are both grounded, the VOUT port of the voltage detection chip U1 is connected to the gate of the NMOS tube Q3, the drain of the NMOS tube Q3 is connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q3 and the source of the NMOS tube Q2 are both grounded.

2. The low power consumption energy storage management circuit for the hardware temperature measuring device according to claim 1, characterized in that: A Schottky diode D12 is connected in series between the input terminal Vin and the source of the PMOS tube Q1.

3. The low power consumption energy storage management circuit for the hardware temperature measuring device according to claim 1, characterized in that: The two ends of the polarity capacitor C26 are connected in parallel with a filter capacitor C30 .

4. The low power consumption energy storage management circuit for the hardware temperature measuring device according to claim 1, characterized in that: A transient diode D10 is connected in parallel between the VDD port and the GND port of the voltage detection chip U1.

5. The low power consumption energy storage management circuit for the hardware temperature measuring device according to claim 4, characterized in that: The model of the voltage detection chip U1 is BL8506-35CRM.

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