Three different digital interface output device based on IRIG-B code

Abstract

The utility model discloses an output device based on three different digital interfaces of an IRIG-B code, which relates to the technical field of IRIG-B and FPGA decoding control and comprises a decoding unit, an IRIG-B generator module, an FPGA decoding module, a power supply module, an RS232 output module, an RS485 output module and a TTL output module. Wherein the FPGA decoding module is respectively connected with the IRIG-B generator module, the decoding unit, the power supply module, the RS232 output module, the RS485 output module and the TTL output module, the IRIG-B code uses three different output interface types in the use process, time service is carried out on three different devices at the same time, the development difficulty of using the IRIG-B code by a user is effectively reduced, and the development efficiency of the IRIG-B code is improved. The IRIG-B code time service method has the advantages that the IRIG-B code time service module is optimized, the adaptability of the IRIG-B code decoding module is greatly improved, the problem that the IRIG-B code cannot be used due to the fact that the IRIG-B code is limited by interface types in the using process is solved, the using technical threshold of the IRIG-B code is lowered, and the IRIG-B time service technology can be used in simple systems such as a subsystem and a microsystem.

Description

Technical Field

[0001] The utility model relates to the technical field of IRIG-B and FPGA decoding control, in particular to a device for outputting three different digital interfaces based on IRIG-B codes. Background Art

[0002] IRIG-B (Inter Range Instrumentation Group) is an internationally accepted standard time code type and is widely used in time information transmission systems, especially in power systems.

[0003] With the development of the power system, more and more devices need IRIG-B timing, and the demand for IRIG-B code decoding is also very strong. However, the real-time requirements of IRIG-B code decoding are very high, and ordinary CPUs are difficult to perform this task. Even if they can be decoded, the time accuracy of the decoded code is very low, and the output interface is single and cannot be adapted to more devices. Therefore, there is an urgent need for a real-time decoding system based on FPGA and multiple output interfaces to meet the use of IRIG-B code timing in different occasions. In view of the above problems, the inventor proposes an output device based on three different digital interfaces of IRIG-B code to solve the above problems. Utility Model Content

[0004] In order to solve the problem that the IRIG-B code decoding module has a single output interface and cannot satisfy the direct interconnection under various hardware interfaces; the purpose of the utility model is to provide an output device with three different digital interfaces based on IRIG-B code.

[0005] To solve the above technical problems, the utility model adopts the following technical solutions: a system of three different digital interface output devices based on IRIG-B code, including a decoding unit, an IRIG-B generator module, an FPGA decoding module, a power module, an RS232 output module, an RS485 output module, and a TTL output module; wherein the FPGA decoding module is respectively connected to the IRIG-B generator module, the decoding unit, the power module, the RS232 output module, the RS485 output module, and the TTL output module. The IRIG-B code uses three different output interface types during use, and provides time for three different devices at the same time, which effectively reduces the development difficulty of users using the IRIG-B code, and also greatly improves the adaptability of the IRIG-B code decoding module, solves the problem that the IRIG-B code cannot be used due to the limitation of the interface type during use, reduces the technical threshold for the use of the IRIG-B code, and can use the IRIG-B timing technology in simple systems such as subsystems and microsystems.

[0006] Preferably, the processor chip model in the IRIG-B generator module is GD32F407 of GigaDevice, the decoding unit uses the decoding function of the IRIG-B code implemented by the Verilog HDL language, the FPGA chip model in the FPGA decoding module is Anlu EF2L45LG144, and the power chip model in the power module is Shanghai Belling BL8033, including input and output filter capacitors and rectifier inductors and feedback resistors; wherein, the VIN of the power chip is connected to one end of the input capacitor, the VOUT of the chip in the power module is connected to one end of the output capacitor to form a filter circuit, and the SW of the power supply is connected to one end of the rectifier inductor to form a rectifier circuit. The chip model in the RS232 output module is the SIT3232E level conversion chip of Xinlite, and the chip model in the RS485 output module is the SIT65HVD75DR of Xinlite. The FPGA chip EF2L45LG144 also needs to provide an active oscillator 25MHz and an IO power supply 3.3V.

[0007] Preferably, the power module includes a resistor, a capacitor, an inductor and a power chip, wherein the VIN of the power chip is connected to one end of the input capacitor, the VOUT of the power chip is connected to one end of the output capacitor to form a filter circuit, and the SW of the power chip is connected to one end of the inductor to form a rectifier circuit, thereby forming a complete DC-DC step-down circuit.

[0008] Compared with the prior art, the beneficial effects of the utility model are:

[0009] In the utility model, not only the decoding function of the IRIG-B code is realized through the FPGA decoding module, but also three different output interfaces are expanded, so that time can be provided to three different devices at the same time, which effectively reduces the development difficulty of users using the IRIG-B code, and also greatly improves the adaptability of the IRIG-B code decoding module. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 This is a schematic diagram of the system structure of three different digital interface output devices based on IRIG-B code according to an embodiment of the utility model;

[0012] Figure 2This is a schematic diagram of the power supply circuit structure of a device with three different digital interface outputs based on IRIG-B code according to an embodiment of the utility model;

[0013] Figure 3 The present invention is a schematic diagram of the principle structure of three different digital interface output devices based on IRIG-B code according to an embodiment of the present invention.

[0014] In the figure: 1. Decoding unit; 2. IRIG-B generator module; 3. FPGA decoding module; 4. Power supply module; 5. RS232 output module; 6. RS485 output module; 7. TTL output module. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0016] Example: Figure 1-3 As shown, the utility model provides three different digital interface output devices based on IRIG-B code, including a decoding unit 1, an IRIG-B generator module 2, an FPGA decoding module 3, a power supply module 4, an RS232 output module 5, an RS485 output module 6, and a TTL output module 7;

[0017] The FPGA decoding module 3 is respectively connected to the IRIG-B generator module 2, the decoding unit 1, the power module 4, the RS232 output module 5, the RS485 output module 6 and the TTL output module 7; the power module 4 is connected to the IRIG-B generator module 2 and the FPGA decoding module 3.

[0018] FPGA decoding module 3 is mainly composed of EF2L45LG144 from Anlu, active crystal oscillator and power supply, which realizes the decoding function of IRIG-B;

[0019] RS232 output module 5 is mainly composed of SIT3232E level conversion chip and peripheral circuits to realize the physical level conversion from TTL interface to RS232 interface;

[0020] RS485 output module 6 is mainly composed of SIT65HVD75DR single-ended to differential conversion chip and peripheral circuits to realize the physical level conversion from TTL interface to RS485 interface;

[0021] Since there are many types of devices using IRIG-B codes, the current commonly used decoding modules cannot meet the output of various types of interfaces. Therefore, the utility model adopts three different data interface outputs to realize the interconnection between modules and different types of designs, making the IRIG-B code more widely used.

[0022] In addition, the utility model can also support the simultaneous output function of three different interfaces, and can provide time for three different devices at the same time.

[0023] The processor chip model in the IRIG-B generator module 2 is GigaDevice's GD32F407, the decoding unit 1 uses Verilog HDL language to implement the IRIG-B code decoding function, the power chip model in the power module 4 is Shanghai Belling BL8033, including input and output filter capacitors and rectifier inductors and feedback resistors; wherein, the VIN of the chip in the power module is connected to one end of the input capacitor, the VOUT of the power chip is connected to one end of the output capacitor to form a filter circuit, the SW of the power supply is connected to one end of the rectifier inductor to form a rectifier circuit, the chip model in the RS232 output module 5 is the SIT3232E level conversion chip of Xinlite, and the chip model in the RS485 output module 6 is the SIT65HVD75DR of Xinlite.

[0024] The power module 4 includes a resistor, a capacitor, an inductor and a power chip, wherein the VIN of the power chip is connected to one end of the input capacitor, the VOUT of the power chip is connected to one end of the output capacitor, and the SW of the power chip is connected to one end of the inductor to form a rectifier circuit, thereby forming a complete DC-DC buck circuit.

[0025] The FPGA chip model in the FPGA decoding module 3 is Anlu EF2L45LG144. The FPGA chip EF2L45LG144 also needs to provide an active oscillator 25MHz and an IO power supply 3.3V.

[0026] Working principle: IRIG-B code uses three different types of output interfaces during use, and provides time for three different devices at the same time, which effectively reduces the development difficulty of users using IRIG-B code. At the same time, it also greatly improves the adaptability of IRIG-B code decoding module, solves the problem that IRIG-B code cannot be used due to the limitation of interface type during use, reduces the technical threshold for using IRIG-B code, and can use IRIG-B timing technology in simple systems such as subsystems and microsystems.

[0027] Finally, it should be noted that the above are only preferred examples of the utility model and are not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A device for outputting three different digital interfaces based on IRIG-B code, comprising a decoding unit (1), an IRIG-B generator module (2), an FPGA decoding module (3), a power supply module (4), an RS232 output module (5), an RS485 output module (6), and a TTL output module (7), characterized in that: The FPGA decoding module (3) is respectively connected to the decoding unit (1), the IRIG-B generator module (2), the power supply module (4), the RS232 output module (5), the RS485 output module (6) and the TTL output module (7).

2. The device for outputting three different digital interfaces based on IRIG-B code as claimed in claim 1, characterized in that: The decoding unit (1) uses Verilog HDL language to implement the decoding function of the IRIG-B code.

3. The device for outputting three different digital interfaces based on IRIG-B code as claimed in claim 1, characterized in that: The FPGA decoding module (3) is provided with an FPGA chip EF2L45LG144.

4. The device for outputting three different digital interfaces based on IRIG-B code as claimed in claim 1, characterized in that: The power module (4) comprises an input and output filter capacitor, a rectifier inductor and a feedback resistor; the VIN of the chip in the power module (4) is connected to one end of the input capacitor; the VOUT of the chip in the power module (4) is connected to one end of the output capacitor to form a filter circuit; and the SW of the power supply is connected to one end of the rectifier inductor to form a rectifier circuit.

5. The device for outputting three different digital interfaces based on IRIG-B code as claimed in claim 3, characterized in that: The FPGA chip EF2L45LG144 also needs to provide an active oscillator 25MHz and an IO power supply 3.3V.

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