Silicon carbide MOSFET device capable of improving through-current capability

Abstract

The utility model relates to a silicon carbide MOSFET device with improved through-current capability. Relates to the technical field of semiconductors. Comprising a silicon carbide substrate; the silicon carbide drift layer is arranged on the silicon carbide substrate, and the top of the silicon carbide drift layer is sequentially provided with an N + region and a JFET region from bottom to top; the PW region is located in the JFET region, extends downwards from the top surface of the silicon carbide drift layer and is connected with the N + region; the NP region is located in the PW region and extends downwards from the top surface of the PW region, and a distance is formed between the NP region and the N + region; the PP region extends downwards from the top surface of the PW region and is positioned in the middle of the NP region, and a distance is formed between the PP region and the N + region; the gate oxide layer is positioned on the top surface of the JFET region; the ohmic metal layer is located in the gate oxide layer, and the bottom of the ohmic metal layer is connected with the NP region and the PP region; the Poly layer is located on the top surface of the gate oxide layer; according to the utility model, the resistance of the device is reduced, the through-current capability is improved, and the possibility of bipolar degradation of the device is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a silicon carbide MOSFET device with improved current-carrying capacity. Background Art

[0002] Compared with silicon, silicon carbide has more advantages in bandgap width, critical breakdown field strength and thermal conductivity. This means that Si-based IGBT devices originally used in high-voltage and high-power fields can be replaced by silicon carbide MOSFET devices. While meeting stringent application requirements, MOSFET, a unipolar device, has better switching characteristics, which also reduces the loss, cost, size and weight of the application system. Especially now with the rapid development of new energy vehicles, clean energy and other fields, silicon carbide MOSFET devices have become their first choice.

[0003] Due to the body diode carried by the silicon carbide MOSFET device, it is not necessary to connect an additional freewheeling diode in parallel to achieve protection during use, thus reducing the amount of devices used. In addition, the P region of the silicon carbide MOSFET body diode and the N region that forms the channel are short-circuited in theory due to the ohmic contact, thereby improving the reverse withstand voltage capability of the device. However, the body diode has advantages as well as disadvantages. Since the silicon carbide epitaxial layer has material lattice defects such as BPD, during the freewheeling process of the silicon carbide MOSFET, the holes in the P region of the body diode will easily enter the epitaxial layer, which will easily cause the electrons and holes in the epitaxial layer to recombine, causing the material lattice defects to spread further, resulting in bipolar degradation, and the appearance of a larger defect area, causing the performance degradation of the device. Utility Model Content

[0004] In view of the above problems, the utility model provides a silicon carbide MOSFET device with improved current carrying capacity, which improves the current carrying capacity of the device and reduces the risk of bipolar degradation of the device during the freewheeling process.

[0005] The technical solution of the utility model is:

[0006] Silicon carbide MOSFET devices with improved current capability, including:

[0007] Silicon carbide substrate;

[0008] A silicon carbide drift layer is arranged on the silicon carbide substrate, and an N+ region and a JFET region are arranged in sequence from bottom to top on the top of the silicon carbide drift layer;

[0009] A PW region, located in the JFET region, extending downward from the top surface of the silicon carbide drift layer and connected to the N+ region;

[0010] An NP region, located in the PW region, extending downward from the top surface of the PW region, and having a spacing from the N+ region;

[0011] A PP region, extending downward from the top surface of the PW region, located in the middle of the NP region, and spaced apart from the N+ region;

[0012] A gate oxide layer, located on a top surface of the JFET region;

[0013] An ohmic metal layer, located in the gate oxide layer, and connected to the NP region and the PP region at the bottom;

[0014] A Poly layer, located on the top surface of the gate oxide layer;

[0015] An isolation dielectric layer, disposed on the top surface of the Poly layer, extending downward from the side, and connected to the NP region;

[0016] The front electrode metal covers the top surface of the isolation dielectric layer and the ohmic metal layer.

[0017] Specifically, the conductivity type of the silicon carbide substrate and the silicon carbide drift layer are both N-type.

[0018] Specifically, the concentration range of the N+ region is 8E16-5E17cm -2 .

[0019] Specifically, the concentration range of the silicon carbide drift layer is 8E15-2E16cm -2 .

[0020] Specifically, the concentration range of the PW region is 1E17-1E18cm -2 .

[0021] Specifically, the concentration range of the JFET region is 5E16-1E17cm -2 .

[0022] Specifically, the width of the N+ region is 5%-8% of the width of the silicon carbide drift layer.

[0023] Beneficial effects of the utility model:

[0024] 1. Reduce device resistance and improve device current capacity:

[0025] In the resistance distribution of silicon carbide devices, the drift layer resistance accounts for a large proportion, which greatly affects the current flow capacity of the device. The utility model structure forms a layer of N+ region with a higher concentration by ion implantation in the chip source area, which reduces the resistance of the silicon carbide drift layer, reduces the resistance of the entire chip, and improves the current flow capacity. According to simulation verification, this structure can improve the current flow capacity by 10%-14% compared with conventional planar gate silicon carbide MOSFET devices.

[0026] 2. Reduce the risk of bipolar degradation of devices:

[0027] Due to the body diode carried by the silicon carbide MOSFET, the P-region holes of the body diode will enter the drift layer during the freewheeling process, causing the P-region holes and the drift layer electrons to recombine with each other, resulting in the spread of lattice defects in the drift layer, resulting in the degradation of device performance, the most obvious of which is the increase in on-resistance and the decrease in current carrying capacity. The N+ region formed by the structure of the utility model is located below the P region and has a high concentration, so it can better cut off the P-region holes during the freewheeling process, preventing them from entering the drift layer, and reducing the possibility of bipolar degradation of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0029] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0030] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0031] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0032] Figure 5 It is a schematic diagram of the structure of step S500 of the utility model;

[0033] Figure 6 It is a structural schematic diagram of step S600 of the utility model;

[0034] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0035] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0036] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0037] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0038] Fig.11 It is a structural schematic diagram of step S1100 of the utility model;

[0039] In the figure, 1 is the silicon carbide substrate, 2 is the silicon carbide drift layer, 3 is the N+ region, 4 is the PW region, 5 is the NP region, 6 is the PP region, 7 is the JFET region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic metal layer, and 12 is the front source metal. DETAILED DESCRIPTION

[0040] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0041] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] A method for preparing a silicon carbide MOSFET device with improved current flow capacity comprises the following steps:

[0044] S100, refer to Figure 1 As shown, a silicon carbide drift layer 2 is formed by epitaxial growth on a silicon carbide substrate 1;

[0045] S200, refer to Figure 2 As shown, an N+ region 3 is formed in the source region on the silicon carbide drift layer 2 by depositing a mask layer, yellow light, pattern etching, and ion implantation;

[0046] In view of the fact that the role of the N+ region 3 in step S200 is to reduce the device resistance and bipolar degradation effect, the concentration of the N+ region 3 is greater than the concentration of the silicon carbide drift layer 2. At the same time, in order to prevent the space charge region from expanding in the PW region 4 during the reverse blocking process of the device, the concentration is also less than the concentration of the PW region 4. The concentration range of the N+ region in this patent is 8E16-5E17cm -2.

[0047] In view of the fact that the reverse withstand voltage of the device during the cut-off process is mainly borne by the silicon carbide drift layer 2, the width of the N+ region 3 in step S200 should not be too wide, as too wide a width will reduce the device's ability to withstand reverse withstand voltage. Therefore, the width of the N+ region 3 is 5%-8% of the width of the silicon carbide drift layer 2, and the width of the silicon carbide drift layer 2 adopts the conventional specifications in the industry.

[0048] S300, refer to Figure 3 As shown, a PW region 4 is formed on the silicon carbide drift layer 2 by depositing a mask layer, yellow light, pattern etching, and ion implantation;

[0049] S400, refer to Figure 4 As shown, a spacer layer is formed in the PW region 4 by depositing a mask layer, yellow light, and pattern etching, and an NP region 5 is formed by ion implantation;

[0050] S500, refer to Figure 5 As shown, a PP region 6 is formed in the PW region 4 by depositing a mask layer, yellow light, pattern etching, and ion implantation;

[0051] S600, refer to Figure 6 As shown, a JFET region 7 is formed on the silicon carbide drift layer 2 by depositing a mask layer, yellow light, pattern etching, and ion implantation;

[0052] S700, reference Figure 7 As shown, a gate oxide layer 8 is formed on the top surface of the silicon carbide drift layer 2 by dry oxygen growth;

[0053] S800, reference Figure 8 As shown, a Poly layer 9 is formed by depositing polysilicon on the gate oxide layer 8, which is led out as a gate electrode;

[0054] S900, refer to Fig. 9 As shown, an isolation dielectric layer 10 in contact with the Poly layer 9 and the NP region 5 is formed by deposition on the Poly layer 9 to isolate the gate and the source to avoid short circuits at the two locations;

[0055] S1000, refer to Fig.10 As shown, an ohmic metal layer 11 in contact with the NP region 5 and the PP region 6 is formed on the silicon carbide drift layer 2 by sputtering, and then alloyed by annealing to form an ohmic contact;

[0056] S1100, reference Fig.11 As shown, a front electrode metal 12 is formed on the isolation dielectric layer 10 and the ohmic metal layer 11 by sputtering to be led out as a source electrode.

[0057] Silicon carbide MOSFET devices with improved current capability, including:

[0058] Silicon carbide substrate 1;

[0059] The silicon carbide drift layer 2 is arranged on the silicon carbide substrate 1, and the top of the silicon carbide drift layer 2 is provided with an N+ region 3 and a JFET region 7 arranged in sequence from bottom to top; the conductivity type of the silicon carbide substrate 1 and the silicon carbide drift layer 2 are both N-type.

[0060] The concentration of SiC drift layer 2 is in the range of 8E15-2E16cm -2 The concentration of JFET region 7 is in the range of 5E16-1E17cm -2 .

[0061] The concentration range of N+ region 3 is 8E16-5E17cm -2 .

[0062] The PW region 4 is located in the JFET region 7, extends downward from the top surface of the silicon carbide drift layer 2, and is connected to the N+ region 3; the concentration range of the PW region 4 is 1E17-1E18cm -2 .

[0063] NP region 5, located in the PW region 4, extending downward from the top surface of the PW region 4, and having a spacing from the N+ region 3;

[0064] A PP region 6 extending downward from the top surface of the PW region 4 and located in the middle of the NP region 5;

[0065] A gate oxide layer 8, located on the top surface of the JFET region 7;

[0066] An ohmic metal layer 11 is located in the gate oxide layer 8, and its bottom is connected to the NP region 5 and the PP region 6;

[0067] A Poly layer 9, located on the top surface of the gate oxide layer 8;

[0068] An isolation dielectric layer 10 is disposed on the top surface of the Poly layer 9 and extends downward from the side to be connected to the NP region 5;

[0069] The front electrode metal 12 covers the top surfaces of the isolation dielectric layer 10 and the ohmic metal layer 11 .

[0070] The utility model reduces the resistance of the silicon carbide drift layer of the device and improves the current-carrying capacity of the device by forming an N+ region in the drift layer of the silicon carbide MOSFET. In addition, this N+ region also effectively prevents the P-region holes from entering the silicon carbide drift layer during the continuous current process of the device, so that the P-region holes are cut off in this N+ region, reducing the risk of bipolar degradation.

[0071] Regarding the contents disclosed in this case, there are a few points that need to be explained:

[0072] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0073] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;

[0074] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A silicon carbide MOSFET device with improved current carrying capacity, characterized in that: include: Silicon carbide substrate (1); A silicon carbide drift layer (2) is arranged on the silicon carbide substrate (1), and an N+ region (3) and a JFET region (7) are arranged in sequence from bottom to top on the top of the silicon carbide drift layer (2); A PW region (4) is located in the JFET region (7), extends downward from the top surface of the silicon carbide drift layer (2), and is connected to the N+ region (3); An NP region (5) is located in the PW region (4), extends downward from the top surface of the PW region (4), and is spaced apart from the N+ region (3); A PP region (6), extending downward from the top surface of the PW region (4), located in the middle of the NP region (5), and spaced apart from the N+ region (3); A gate oxide layer (8), located on the top surface of the JFET region (7); An ohmic metal layer (11), located in the gate oxide layer (8), and having a bottom connected to the NP region (5) and the PP region (6); A Poly layer (9), located on the top surface of the gate oxide layer (8); An isolation dielectric layer (10) is disposed on the top surface of the Poly layer (9), extends downward from the side, and is connected to the NP region (5); The front electrode metal (12) covers the top surfaces of the isolation dielectric layer (10) and the ohmic metal layer (11).

2. The silicon carbide MOSFET device with improved current carrying capacity according to claim 1, characterized in that: The silicon carbide substrate (1) and the silicon carbide drift layer (2) are both of N-type conductivity type.

3. The silicon carbide MOSFET device with improved current carrying capacity according to claim 1, characterized in that: The concentration range of the N+ region (3) is 8E16-5E17cm -2 .

4. The silicon carbide MOSFET device with improved current carrying capacity according to claim 1, characterized in that: The concentration range of the silicon carbide drift layer (2) is 8E15-2E16cm -2 .

5. The silicon carbide MOSFET device with improved current carrying capacity according to claim 1, characterized in that: The concentration range of the PW region (4) is 1E17-1E18 cm -2 .

6. The silicon carbide MOSFET device with improved current carrying capacity according to claim 1, characterized in that: The concentration of the JFET region (7) is in the range of 5E16-1E17cm -2 .

7. The silicon carbide MOSFET device with improved current carrying capacity according to claim 1, characterized in that: The width of the N+ region (3) is 5%-8% of the width of the silicon carbide drift layer (2).

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