Motor precision compensation device
By designing a motor accuracy compensation device independent of the driver, and using components such as FPGA chips to achieve motor accuracy compensation, the problem of insufficient flexibility in the driver compensation scheme in the prior art is solved, and the motor control accuracy and flexibility in driver selection are improved.
Patent Information
- Application Number
- CN202420971285.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-07
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-07
AI Technical Summary
Existing motor accuracy compensation schemes are usually carried out inside the driver, resulting in limited flexibility in driver selection, inconsistent compensation data, and recompensation is required when replacing the driver or motor, which is insufficient flexibility.
A motor accuracy compensation device independent of the driver is designed, including FPGA chip, power management module, signal processing module and clock module. It is connected to the encoder through the input port and the output port is connected to the driver to realize motor accuracy compensation and compensate data storage. On the motor side.
Improves the flexibility of driver selection, ensures the consistency of driver parameters, avoids the need for recompensation when replacing drivers or motors, and enhances motor control accuracy.
Smart Images
Figure CN222283105U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of motors, and in particular relates to a motor precision compensation device. Background Art
[0002] The movement of machinery in the field of automation requires the cooperation of the control unit (PLC or industrial computer), the drive unit (driver) and the motor unit (DD motor or linear motor). The control unit issues instructions, and the drive unit generates precise control to make the motor run at the specified speed and stroke. Due to physical factors such as deviations in mechanical structure or differences in the installation process, the accuracy of DD motors or linear motors will be affected. Therefore, in many fields that require high precision, some solutions are needed to compensate for this mechanical physical deviation.
[0003] The existing accuracy compensation solution is performed inside the driver. The advantage of this is that no new hardware needs to be added, but it also has the following disadvantages:
[0004] 1. Many drive manufacturers have not developed compensation functions. Even if they have developed this function, it can only be applied to certain specific drives. This will cause great limitations in drive selection. In addition, drives from different manufacturers have different compensation methods, which requires debugging personnel to be familiar with the compensation methods of multiple drives.
[0005] 2. Since the data that needs to be compensated for each motor is different, it is necessary to import different compensation parameters into each driver.
[0006] 3. After compensation, the driver and motor are bound together. If the driver or motor needs to be replaced later, re-compensation is required, which reduces flexibility.
[0007] Therefore, in view of the above technical problems, it is necessary to provide a motor precision compensation device. Utility Model Content
[0008] The utility model aims to provide a motor precision compensation device, which can meet the motor precision compensation requirements independent of a driver.
[0009] In order to achieve the above-mentioned object, a specific embodiment of the utility model provides a motor precision compensation device, the device comprises a housing, a circuit board installed in the housing, and an input port and an output port connected to the circuit board, the input port and the output port are fixedly installed with the housing, the input port is used to connect to an encoder on the motor, the output port is used to connect to a driver connected to the motor, and a motor precision compensation circuit connected to the input port and the output port is arranged on the circuit board;
[0010] The motor precision compensation circuit includes a connected FPGA chip and a power management module, and a configuration module, a signal processing module and a clock module connected to the FPGA chip and the power management module. The FPGA chip is connected to the input port, the signal processing module is connected to the output port, the clock module is used to generate a clock signal and transmit the clock signal to the FPGA chip, and the power management module is used to provide working voltage to the FPGA chip, the configuration module, the signal processing module and the clock module.
[0011] In one or more embodiments of the present invention, the motor precision compensation circuit further includes a filter circuit connected to the power management module, and the filter circuit is used to filter the working voltage.
[0012] In one or more embodiments of the present invention, the filtering circuit includes a plurality of capacitor groups, each of the capacitor groups is connected to a corresponding working voltage and a ground voltage, and each of the capacitor groups includes a plurality of capacitors connected in parallel.
[0013] In one or more embodiments of the present invention, the motor precision compensation circuit further includes a current limiting circuit, and the current limiting circuit is connected to the input port and the FPGA chip for current limiting.
[0014] In one or more embodiments of the present invention, the current limiting circuit includes a plurality of resistors connected to the input port and the FPGA chip.
[0015] In one or more embodiments of the present utility model, the power management module includes an input filter circuit and multiple linear regulators, the input filter circuit is connected to the power supply voltage to filter the power supply voltage, the linear regulator is connected to the power supply voltage and one or more of the FPGA chip, configuration module, signal processing module and clock module, and the linear regulator is used to convert the power supply voltage into an operating voltage.
[0016] In one or more embodiments of the present utility model, the input filter circuit includes a first capacitor, a second capacitor, a first resistor and a light-emitting diode, the first capacitor and the second capacitor are connected in parallel between a power supply voltage and a ground voltage, the first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is connected to the anode of the light-emitting diode, and the cathode of the light-emitting diode is connected to the ground voltage.
[0017] In one or more embodiments of the present utility model, the clock module includes a connected crystal oscillator and a reset circuit, the reset circuit is used to reset the FPGA chip, the crystal oscillator is connected to the FPGA chip, and the crystal oscillator is used to generate a clock signal and transmit the clock signal to the FPGA chip.
[0018] In one or more embodiments of the present utility model, the reset circuit includes a second resistor, a ninth capacitor and a button, the first end of the second resistor is connected to the working voltage, the second end of the second resistor is connected to the first end of the button, the first end of the ninth capacitor is connected to the first end of the button, the second end of the ninth capacitor is connected to the second end of the button and the ground voltage, and the third and fourth ends of the button are connected to the crystal oscillator.
[0019] In one or more embodiments of the present utility model, the configuration module includes a configuration chip and a configuration interface, both of which are connected to the FPGA chip, the configuration interface is used to receive external configuration information and transmit the configuration information to the FPGA chip, and the configuration chip is used to obtain and store the configuration information through the FPGA chip.
[0020] Compared with the prior art, the motor precision compensation device of the utility model has a simple structure and a small size. It can be directly connected to the motor and the driver. When the internal space of the motor is sufficient, it can be directly designed and placed inside the motor. When the internal space of the motor is insufficient, it can be regarded as integrated with the motor through an external connection, so that the compensation data is no longer stored in the driver, but stored at the motor end. This has the following advantages:
[0021] 1. Make the precision compensation no longer dependent on the driver, and make the driver selection more flexible.
[0022] 2. There is no motor accuracy compensation data inside the driver, so that a set of parameters can be used for multiple drivers, ensuring the consistency of the driver parameters.
[0023] 3. If the driver or motor needs to be replaced later, there is no need to re-compensate, which is convenient for after-sales work.
[0024] 4. When the motor is shipped, you can choose not to do precision compensation (not equipped with this device) or do precision compensation (equipped with this device and the data is written at the factory). The overall selection is based on actual needs, with a higher degree of freedom. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the utility model, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0026] Figure 1 It is a structural diagram of a motor precision compensation device in one embodiment of the utility model.
[0027] Figure 2The schematic diagram of the motor precision compensation circuit in one embodiment of the utility model is shown in FIG.
[0028] Figure 3 It is a structural diagram of the input port and the output port in one embodiment of the utility model.
[0029] Figure 4a and 4b This is a circuit schematic diagram of an FPGA chip in one embodiment of the utility model.
[0030] Figure 5 1 is a circuit schematic diagram of a current limiting circuit in one embodiment of the utility model.
[0031] Figure 6 1 is a circuit diagram of a power management module in one embodiment of the utility model.
[0032] Figure 7 The figure is a circuit diagram of a filter circuit in one embodiment of the utility model.
[0033] Figure 8 The figure is a circuit diagram of a clock module in one embodiment of the present utility model.
[0034] Fig. 9 The figure is a circuit diagram of a signal processing module in one embodiment of the utility model.
[0035] Fig.10 The figure is a circuit diagram of a data configuration module in one embodiment of the utility model. DETAILED DESCRIPTION
[0036] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0037] The words "coupled" or "connected" or "connected" in the specification include both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the present utility model, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.
[0038] like Figure 1 As shown, a motor precision compensation device in an embodiment of the utility model, wherein a plurality of encoders are arranged on the motor, and these encoders are used to generate encoder signals indicating the position or motion state of the motor, and the motor is also connected to a driver. The motor precision compensation device comprises a housing 13, a circuit board (not shown) installed in the housing, and an input port 11 and an output port 12 connected to the circuit board, and the input port 11 and the output port 12 are fixedly installed with the housing 13. The input port 11 is used to connect to the encoder on the motor, and the output port 12 is used to connect to the driver. A motor precision compensation circuit connected to the input port 11 and the output port 12 is arranged on the circuit board.
[0039] like Figure 2 As shown, the motor precision compensation circuit includes a connected FPGA chip 20 and a power management module 30, as well as a configuration module 60, a signal processing module 50 and a clock module 40 connected to the FPGA chip 20 and the power management module 30, as well as a current limiting circuit 21 connected to the FPGA chip 20 and the input port 11 and a filtering circuit 31 connected to the power management module 30.
[0040] The current limiting circuit 21 is used to reduce the current of the encoder signal received by the FPGA chip 20, and the FPGA chip 20 is used to generate a compensation signal based on multiple encoder signals. In actual application scenarios, the processing of the encoder signal can be programmed based on the Verilog HDL hardware description language and implemented on the FPGA chip 20.
[0041] The signal processing module 50 is used to perform differential processing on the compensation signal and generate a differential compensation signal. The signal processing module 50 is connected to the output port 12 to transmit the differential compensation signal to the driver. After receiving the compensation signal, the driver can perform compensation control on the motor to improve the control accuracy of the motor. The clock module 40 is used to generate a clock signal and transmit the clock signal to the FPGA chip 20. The configuration module 60 is used to configure the program settings of the FPGA chip 20. The power management module 30 is used to provide multiple operating voltages to the FPGA chip 20, the configuration module 60, the signal processing module 50 and the clock module 40, and the filter circuit 31 is used to filter the multiple operating voltages.
[0042] The motor precision compensation device is small in size and low in cost. It can be directly installed inside the motor if there is enough space inside the motor. If there is not enough space inside the motor, it can be regarded as an integral part of the motor through external connection. It is flexible and convenient to use. And the compensation data is no longer stored in the driver, but stored at the motor end. In this way, the motor precision compensation is no longer dependent on the driver, and the driver selection is more flexible. There is no need to set the relevant data of the motor precision compensation inside the driver, so that a set of parameters can be used for multiple drivers, ensuring the consistency of the driver parameters. If the driver or motor needs to be replaced later, there is no need to re-compensate.
[0043] Specifically, Figure 3 As shown, both input port 11 and output port 12 are DB15 interfaces for serial communication (RS-232 protocol). Pins 4, 5, 6, 12, 13, and 14 of input port 11 are used to transmit encoder signals IN_Z-, IN_B-, IN_A-, IN_Z+, IN_B+, and IN_A+, respectively. Pins 4, 5, 6, 12, 13, and 14 of output port 12 are used to receive differential compensation signals OUT_Z-,
[0044] like Figure 4a , 4b As shown, the FPGA chip 20 receives the encoder signal through pins 38, 39, 52-55, processes it and forms a compensation signal, and then sends it out through pins 98, 100, and 101. The motor precision compensation circuit also includes a light-emitting unit, which is connected to the FPGA chip 20. By writing a relevant program for the FPGA chip 20, the FPGA chip 20 can control the light-emitting diodes D2 and D3 in the light-emitting unit to emit light as working status indicators. The anodes of the light-emitting diodes D2 and D3 are respectively connected to the pins 141 and 142 of the FPGA chip 20.
[0045] like Figure 4a , 4b and Figure 5As shown, in one embodiment, the current limiting circuit includes a plurality of resistors R6, R7, R8 to R11. The first end of the resistor R6 is connected to the pin 12 of the input port 11, the first end of the resistor R7 is connected to the pin 4 of the input port 11, the first end of the resistor R8 is connected to the pin 14 of the input port 11, the first end of the resistor R9 is connected to the pin 6 of the input port 11, the first end of the resistor R10 is connected to the pin 13 of the input port 11, and the first end of the resistor R11 is connected to the pin 5 of the input port 11.
[0046] The second end of resistor R6 is connected to pin 38 of FPGA chip 20, the second end of resistor R7 is connected to pin 39 of FPGA chip 20, the second end of resistor R8 is connected to pin 54 of FPGA chip 20, the second end of resistor R9 is connected to pin 55 of FPGA chip 20, the second end of resistor R10 is connected to pin 52 of FPGA chip 20, and the second end of resistor R11 is connected to pin 53 of FPGA chip 20.
[0047] These resistors R6, R7, R8-R11 are respectively connected between pins 38, 39, 52-55 for receiving encoder signals on the FPGA chip 20 and pins 4, 5, 6, 12, 13, 14 for outputting encoder signals in the input port 11. By limiting the current and dividing the voltage of the encoder signal, the current of the encoder signal received by the FPGA chip 20 is reduced to prevent the encoder signal from being directly input into the FPGA chip and burning the pins. In some specific scenarios, when the encoder signal contains a zero mark signal, the resistor R4 can be directly connected to the pin 12 of the input port 11 for inputting the zero mark signal and the pin 12 of the output port 12 for outputting the zero mark signal, and the resistor R4 can be directly connected to the pin 12 of the input port 11 for inputting the zero mark signal and the pin 4 of the output port 12 for outputting the zero mark signal.
[0048] like Figure 6 As shown, the power management module 30 includes three linear regulators U4, U5, U6 and an input filter circuit. The three linear regulators U4, U5, U6 are connected to the 5V voltage output pin on the input port 11, converting the 5V voltage into operating voltages of 1.2V, 2.5V and 3.3V respectively, and are connected to the FPGA chip 20, the configuration module 60, the signal processing module 50 and the clock module 40 that require corresponding operating voltages.
[0049] The input filter circuit includes a first capacitor C1, a second capacitor C2, a first resistor R1 and a light-emitting diode D1. The first capacitor C1 and the second capacitor C2 are connected in parallel between a 5V power supply voltage output pin on the input port 11 and a ground voltage. A first end of the first resistor R1 is connected to the 5V power supply voltage output pin on the input port 11 to receive a 5V power supply voltage. A second end of the first resistor R1 is connected to an anode of the light-emitting diode D1. A cathode of the light-emitting diode D1 is connected to the ground voltage. The light-emitting diode D1 is used as a power indicator light.
[0050] like Figure 7 As shown, in one embodiment, the filter circuit 31 includes multiple groups of capacitor groups, each group of capacitor groups is connected to the corresponding working voltage and ground voltage, and each group of capacitor groups includes multiple parallel capacitors. One group of capacitor groups is composed of capacitors C20 and C21 connected in parallel, and the group of capacitor groups is connected between the 2.5V working voltage and the ground voltage generated by the linear regulator U5. One group of capacitor groups is composed of capacitors C16, C17, C18, and C19 connected in parallel, and the group of capacitor groups is connected between the 3.3V working voltage and the ground voltage generated by the linear regulator U4. One group of capacitor groups is composed of capacitors C12, C13, C14, and C15 connected in parallel, and the group of capacitor groups is connected between the 1.2V working voltage and the ground voltage generated by the linear regulator U6. The filter circuit also includes an RC filter circuit composed of a resistor R20 and a capacitor C22, one end of the RC filter circuit is connected to the same ground voltage as each group of capacitor groups, and the other end of the RC filter circuit is connected to another ground voltage to filter the working voltage. The filter circuit 31 filters the operating voltage, especially filters out the power supply noise on the FPGA chip 20, thereby ensuring the stability and reliability of the circuit.
[0051] like Figure 8 As shown, the clock module 40 includes a connected crystal oscillator U7 and a reset circuit. Pin 3 of the crystal oscillator U7 is connected to pin 91 of the FPGA chip 20 through a resistor R3, a capacitor C10 is connected between pin 2 and pin 4 of the crystal oscillator U7, and pin 4 of the crystal oscillator U7 is simultaneously connected to a 3.3V operating voltage. The crystal oscillator U7 is used to generate a clock signal and transmit the clock signal to the FPGA chip 20. The reset circuit is used to reset the FPGA chip 20, and the reset circuit includes a second resistor R2, a ninth capacitor C9, and a button K. The first end of the second resistor R2 is connected to the 3.3V operating voltage, the second end of the second resistor R2 is connected to the first end of the button K, the first end of the ninth capacitor C9 is connected to pin 1 of the button K and pin 90 of the FPGA chip 20, the second end of the ninth capacitor C9 is connected to pin 2 of the button K and the ground voltage, and the first end of the ninth capacitor C9 is short-circuited with the ground voltage by pressing the button K to reset the FPGA chip 20.
[0052] like Fig. 9As shown, the model of the signal processing module 50 is ISL32172. Based on the serial communication protocol adopted by the output port 12, a differential signal is required for data transmission. The ISL32172 can generate such a differential signal, that is, the compensation signal generated by the FPGA chip 20 is differentiated and a differential compensation signal is generated, and it is sent to the driver through the output port 12, thereby realizing reliable data transmission. Pin 1 of the signal processing module 50 is connected to pin 98 of the FPGA chip 20, pin 2 of the signal processing module 50 is connected to pin 14 of the output port 12, pin 3 of the signal processing module 50 is connected to pin 6 of the output port 12, pin 4 of the signal processing module 50 is connected to the ground voltage, pin 5 of the signal processing module 50 is connected to pin 5 of the output port 12, pin 6 of the signal processing module 50 is connected to pin 13 of the output port 12, pin 7 of the signal processing module 50 is connected to pin 101 of the FPGA chip 20, pin 8 of the signal processing module 50 is connected to the ground voltage, pin 9 of the signal processing module 50 is connected to pin 100 of the FPGA chip 20, a capacitor C11 is connected between pin 12 and pin 16 of the signal processing module 50, pin 12 of the signal processing module 50 is connected to the ground voltage, and pin 16 of the signal processing module 50 is connected to a power supply voltage of 5V.
[0053] like Fig.10 As shown, the configuration module 60 includes a configuration chip U9 and a configuration interface U10. The configuration interface U10 is connected to the FPGA chip 20. The configuration interface U10 is used to receive external configuration information and transmit the configuration information to the FPGA chip 20 for the FPGA chip 20 to burn the program. The configuration chip U9 is connected to the FPGA chip. The configuration chip U9 is used to obtain and store configuration information from the FPGA chip 20.
[0054] Specifically, the configuration chip U9 is EPCS4, a serial configuration device that is mainly used to save the configuration information of the FPGA to ensure that the program is not lost when the power is off. EPCS4 has advanced features such as in-system programmable (ISP) and flash memory access interface, and uses a small outline integrated circuit (SOIC) package that saves single board space, making it a low-cost configuration device. The configuration interface U10 is a JTAG interface that can be connected to a computer via a USB Blaster burner.
[0055] Pin 1 of the configuration chip U9 is connected to pin 8 of the FPGA chip 20, pin 2 of the configuration chip U9 is connected to pin 13 of the FPGA chip 20, pin 3 of the configuration chip U9 is connected to the operating voltage of 3.3V, pin 4 of the configuration chip U9 is connected to the ground voltage, pin 8 and pin 7 of the configuration chip U9 are connected to the operating voltage of 3.3V, pin 5 of the configuration chip U9 is connected to pin 6 of the FPGA chip 20, and pin 6 of the configuration chip U9 is connected to pin 12 of the FPGA chip 20.
[0056] Pin 1 of the configuration interface U10 is connected to pin TCK of the FPGA chip 20, pin 1 of the configuration interface U10 is connected to the ground voltage through resistor R12, pin 2 of the configuration interface U10 is connected to the ground voltage, pin 3 of the configuration interface U10 is connected to pin TDO of the FPGA chip 20, pin 4 of the configuration interface U10 is connected to a working voltage of 2.5V, pin 5 of the configuration interface U10 is connected to pin TMS of the FPGA chip 20, pin 5 of the configuration interface U10 is connected to a working voltage of 2.5V through resistor R13, pin 7 of the configuration interface U10 is connected to pin TDI of the FPGA chip 20, pin 7 of the configuration interface U10 is connected to a working voltage of 2.5V through resistor R14, and pin 8 of the configuration interface U10 is connected to the ground voltage.
[0057] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.
[0058] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A motor precision compensation device, characterized in that: The device comprises a housing, a circuit board installed in the housing, and an input port and an output port connected to the circuit board, wherein the input port and the output port are fixedly installed to the housing, the input port is used to be connected to an encoder on a motor, the output port is used to be connected to a driver connected to the motor, and a motor precision compensation circuit connected to the input port and the output port is arranged on the circuit board; The motor precision compensation circuit includes a connected FPGA chip and a power management module, and a configuration module, a signal processing module and a clock module connected to the FPGA chip and the power management module. The FPGA chip is connected to the input port, the signal processing module is connected to the output port, the clock module is used to generate a clock signal and transmit the clock signal to the FPGA chip, and the power management module is used to provide working voltage to the FPGA chip, the configuration module, the signal processing module and the clock module.
2. The motor accuracy compensation device according to claim 1, characterized in that: The motor precision compensation circuit also includes a filter circuit connected to the power management module, and the filter circuit is used to filter the working voltage.
3. The motor accuracy compensation device according to claim 2, characterized in that: The filter circuit includes a plurality of capacitor groups, each of which is connected to a corresponding working voltage and a ground voltage, and each of which includes a plurality of capacitors connected in parallel.
4. The motor precision compensation device according to claim 1, characterized in that: The motor precision compensation circuit also includes a current limiting circuit, which is connected to the input port and the FPGA chip for current limiting.
5. The motor precision compensation device according to claim 4, characterized in that: The current limiting circuit includes a plurality of resistors connected to the input port and the FPGA chip.
6. The motor precision compensation device according to claim 1, characterized in that: The power management module includes an input filter circuit and multiple linear regulators. The input filter circuit is connected to the power supply voltage to filter the power supply voltage. The linear regulator is connected to the power supply voltage and one or more of the FPGA chip, configuration module, signal processing module and clock module. The linear regulator is used to convert the power supply voltage into an operating voltage.
7. The motor precision compensation device according to claim 6, characterized in that: The input filter circuit includes a first capacitor, a second capacitor, a first resistor and a light-emitting diode. The first capacitor and the second capacitor are connected in parallel between a power supply voltage and a ground voltage. The first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is connected to an anode of the light-emitting diode, and the cathode of the light-emitting diode is connected to the ground voltage.
8. The motor precision compensation device according to claim 1, characterized in that: The clock module includes a connected crystal oscillator and a reset circuit, wherein the reset circuit is used to reset the FPGA chip, the crystal oscillator is connected to the FPGA chip, and the crystal oscillator is used to generate a clock signal and transmit the clock signal to the FPGA chip.
9. The motor precision compensation device according to claim 8, characterized in that: The reset circuit includes a second resistor, a ninth capacitor and a button, the first end of the second resistor is connected to the working voltage, the second end of the second resistor is connected to the first end of the button, the first end of the ninth capacitor is connected to the first end of the button, the second end of the ninth capacitor is connected to the second end of the button and the ground voltage, and the third and fourth ends of the button are connected to the crystal oscillator.
10. The motor precision compensation device according to claim 1, characterized in that: The configuration module includes a configuration chip and a configuration interface. Both the configuration interface and the configuration chip are connected to the FPGA chip. The configuration interface is used to receive external configuration information and transmit the configuration information to the FPGA chip. The configuration chip is used to obtain and store the configuration information through the FPGA chip.