Package substrate

Abstract

A packaging substrate is mainly characterized in that an insulation protection layer is formed on a circuit structure, the outer side of the circuit structure comprises an insulation layer and a first circuit layer combined with the insulation layer, and the insulation layer is provided with at least one concave part, so that the insulation protection layer is combined with a combination layer formed in the concave part, or the insulation protection layer is embedded into the concave part and protrudes out of the concave part. Therefore, when the insulation protection layer is in an NSMD design, the part around the opening is not arranged on the surface of the insulation layer, so that the insulation protection layer is prevented from generating an overlarge undercut structure.

Description

Technical Field

[0001] The present application relates to a semiconductor manufacturing process, and more particularly to a packaging substrate. Background Art

[0002] With the rapid development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing in the direction of high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] Figure 1 It is a cross-sectional schematic diagram of a conventional packaging substrate 1 .

[0004] like Figure 1 As shown, a first circuit layer 11 embedded in the dielectric layer 10 and a second circuit layer 12 formed on the dielectric layer 10 are formed on two opposite surfaces of a dielectric layer 10, and at least one conductive blind hole 100 electrically connecting the first circuit layer 11 and the second circuit layer 12 is formed in the dielectric layer 10, and a solder mask 13 such as green paint is formed on two opposite surfaces of the dielectric layer 10 so that partial surfaces of the first circuit layer 11 and the second circuit layer 12 are exposed in the openings 130 of the solder mask 13 to serve as electrical contact pads.

[0005] However, in the existing packaging substrate 1, the solder mask 13 is designed as a non solder mask defined (NSMD), and the green paint around the opening 130 is arranged on the surface of the dielectric layer 10, thereby generating a larger undercut structure P, which easily causes the bottom of the solder mask 13 to peel off, resulting in poor reliability of the packaging substrate 1.

[0006] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content

[0007] In view of the various deficiencies of the above-mentioned prior art, the present application provides a packaging substrate, comprising: a circuit structure, the outer side of which includes an insulating layer and a first circuit layer combined with the insulating layer, wherein the insulating layer has at least one recess; and an insulating protective layer, disposed on the circuit structure, wherein the insulating protective layer is combined with a bonding layer formed in the recess, or the insulating protective layer is embedded in the recess and protrudes from the recess.

[0008] The present application also provides a method for manufacturing a packaging substrate, comprising: providing a circuit structure, the outer side of which includes an insulating layer and a first circuit layer combined with the insulating layer, wherein the insulating layer has at least one recess; and forming an insulating protective layer on the circuit structure, wherein the insulating protective layer is combined with a bonding layer formed in the recess, or the insulating protective layer is embedded in the recess and protrudes from the recess.

[0009] In the aforementioned packaging substrate and its manufacturing method, the circuit structure includes a core layer and wiring layers arranged on opposite sides of the core layer, wherein the core layer has at least one conductive through hole electrically connected to the wiring layer, and the insulating layer is formed on the core layer to cover the wiring layer and electrically connect the wiring layer to the first circuit layer.

[0010] In the aforementioned packaging substrate and its manufacturing method, the insulating layer is defined with a first surface and a second surface relative to each other, so that the first circuit layer is combined with the first surface of the insulating layer, and a second circuit layer is formed on the second surface of the insulating layer, and at least one conductive blind hole electrically connecting the first circuit layer and the second circuit layer is formed in the insulating layer.

[0011] In the aforementioned packaging substrate and its manufacturing method, the insulating protection layer has a plurality of openings so that a portion of the surface of the first circuit layer is exposed to the plurality of openings.

[0012] In the aforementioned packaging substrate and its manufacturing method, the bonding layer is made of metal material.

[0013] From the above, it can be seen that in the packaging substrate and its manufacturing method of the present application, the insulating protective layer is mainly combined with the bonding layer or embedded in the recess, so that when the insulating protective layer is designed as a non-solder mask definition (NSMD), the part around the opening will not be arranged on the surface of the insulating layer, and thus an excessively large bottom cut structure will not be generated. Therefore, compared with the prior art, the present application can avoid the problem of peeling off at the bottom of the insulating protective layer, thereby improving the reliability of the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a cross-sectional schematic diagram of an existing packaging substrate.

[0015] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing a packaging substrate of the present application.

[0016] FIG. 3A to FIG. 3B for FIG. 2B to FIG. 2D A cross-sectional schematic diagram of another embodiment of the present invention.

[0017] FIG. 4A to FIG. 4C It is a cross-sectional schematic diagram of a second embodiment of a method for manufacturing a packaging substrate of the present application.

[0018] FIG. 5A to FIG. 5B for FIG. 4B to FIG. 4C A cross-sectional schematic diagram of another embodiment of the present invention.

[0019] Description of Reference Numerals

[0020] 1,2,3,4,5 Package substrate

[0021] 10 Dielectric layer

[0022] 100,200,400 Conductive blind vias

[0023] 11,21,41 First circuit layer

[0024] 12,22,42 Second circuit layer

[0025] 13 Solder mask

[0026] 130,230a,230b,330a Opening

[0027] 2a,4a Line Structure

[0028] 20,40 Insulation layer

[0029] 210,220,410,420 Electrical contact pads

[0030] 23a,23b,33a Insulation protection layer

[0031] 24,90 plate body

[0032] 24a First side

[0033] 24b Second side

[0034] 240 Core Layer

[0035] 241 Wiring Layer

[0036] 242 Conductive vias

[0037] 25 Bonding layer

[0038] 40a First surface

[0039] 40b Second surface

[0040] 9 Bearing

[0041] 91 Release layer

[0042] 92 Metal Layer

[0043] P Undercut Structure

[0044] S recess. DETAILED DESCRIPTION

[0045] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0046] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0047] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing a packaging substrate 2 of the present application.

[0048] like Figure 2A As shown, a plate 24 is provided, which has a first side 24a and a second side 24b, so that an insulating layer 20 is formed on the first side 24a and the second side 24b of the plate 24 respectively, and at least one recess S is formed in the insulating layer 20 on the first side 24a.

[0049] In this embodiment, the board 24 includes a core layer 240 and wiring layers 241 disposed on two opposite surfaces of the core layer 240, wherein at least one conductive via 242 electrically connected to the wiring layers 241 is formed in the core layer 240. For example, the material forming the wiring layer 241 and the conductive via 242 includes copper material, and the material forming the core layer 240 is a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), or prepreg (PP).

[0050] Furthermore, the insulating layer 20 is a dielectric layer, and its forming material is such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0051] In addition, the insulating layer 20 is formed on the board 24 by lamination to cover the wiring layers 241 .

[0052] In addition, the insulating layer 20 on the first side 24 a is formed with the recesses S by laser or other methods.

[0053] like Figure 2B As shown, a bonding layer 25 is formed in the recess S of the first side 24 a so that the upper surface of the bonding layer 25 is flush with the upper surface of the insulating layer 20 of the first side 24 a .

[0054] In this embodiment, the bonding layer 25 is a metal material, such as a copper layer.

[0055] like Figure 2C As shown, a first circuit layer 21 is formed on the surface of the insulating layer 20 at the first side 24a, and a second circuit layer 22 is formed on the surface of the insulating layer 20 at the second side 24b, so as to obtain a circuit structure 2a.

[0056] In this embodiment, the first circuit layer 21 is made of copper material, and is electrically connected to the wiring layer 241. For example, the first circuit layer 21 adopts a redistribution layer (RDL) specification.

[0057] Furthermore, the second circuit layer 22 is made of copper material, which is electrically connected to the wiring layer 241, and at least one conductive blind via 200 electrically connected to the wiring layer 241, the first circuit layer 21 and the second circuit layer 22 can be formed in the insulating layer 20. For example, the second circuit layer 22 and the conductive blind via 200 adopt the circuit redistribution layer (RDL) specification.

[0058] like Figure 2D As shown, an insulating protective layer 23 a such as a solder mask is formed on the bonding layer 25 , and the insulating protective layer 23 a has a plurality of openings 230 a , so that a portion of the surface of the first circuit layer 21 is exposed through the plurality of openings 230 a to serve as an electrical contact pad 210 .

[0059] In this embodiment, the insulating protection layer 23 a is made of non solder mask defined (NSMD) to form the opening 230 a on the first side 24 a, so that the insulating protection layer 23 a does not contact the insulating layer 20 .

[0060] Furthermore, the insulating protection layer 23b is also formed on the surface of the insulating layer 20 on the second side 24b, and the insulating protection layer 23b on the second side 24b has a plurality of openings 230b, so that a portion of the surface of the second circuit layer 22 is exposed in the plurality of openings 230b, for use as electrical contact pads 220. For example, the openings 230b on the second side 24b can be made by solder mask defined (SMD) so that the insulating protection layer 23b contacts the insulating layer 20, so as to obtain the package substrate 2 of the present application.

[0061] In addition, if FIG. 3A to FIG. 3B Another method of manufacturing the package substrate 3 shown in FIG. 1 may omit Figure 2B The process of making the bonding layer 25 is to form the insulating protection layer 33a of the first side 24a in the recess S and protrude from the recess S and contact the insulating layer 20, and at the same time, the insulating protection layer 33a is formed with an opening 330a of non-solder mask definition (NSMD) specification.

[0062] Therefore, the first embodiment of the method for manufacturing the packaging substrates 2, 3 of the present application mainly designs the recess S so that the insulating protective layer 23a, 33a is combined with the bonding layer 25 or embedded in the recess S, so that when the insulating protective layer 23a, 33a is designed as a non-solder mask definition (NSMD), the solder mask material (such as green paint) around the openings 230a, 330a is not provided on the surface of the insulating layer 20, so that the insulating protective layer 23a, 33a will not produce an excessively large undercut structure, or even no undercut structure. Therefore, compared with the prior art, the method of this embodiment can effectively avoid the problem of peeling off at the bottom of the insulating protective layer 23a, 33a, thereby effectively improving the reliability of the packaging substrates 2, 3.

[0063] FIG. 4A to FIG. 4C The cross-sectional view of the second embodiment of the method for manufacturing the package substrate 4 of the present application is shown in FIG. The difference between the present embodiment and the first embodiment lies in the form of the package substrate 4, and the other structures are substantially the same, so the same points will not be described in detail below.

[0064] like Figure 4A As shown, a carrier 9 is provided to form circuit structures 4 a on two opposite sides of the carrier 9 .

[0065] In this embodiment, the carrier 9 is a temporary carrier, which can be a plate having metal surfaces on opposite sides, such as a copper foil substrate, and a release layer 91 is provided on the surface of the plate body 90, and a metal layer 92 such as a copper layer is formed on the release layer 91 so that the circuit structure 4a is formed on the metal layer 92.

[0066] Furthermore, the circuit structure 4 a includes a first circuit layer 41 and a bonding layer 25 disposed on the metal layer 92 , an insulating layer 40 disposed on the first circuit layer 41 and the bonding layer 25 , and at least one second circuit layer 42 formed on the insulating layer 40 .

[0067] The first circuit layer 41 is made of copper, and its material is the same as the material used to form the metal layer 92 .

[0068] In this embodiment, the first circuit layer 41 and the bonding layer 25 can be formed together on the metal layer 92 using a redistribution layer (RDL) specification.

[0069] The insulating layer 40 is defined to have a first surface 40 a and a second surface 40 b opposite to each other, so that the first surface 40 a is combined with the metal layer 92 , and the first circuit layer 41 is disposed on the first surface 40 a of the insulating layer 40 .

[0070] In this embodiment, the insulating layer 40 is a dielectric layer, and its forming material is such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0071] Furthermore, the insulating layer 40 is pressed onto the first circuit layer 41 and the bonding layer 25 in a pressing manner, so that the first circuit layer 41 and the bonding layer 25 are embedded in the insulating layer 40 .

[0072] The second circuit layer 42 is formed on the second surface 40 b of the insulating layer 40 , and at least one conductive blind via 400 electrically connecting the first circuit layer 41 and the second circuit layer 42 is formed in the insulating layer 40 .

[0073] In this embodiment, the second circuit layer 42 and the conductive blind via 400 adopt the circuit redistribution layer (RDL) specification.

[0074] like Figure 4B As shown, the plate body 90 of the carrier 9 and the metal layer 92 (as shown in FIG. 1 ) are separated by the release layer 91. Figure 4A Then, the metal layer 92 is removed to obtain a plurality of circuit structures 4a.

[0075] In this embodiment, the release layer 91 is removed by peeling or other methods to separate the plate 90 from the metal layer 92 , and the metal layer 92 is removed by etching.

[0076] Furthermore, the surfaces of the first circuit layer 41 and the bonding layer 25 are lower than or flush with the first surface 40 a of the insulating layer 40 , so that the first circuit layer 41 and the bonding layer 25 are exposed on the first surface 40 a of the insulating layer 40 .

[0077] like Figure 4C As shown, an insulating protection layer 23a is formed on the bonding layer 25 to form a coreless packaging substrate 4, and the insulating protection layer 23a has a plurality of openings 230a so that a portion of the surface of the first circuit layer 41 is exposed through the plurality of openings 230a to serve as an electrical contact pad 410.

[0078] In this embodiment, the insulating protection layer 23 a is formed by non-solder mask definition (NSMD) to form the opening 230 a, so that the insulating protection layer 23 a does not contact the insulating layer 40 .

[0079] Furthermore, the insulating protection layer 23b is also formed on the second surface 40b of the insulating layer 40, and the insulating protection layer 23b of the second surface 40b has a plurality of openings 230b, so that a portion of the surface of the second circuit layer 42 is exposed in the plurality of openings 230b, for use as electrical contact pads 420. For example, the openings 230b can be made using a solder mask (SMD) so that the insulating protection layer 23b contacts the insulating layer 40.

[0080] In addition, if FIG. 5A to FIG. 5B Another method for manufacturing the package substrate 5 shown in FIG. Figure 4B , the bonding layer 25 of the circuit structure 4a can be removed first to form a recess S on the first surface 40a of the insulating layer 40, so that the insulating protection layer 33a is formed in the recess S and protrudes from the recess S and contacts the insulating layer 40, and at the same time, the insulating protection layer 33a is formed with an opening 330a of a non-solder mask definition (NSMD) specification.

[0081] Therefore, the second embodiment of the method for manufacturing the packaging substrate 4, 5 of the present application mainly combines the insulating protective layer 23a, 33a with the bonding layer 25 or embeds it into the recess S, so that when the insulating protective layer 23a, 33a is designed as a non-solder mask definition (NSMD), the solder mask material (such as green paint) around the opening 230a, 330a is not provided on the first surface 40a of the insulating layer 40, so that the insulating protective layer 23a, 33a will not produce an excessively large undercut structure, or even no undercut structure. Therefore, compared with the prior art, the method of this embodiment can effectively avoid the problem of peeling off at the bottom of the insulating protective layer 23a, 33a, thereby effectively improving the reliability of the packaging substrate 4, 5.

[0082] The present application also provides a packaging substrate 2, 3, 4, 5, including: a circuit structure 2a, 4a and an insulating protection layer 23a, 33a.

[0083] The circuit structure 2a, 4a includes an insulating layer 20, 40 and a first circuit layer 21, 41 combined with the insulating layer 20, 40 on the outside, wherein the insulating layer 20, 40 has at least one recess S.

[0084] The insulating protection layer 23a, 33a is disposed on the circuit structure 2a, 4a, wherein the insulating protection layer 23a is combined with a bonding layer 25 formed in the recess S, or the insulating protection layer 33a is embedded in the recess S and protrudes from the recess S.

[0085] In one embodiment, the circuit structure 2a includes a core layer 240 and a wiring layer 241 disposed on two opposite surfaces of the core layer 240, wherein the core layer 240 has at least one conductive through hole 242 electrically connected to the wiring layer 241, and the insulating layer 20 is formed on the core layer 240 to cover the wiring layer 241 and electrically connect the wiring layer 241 to the first circuit layer 21.

[0086] In one embodiment, the insulating layer 40 is defined with a first surface 40a and a second surface 40b opposite to each other, so that the first circuit layer 41 is combined with the first surface 40a of the insulating layer 40, and a second circuit layer 42 is formed on the second surface 40b of the insulating layer 40, and at least one conductive blind hole 400 electrically connecting the first circuit layer 41 and the second circuit layer 42 is formed in the insulating layer 40.

[0087] In one embodiment, the insulating protection layer 23a, 33a has a plurality of openings 230a, 330a, so that a portion of the surface of the first circuit layer 21, 41 is exposed through the plurality of openings 230a, 330a.

[0088] In one embodiment, the bonding layer 25 is made of metal.

[0089] In summary, the packaging substrate and its manufacturing method of the present application, through the insulating protective layer combining the bonding layer or embedding the recess, when the insulating protective layer is designed as a non-solder mask definition (NSMD), the solder mask material around the opening is not provided on the surface of the insulating layer, thereby not generating an excessively large bottom cut structure. Therefore, the present application can effectively avoid the problem of peeling off at the bottom of the insulating protective layer, thereby effectively improving the reliability of the packaging substrate.

[0090] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be as set forth in the claims.

Claims

1. A packaging substrate, characterized in that: include: A circuit structure, the outer side of which includes an insulating layer and a first circuit layer combined with the insulating layer, wherein the insulating layer has at least one concave portion; and The insulating protection layer is arranged on the circuit structure, wherein the insulating protection layer is combined with a combination layer formed in the concave portion, or the insulating protection layer is embedded in the concave portion and protrudes from the concave portion.

2. The packaging substrate according to claim 1, wherein: The circuit structure includes a core layer and wiring layers arranged on two opposite surfaces of the core layer, wherein the core layer has at least one conductive through hole electrically connected to the wiring layer, and the insulating layer is formed on the core layer to cover the wiring layer and electrically connect the wiring layer to the first circuit layer.

3. The packaging substrate according to claim 1, wherein: The insulating layer is defined with a first surface and a second surface opposite to each other, so that the first circuit layer is combined on the first surface of the insulating layer, and a second circuit layer is formed on the second surface of the insulating layer, and at least one conductive blind hole electrically connecting the first circuit layer and the second circuit layer is formed in the insulating layer.

4. The packaging substrate according to claim 1, wherein: The insulating protection layer has a plurality of openings so that a portion of the surface of the first circuit layer is exposed from the plurality of openings.

5. The packaging substrate according to claim 1, wherein: The bonding layer is made of metal material.

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