Circuit of modular superposition type fault injection device
Through the circuit of the modular superimposed fault injection device, the signal source driving relay driver chip is used to control the relay status, which solves the problem that the existing fault injection device cannot combine the injection fault signal, and improves the test efficiency.
Patent Information
- Application Number
- CN202420024849.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-05
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-01-05
AI Technical Summary
The existing fault injection device integrated module is inconvenient for damage maintenance, and it is impossible to achieve combined injection of multiple fault signals, making it difficult to cope with complex testing environments.
Design a circuit of a modular superimposed fault injection device, drive the relay drive chip through a signal source to control the state of the relay, realize the individual or superimposed injection of the fault signal, and control the operation of the relay using reset, setting, address signal, etc. of the signal source. .
The individual or combination injection of fault signals is realized to meet the testing needs of different fault signals and improve the testing efficiency.
Smart Images
Figure CN222319056U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of fault injection testing, in particular to a circuit of a modularized superimposed fault injection device. Background Art
[0002] Fault injection is a test verification method, which injects faults into the device under test according to certain fault types set according to requirements, verifies whether the device fails, and evaluates the test performance of the product based on the results. It has become an important verification method for product testing and system verification, and is also a necessary verification method for functional safety.
[0003] At present, the fault injection device is placed between signal channels. As an integrated module, it is difficult to repair once it is damaged. In addition, the number of inputs and outputs is fixed, and the injected fault signals cannot be superimposed. The combined injection of multiple fault signals cannot be achieved, making it difficult to cope with increasingly complex test environments.
[0004] Therefore, it is necessary to design a circuit of a modular superposition fault injection device to realize the single injection or superposition injection of fault signals, meet the test requirements of different fault signals, and improve the test efficiency. Summary of the invention
[0005] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a circuit of a modular superposition fault injection device to achieve separate injection or superposition injection of fault signals, meet the test requirements of different fault signals, and improve test efficiency.
[0006] In order to achieve the above-mentioned purpose, the utility model is a circuit of a modular superposition fault injection device, including a signal source, a relay driving chip, and a relay. The reset signal RESET terminal, the setting input signal SET terminal, the address signal A0 terminal, the address signal A1 terminal, the address signal A2 terminal, the chip select signal CS terminal, and the potential signal LVL terminal of the signal source are connected in sequence with the RESET pin, SET pin, A0 pin, A1 pin, A2 pin, CS pin, and LVL pin of the relay driving chip, the OUT1 pin of the relay driving chip is connected with the No. 1 pin of the relay four, the OUT2 pin of the relay driving chip is connected with the No. 1 pin of the relay three, and the OUT3 pin of the relay driving chip is connected with the No. 1 pin of the relay two. Pins are connected, OUT4 pin of the relay driver chip is connected to pin 1 of relay one, pin 8 of relay one, pin 8 of relay two, pin 8 of relay three, and pin 8 of relay four are connected to the VCC power supply, pin 2 and pin 7 of relay one are connected to the interference voltage, pin 2 and pin 7 of relay two are connected to the interference ground, pin 2 and pin 7 of relay three are connected to the interference signal end of the signal source, pin 3 and pin 6 of relay one, pin 3 and pin 6 of relay two, pin 3 and pin 6 of relay three, pin 3 and pin 6 of relay four are connected to the expected signal end of the signal source, and after pin 4 and pin 5 of relay four are connected, they are connected to the output end.
[0007] The signal types outputted by the expected signal end and the interference signal end of the signal source are the same.
[0008] The VCC pin of the relay driving chip is divided into three paths and respectively connected to the COM pin of the relay driving chip, one end of the capacitor and the VCC power supply, and the other end of the capacitor is grounded.
[0009] The GND pin and the PGNG pin of the relay driver chip are grounded.
[0010] The model of the relay driver chip is MAX4821.
[0011] A parallel structure of a resistor and a diode is connected in series between pin 1 and pin 8 of relay one, relay two, relay three, and relay four; pin 2 and pin 7 are normally open contacts; pin 3 and pin 6 are switching contacts; and pin 4 and pin 5 are normally closed contacts.
[0012] The relay 1, relay 2, relay 3 and relay 4 are double-contact power relays, model RJ22S-CD-D5.
[0013] The relay 1 is a short-circuit relay for power supply, the relay 2 is a short-circuit relay for ground, the relay 3 is a short-circuit relay for signal room, and the relay 4 is a signal disconnect relay.
[0014] It also includes 1 to 4 additional relays, and pin 1 of the additional relay is connected to pin OUT5, pin OUT6, pin OUT7, or pin OUT8 of the relay driver chip.
[0015] Compared with the prior art, the utility model drives the relay driving chip through a signal source, thereby controlling the state of each relay, realizing the single injection of a certain fault signal or the superposition injection of several fault signals, meeting the test requirements of injecting different fault signals separately or in combination, and improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 This is a circuit diagram of the utility model.
[0017] Figure 2 This is the internal circuit diagram of the relay of the utility model. Implementation
[0018] The utility model is now further described with reference to the accompanying drawings.
[0019] See also Figure 1The utility model is a circuit of a modular superposition fault injection device, including a signal source, a relay driver chip, and a relay. The reset signal RESET terminal, the setting input signal SET terminal, the address signal A0 terminal, the address signal A1 terminal, the address signal A2 terminal, the chip selection signal CS terminal, and the potential signal LVL terminal of the signal source 1 are connected in sequence with the RESET pin, SET pin, A0 pin, A1 pin, A2 pin, CS pin, and LVL pin of the relay driver chip 2. The OUT1 pin of the relay driver chip 2 is connected with the No. 1 pin of the relay four K4, the OUT2 pin of the relay driver chip 2 is connected with the No. 1 pin of the relay three K3, the OUT3 pin of the relay driver chip 2 is connected with the No. 1 pin of the relay two K2, and the relay driver chip 2 The OUT4 pin is connected to the No. 1 pin of the relay K1, the No. 8 pin of the relay K1, the No. 8 pin of the relay K2, the No. 8 pin of the relay K3, and the No. 8 pin of the relay K4 are connected to the VCC power supply, the No. 2 pin and the No. 7 pin of the relay K1 are connected to the interference voltage, the No. 2 pin and the No. 7 pin of the relay K2 are connected to the interference ground, the No. 2 pin and the No. 7 pin of the relay K3 are connected to the interference signal end of the signal source 1, the No. 3 pin and the No. 6 pin of the relay K1, the No. 3 pin and the No. 6 pin of the relay K2, the No. 3 pin and the No. 6 pin of the relay K3, the No. 3 pin and the No. 6 pin of the relay K4 are connected to the expected signal end of the signal source 1, and the No. 4 pin and the No. 5 pin of the relay K4 are connected and then connected to the output end. The VCC pin of the relay driver chip 2 is divided into three paths and is respectively connected to the COM pin of the relay driver chip 2, one end of the capacitor and the VCC power supply, and the other end of the capacitor is grounded. The GND pin and the PGNG pin of the relay driver chip 2 are grounded.
[0020] Signal source 1 outputs several groups of fault injection control signals, expected signals and interference signals. The reset signal RESET terminal, input signal SET terminal, address signal A0 terminal, address signal A1 terminal, address signal A2 terminal, chip select signal CS terminal and potential signal LVL terminal of signal source 1 are control signal output terminals, which can address select, enable and reset the relay driver chip 2, and after decoding and amplification by the relay driver chip, generate an electrical signal to drive the relay and send it to each relay.
[0021] The address signal A0, the address signal A1, the address signal A2 and the reset signal RESET are unique and can uniformly control multiple fault injection devices; the input signal SET, the chip select signal CS, and the potential signal LVL are unique for a single expected signal, and multiple fault injection devices require multiple sets of input signals SET, chip select signals CS, and potential signals LVL.
[0022] The expected signal type of signal source 1 is not limited, such as CAN, SPI, temperature sensor signal, pressure sensor signal, etc. The expected signal end and the interference signal end of signal source 1 output the same signal type. The interference signal of signal source 1 includes the same type of interference as the expected signal and electromagnetic interference, etc. For example, when CANH is the expected signal, CANL or electrostatic interference can be the interference signal.
[0023] The model of relay driver chip 2 is MAX4821, which can be cascaded controlled. The SET pin of MAX4821 is the setting input signal. When the SET pin is low, all latches and registers are high and all outputs are turned on; the RESET pin is the reset signal. When the RESET pin is low, all chips have no output; the A0 pin, A1 pin, and A2 pin are address inputs. The address bit determines which output is updated; the LVL pin is a potential signal. The LVL pin determines whether the selected output is turned on or off; the CS pin is a chip select signal. When the CS pin is high, the address and potential have no effect on the output. The CS pin latches the address and level data into the parallel register from low to high and updates the output state. After the CS pin is pulled low, the input address data will not be reflected in the next low to high output state.
[0024] When the RESET pin is high and the SET pin is low, assuming that the A0 pin, A1 pin, and A2 pin are at a low level, the CS pin updates the output bit from low to high, and the LVL pin is high to turn on the selected bit output, then the OUT1 pin output is a high level.
[0025] Pin A0, pin A1, pin A2 and pin RESET are used as joint signals, and pin SET, pin CS and pin LVL are set independently. Assuming that two different types of faults of expected signals need to be injected into the device under test, the process is as follows: pin LVL is first pulled low, pin A0, pin A1, pin A2 select a certain address output, pin CS1 updates the address output from low to high and maintains a high level; pin A0, pin A1, pin A2 select another address output, pin CS2 updates the address output from low to high and maintains a high level; finally, pin LVL is pulled high at the same time to realize the conduction of different types of relays in the two fault injection devices.
[0026] See also Figure 2 , between pin 1 and pin 8 of relay 1 K1, relay 2 K2, relay 3 K3, and relay 4 K4, there is a parallel structure of a resistor and a diode in series, pins 2 and 7 are normally open contacts, pins 3 and 6 are changeover contacts, and pins 4 and 5 are normally closed contacts. Relay 1 K1, relay 2 K2, relay 3 K3, and relay 4 K4 are double-contact power relays, model RJ22S-CD-D5.
[0027] Relay 1 K1 is a short-circuit relay for power supply, relay 2 K2 is a short-circuit relay for ground, relay 3 K3 is a short-circuit relay between signals, and relay 4 K4 is a signal disconnect relay, representing four types of fault inputs. In addition to these four relays, it can also be expanded to add 1 to 4 additional relays. Pin 1 of the additional relay is connected to the OUT5 pin, OUT6 pin, OUT7 pin, or OUT8 pin of the relay driver chip 2, and other pins are connected accordingly according to the fault input type of the relay.
[0028] The external power supply provides power supply voltage to relay chip 2, relay 1 K1, relay 2 K2, relay 3 K3, and relay 4 K4, and provides interference voltage and interference ground to relay 1 K1 and relay 2 K2, wherein the power supply voltage and the interference voltage are independent of each other.
[0029] The utility model drives the relay driving chip through a signal source, thereby controlling the state of each relay, realizing the single injection of a certain fault signal or the superposition injection of several fault signals, meeting the test requirements of injecting different fault signals separately or in combination, and improving the test efficiency.
Claims
1. A circuit of a modular superposition fault injection device, comprising a signal source, a relay driver chip, and a relay, characterized in that: The reset signal RESET terminal, the set input signal SET terminal, the address signal A0 terminal, the address signal A1 terminal, the address signal A2 terminal, the chip select signal CS terminal, and the potential signal LVL terminal of the signal source (1) are connected to the RESET pin, SET pin, A0 pin, A1 pin, A2 pin, CS pin, and LVL pin of the relay driver chip (2) in sequence; the OUT1 pin of the relay driver chip (2) is connected to the No. 1 pin of relay four (K4); the OUT2 pin of the relay driver chip (2) is connected to the No. 1 pin of relay three (K3); the OUT3 pin of the relay driver chip (2) is connected to the No. 1 pin of relay two (K2); the OUT4 pin of the relay driver chip (2) is connected to the No. 1 pin of relay one (K1); and the relay one Pin 8 of relay one (K1), pin 8 of relay two (K2), pin 8 of relay three (K3), and pin 8 of relay four (K4) are connected to the VCC power supply, pin 2 and pin 7 of relay one (K1) are connected to the interference voltage, pin 2 and pin 7 of relay two (K2) are connected to the interference ground, pin 2 and pin 7 of relay three (K3) are connected to the interference signal end of signal source (1), pin 3 and pin 6 of relay one (K1), pin 3 and pin 6 of relay two (K2), pin 3 and pin 6 of relay three (K3), and pin 3 and pin 6 of relay four (K4) are connected to the expected signal end of signal source (1), and pin 4 and pin 5 of relay four (K4) are connected and then connected to the output end.
2. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: The signal type outputted by the expected signal end and the interference signal end of the signal source (1) is the same.
3. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: The VCC pin of the relay driving chip (2) is divided into three paths and respectively connected to the COM pin of the relay driving chip (2), one end of the capacitor and the VCC power supply, and the other end of the capacitor is grounded.
4. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: The GND pin and the PGNG pin of the relay drive chip (2) are grounded.
5. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: The model of the relay driver chip (2) is MAX4821.
6. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: A parallel structure of a resistor and a diode is connected in series between pins 1 and 8 of the relay 1 (K1), relay 2 (K2), relay 3 (K3), and relay 4 (K4); pins 2 and 7 are normally open contacts; pins 3 and 6 are switching contacts; and pins 4 and 5 are normally closed contacts.
7. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: The relay 1 (K1), relay 2 (K2), relay 3 (K3) and relay 4 (K4) are double-contact power relays, model RJ22S-CD-D5.
8. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: The relay 1 (K1) is a power supply short-circuit relay, the relay 2 (K2) is a ground short-circuit relay, the relay 3 (K3) is a signal short-circuit relay, and the relay 4 (K4) is a signal disconnect relay.
9. The circuit of a modular superposition fault injection device according to claim 1, characterized in that: It also includes 1 to 4 additional relays, and pin 1 of the additional relay is connected to pin OUT5, pin OUT6, pin OUT7, or pin OUT8 of the relay driver chip (2).