USB isolation circuit, chip, device and USB equipment

Abstract

The utility model discloses a USB isolation circuit, a chip, a device and USB equipment, which introduces millimeter wave isolation technology to realize an isolation transmission function, and comprises a first RF module, a plurality of second RF modules, an uplink side and a downlink side, the uplink side and the downlink side comprise interfaces in one-to-one correspondence with the second RF modules, and the interfaces are in one-to-one correspondence with the second RF modules. The uplink side and the downlink side communicate through the first RF module and the second RF module, the first RF module and the second RF module communicate through millimeter waves, and key isolation indexes such as voltage resistance, CMTI and bandwidth of the multi-interface USB equipment can be greatly improved.

Description

Technical Field

[0001] The utility model relates to the field of isolation technology, and in particular to a USB isolation circuit, a chip, a device and a USB equipment. Background Art

[0002] Isolation technology plays an irreplaceable role in the fields of communications, electronic equipment, power systems, etc. The common isolation technologies currently available are optical isolation, capacitive isolation, and magnetic isolation. Optical isolation uses the characteristics of light to achieve unidirectional signal transmission, capacitive isolation uses the capacitance effect to eliminate cross-interference of signals, and magnetic isolation isolates signals through magnetic field shielding. These isolation technologies ensure the stable operation of the system, the safe transmission of data, and reduce the impact of interference and noise.

[0003] However, it is difficult to achieve significant breakthroughs in key isolation indicators such as withstand voltage, CMTI and bandwidth using existing optical isolation, capacitive isolation and magnetic isolation methods. This is especially true for USB devices with multiple interfaces. Due to the presence of multiple interfaces, it is even more difficult to achieve breakthroughs in the above indicators. Utility Model Content

[0004] The technical problem to be solved by the utility model is to provide a USB isolation circuit, chip, device and USB device, which can greatly improve the key isolation indicators such as voltage resistance, CMTI and bandwidth of multi-interface USB devices.

[0005] In order to solve the above technical problems, a technical solution adopted by the utility model is:

[0006] A USB isolation circuit includes a first RF module, a plurality of second RF modules, an upstream side and a downstream side;

[0007] The uplink side includes an uplink port detection and control module, multiple uplink differential modules and multiple uplink interfaces;

[0008] The downstream side includes a downstream port detection and control module, multiple downstream differential modules and multiple downstream interfaces;

[0009] The uplink port detection and control module is connected to the downlink port detection and control module via the first RF module;

[0010] The second RF module, the uplink differential module, the downlink differential module, the uplink interface and the downlink interface correspond to each other one by one;

[0011] The uplink differential module is connected to the corresponding downlink differential module through the corresponding second RF module;

[0012] The uplink port detection and control module is connected to one of the uplink differential modules;

[0013] The downstream port detection and control module is connected to one of the downstream differential modules;

[0014] The uplink interface is connected to the corresponding uplink differential module;

[0015] The downlink interface is connected to the corresponding downlink differential module;

[0016] The first RF module and the second RF module both communicate using millimeter waves.

[0017] Further, comprising two second RF modules;

[0018] One of the uplink differential modules is connected to one of the downlink differential modules via one of the second RF modules;

[0019] One of the uplink interfaces is connected to one of the uplink differential modules;

[0020] One of the downlink interfaces is connected to one of the downlink differential modules;

[0021] Another said uplink differential module is connected to another said downlink differential module through another said second RF module;

[0022] Another of the uplink interfaces is connected to another of the uplink differential modules;

[0023] Another of the downstream interfaces is connected to another of the downstream differential modules.

[0024] Further, the uplink side further includes an uplink PU / PD module, and the downlink side further includes a downlink PU / PD module;

[0025] The uplink PU / PD module is respectively connected to the uplink port detection and control module, one of the uplink differential modules and one of the uplink interfaces;

[0026] The downlink PU / PD module is respectively connected to the downlink port detection and control module, one of the downlink differential modules and one of the downlink interfaces.

[0027] Further, the uplink differential module includes an uplink differential input module and an uplink differential output module;

[0028] The downlink differential module includes a downlink differential input module and a downlink differential output module;

[0029] The second RF module is connected to the corresponding uplink interface through the corresponding uplink differential input module and the uplink differential output module respectively;

[0030] The second RF module is connected to the corresponding downlink interface through the corresponding downlink differential input module and the downlink differential output module respectively.

[0031] In order to solve the above technical problems, another technical solution adopted by the utility model is:

[0032] The plurality of second RF modules are replaced by an upstream differential switch module located on the upstream side and a downstream differential switch module located on the downstream side;

[0033] The uplink differential module, the downlink differential module, the uplink interface and the downlink interface correspond one to one;

[0034] The first RF module is respectively connected to the upstream port detection and control module and the upstream differential module via the upstream differential switch module, and is respectively connected to the downstream port detection and control module and the downstream differential module via the downstream differential switch module.

[0035] Further, it includes two uplink differential modules and two downlink differential modules;

[0036] The uplink side also includes an uplink PU / PD module;

[0037] The downstream side also includes a downstream PU / PD module;

[0038] The uplink PU / PD module is respectively connected to the uplink port detection and control module, one of the uplink interfaces and one of the uplink differential modules;

[0039] The downlink PU / PD module is respectively connected to the downlink port detection and control module, one of the downlink interfaces and one of the downlink differential modules.

[0040] Further, the uplink differential switch module includes an uplink Mux module and an uplink De-Mux module;

[0041] The downstream differential switch module includes a downstream Mux module and a downstream De-Mux module;

[0042] The uplink Mux module and the uplink De-Mux module are respectively connected to the first RF module, the uplink port detection and control module and the uplink differential module;

[0043] The downlink Mux module and the downlink De-Mux module are respectively connected to the first RF module, the downlink port detection and control module and the downlink differential module.

[0044] Further, the uplink differential module includes an uplink differential output module and an uplink differential input module;

[0045] The downlink differential module includes a downlink differential output module and a downlink differential input module;

[0046] The uplink differential input module is respectively connected to the uplink Mux module and the corresponding uplink interface;

[0047] The uplink differential output modules are respectively connected to the uplink De-Mux module and the corresponding uplink interface;

[0048] The downlink differential input module is respectively connected to the downlink Mux module and the corresponding downlink interface;

[0049] The downstream differential output modules are respectively connected to the downstream De-Mux modules and the corresponding downstream interfaces.

[0050] In order to solve the above technical problems, another technical solution adopted by the utility model is:

[0051] A USB isolation chip is provided on which the USB isolation circuit is integrated.

[0052] In order to solve the above technical problems, another technical solution adopted by the utility model is:

[0053] A USB isolation device comprises the above USB isolation circuit.

[0054] In order to solve the above technical problems, another technical solution adopted by the utility model is:

[0055] A USB device comprises the above USB isolation circuit.

[0056] Furthermore, when two upstream interfaces are included, one of the upstream interfaces and its corresponding downstream interface is a USB 2.0 interface or a USB 1.x interface, and the other upstream interface and its corresponding downstream interface is a USB 3.0 interface.

[0057] The beneficial effects of the utility model are as follows: Different from the existing isolation technology, the present application introduces millimeter wave isolation technology to realize the isolated transmission function, based on the fact that millimeter wave is insensitive to the change of the "ground" at both ends of the isolation, so the CMTI index can be greatly improved; based on the fact that millimeter wave transmission does not require a charging and discharging process and the volume can be very small, it can also significantly improve the speed, withstand voltage and bandwidth, and is also suitable for multi-interface circuits. Therefore, the present application provides a USB isolation circuit, chip, device and USB device, which can greatly improve the key isolation indicators such as withstand voltage, CMTI and bandwidth of multi-interface USB devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a structural schematic diagram of a USB isolation circuit according to an embodiment of the utility model;

[0059] Figure 2 This is a structural schematic diagram of a USB isolation circuit according to another embodiment of the utility model;

[0060] Description of labels:

[0061] 1. First RF module; 2. Second RF module;

[0062] 3. Downward side; 4. Upward side;

[0063] 31. Downlink port detection and control module; 32. Downlink differential module;

[0064] 41. Uplink port detection and control module; 42. Uplink differential module;

[0065] 32-1, downstream differential output module; 32-2, downstream differential input module;

[0066] 42-1, uplink differential output module; 42-2, uplink differential input module;

[0067] 43. Uplink PU / PD module;

[0068] 33. Downlink PU / PD module;

[0069] 46. ​​Uplink differential switch module;

[0070] 46-1, uplink Mux module; 46-2, uplink De-Mux module;

[0071] 36. Downstream differential switch module;

[0072] 36-1, downstream Mux module; 36-2, downstream De-Mux module;

[0073] 5. Interface. DETAILED DESCRIPTION

[0074] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in conjunction with the implementation modes and the accompanying drawings.

[0075] like Figure 1 As shown, in an optional embodiment, a USB isolation circuit includes a first RF module 1, a plurality of second RF modules 2, an upstream side and a downstream side;

[0076] The uplink side 4 includes an uplink port detection and control module 41, multiple uplink differential modules 42 and multiple uplink interfaces;

[0077] The downstream side 3 includes a downstream port detection and control module 31, multiple downstream differential modules 32 and multiple downstream interfaces;

[0078] Among them, the uplink interface and the downlink interface constitute interface 5;

[0079] The uplink port detection and control module 41 is connected to the downlink port detection and control module 31 via the first RF module 1;

[0080] The second RF module 2, the uplink differential module 42, the downlink differential module 32, the uplink interface and the downlink interface correspond one to one;

[0081] The uplink differential module 42 is connected via the corresponding second RF module 2 and the corresponding downlink differential module 32;

[0082] The uplink port detection and control module 41 is connected to one of the uplink differential modules 42;

[0083] The downlink port detection and control module 31 is connected to one of the downlink difference modules 32;

[0084] The uplink interface is connected to the corresponding uplink differential module 42;

[0085] The downlink interface is connected to the corresponding downlink differential module 32;

[0086] The first RF module 1 and the second RF module 2 both use millimeter waves for communication;

[0087] Among them, Figure 1 As shown, the first RF module 1 includes a first RF sub-module 1a and a first RF sub-module 1b, wherein the first RF sub-module 1a is located at the downstream side 3, and the first RF sub-module 1b is located at the upstream side 4;

[0088] The second RF module 2 includes a second RF sub-module 2 a and a second RF sub-module 2 b , wherein the second RF sub-module 2 a is located at the downstream side 3 , and the second RF sub-module 2 b is located at the upstream side 4 .

[0089] In another optional embodiment, two second RF modules 2 are included;

[0090] One of the uplink differential modules 42 is connected via one of the second RF modules 2 and one of the downlink differential modules 32;

[0091] One of the uplink interfaces is connected to one of the uplink differential modules 42;

[0092] One of the downlink interfaces is connected to one of the downlink differential modules;

[0093] Another said uplink differential module 42 is connected to another said downlink differential module 32 through another said second RF module 2;

[0094] Another said uplink interface is connected to another said uplink differential module 42;

[0095] Another of the downstream interfaces is connected to another of the downstream differential modules 32 .

[0096] In another optional embodiment, the uplink side 4 further includes an uplink PU / PD module 43, and the downlink side 3 further includes a downlink PU / PD module 33;

[0097] The uplink PU / PD module 43 is respectively connected to the uplink port detection and control module 41, one of the uplink differential modules 42 and one of the uplink interfaces;

[0098] The downlink PU / PD module 33 is respectively connected to the downlink port detection and control module 31, one of the downlink differential modules 32 and one of the downlink interfaces.

[0099] Wherein, the uplink differential module 42 includes an uplink differential input module 42-2 and an uplink differential output module 42-1;

[0100] The downlink differential module 32 includes a downlink differential input module 32-2 and a downlink differential output module 32-1;

[0101] The second RF module 2 is connected to the corresponding uplink interface through the corresponding uplink differential input module 42-2 and the uplink differential output module 42-1;

[0102] The second RF module 2 is connected to the corresponding downlink interface through the corresponding downlink differential input module 32 - 2 and the downlink differential output module 32 - 1 .

[0103] In this embodiment, the upstream interface includes two, and the upstream interface and its corresponding downstream interface constitute an interface 5; one of the interfaces 5 is a USB2.0 interface or a USB1.x interface, and the other interface 5 is a USB3.0 interface;

[0104] On the downlink side, Figure 1 As shown, the interfaces 5 from top to bottom can be represented as DD+ / DD- and DSSTX+ / DSSTX- / DSSRX+ / DSSRX- respectively;

[0105] On the upstream side, Figure 1 As shown, the interfaces 5 from top to bottom can be represented as UD+ / UD- and USSTX+ / USSTX- / USSRX+ / USSRX- respectively;

[0106] Then DD+ / DD- and DSSTX+ / DSSTX- / DSSRX+ / DSSRX- (downstream ports) are connected to USB3.0 / 2.0 / 1.xDevice, and UD+ / UD- and USSTX+ / USSTX- / USSRX+ / USSRX- (upstream ports) are connected to USB3.0 / 2.0 / 1.xHost;

[0107] Figure 1 The attack capabilities of each module are as follows:

[0108] 1. 33-downlink PU / PD module, 43-uplink PU / PD module:

[0109] According to the input control signal, the differential interface DD+ / DD- or UD+ / UD- is pulled up or down;

[0110] 2. 32-2-downstream differential input module, 42-2-upstream differential input module ( Figure 1 The first one from top to bottom):

[0111] Receive USB2.0 / 1.x signals on the D+ / D- interface and convert them into internal signals;

[0112] 3. 32-1- Downstream differential output module, 42-1- Upstream differential input module ( Figure 1 The first one from top to bottom):

[0113] Convert internal signals into USB2.0 / 1.x signals and output them to the D+ / D- interface;

[0114] 4. 32-2-downlink differential input module, 42-2-uplink differential input module ( Figure 1 The second one from top to bottom):

[0115] Receive USB3.0 signals on the SSRX+ / SSRX- interface and convert them into internal signals;

[0116] 5. 32-1- Downstream differential output module, 42-1- Upstream differential input module ( Figure 1 The second one from top to bottom):

[0117] Convert the internal signal into USB3.0 signal and output it to SSTX+ / SSTX- interface;

[0118] 6. 31- Downlink port detection and control module:

[0119] According to the status of the downstream ports DD+ / DD- and DSSTX+ / DSSTX- / DSSRX+ / DSSRX- and the status information of the upstream side, the plug-in and unplugging and transmission direction detection are performed, and corresponding control signals are generated to perform plug-in control. At the same time, the generated status signals are transmitted to the upstream side via millimeter waves;

[0120] 7. 41-Uplink port detection and control module:

[0121] According to the status of the upstream ports UD+ / UD- and USSTX+ / USSTX- / USSRX+ / USSRX- and the status information of the upstream side, the plugging and unplugging and transmission direction detection are performed, and corresponding control signals are generated to perform plugging and unplugging control. At the same time, the generated status signals are transmitted to the downstream side via millimeter waves;

[0122] 8. 1- First RF module:

[0123] Used for transmission control and status wireless isolation channel;

[0124] 9.2- Second RF module ( Figure 1 The first one from top to bottom):

[0125] Wireless isolation channel for transmitting USB2.0 / 1.x data;

[0126] 10.2- Second RF module ( Figure 1 The second one from top to bottom):

[0127] Wireless isolation channel for transmitting USB3.0 data;

[0128] The working process of this embodiment is as follows:

[0129] 1. When no device is connected, DD+ and DD- are pulled down to 0 by the PU / PD module using a 15kΩ resistor; no termination resistor is detected on DSSTX+ / DSSTX-;

[0130] 2. When a USB3.0 device is connected, the termination resistor will be detected on DSSTX+ / DSSTX-; when a USB2.0 / 1.x device is connected, DD+ or DD- will be pulled up to 1 by the device's 1.5kΩ resistor (DD- is pulled up to 1 to indicate that the connected device is a low-speed device, and DD+ is pulled up to 1 to indicate that the connected device is a full-speed or high-speed device);

[0131] 3. The downlink port detection and control module transmits the status information of DD+ / DD- and DSSTX+ / DSSTX- to the uplink port detection and control module through the first RF submodule 1a on the downlink side and the first RF submodule 1b on the uplink side. The uplink port detection and control module connects a termination resistor to USSRX+ / USSRX-, or pulls the corresponding UD+ or UD- up to 1 using a 1.5kΩ resistor through the PU / PD module;

[0132] 4. If the connected device is a USB 3.0 device, enable the upstream and downstream sides respectively. Figure 1 The second second RF module from top to bottom, that is, the DSSRX+ / DSSRX- on the downstream side is directly connected with the USSTX+ / USSTX- on the upstream side through the above second RF module, and the USSRX+ / USSRX- on the upstream side is directly connected with the DSSTX+ / DSSTX- on the downstream side through the above second RF module. At this time, USB3.0 overspeed mode communication can be performed until the termination resistor is not detected on the DSSTX+ / DSSTX- on the downstream side, and the upstream and downstream sides return to the state of device disconnection;

[0133] 5. If the connected device is a USB2.0 / 1.x device, the upstream port detection and control module waits for the reset signal from the host (UD+ and UD- are both pulled down to 0), and then transmits the reset signal to the downstream port detection and control module through the first RF submodule 1a on the upstream side and the first RF submodule 1b on the downstream side. The downstream port detection and control module pulls DD+ and DD- down to 0 through the PU / PD module, thus generating a reset signal for the connected device;

[0134] 6. If the connected device is a high-speed device, similar to steps 3 and 4, according to the high-speed handshake process specified in the USB2.0 protocol, the status of DD+ and DD- is transferred to UD+ and UD-, or the status of UD+ and UD- is transferred to DD+ and DD-, thereby completing the high-speed identification handshake process;

[0135] After the above steps, the connection status and speed mode have been determined and remain unchanged;

[0136] Next, the downstream port detection and control module and the upstream port detection and control module detect the status of their respective D+ / D- in real time. The data transmission direction is determined by which side first detects that D+ / D- changes from the IDLE state to the data transmission state. If the downstream port detection and control module first detects that D+ / D- leaves the IDLE state, it first transmits this information to the upstream port detection and control module. After receiving the information, the upstream port detection and control module enables the differential output module, thereby establishing data transmission in the direction of DD+ / DD- to UD+ / UD-. When the downstream port detection and control module detects that the data transmission is completed, it transmits this information to the upstream port detection and control module. The upstream port detection and control module turns off the differential output and sets UD+ / UD- to the IDLE state. Both sides begin to prepare for the next transmission.

[0137] In low-speed or full-speed mode, if DD+ and DD- are detected to be 0 and exceed 2us, the device is considered disconnected. In high-speed mode, if the differential voltage of DD+ / DD- is greater than 625mV, the device is considered disconnected. After detecting that the device is disconnected, DD+ / DD- is pulled down to 0 through 15kΩ, and the pull-up resistor on UD+ / UD- is removed, returning to the state where the device is not connected.

[0138] This implementation can achieve isolated transmission of USB3.0 / 2.0 / 1.x via millimeter waves.

[0139] In another optional embodiment, Figure 2 As shown, the multiple second RF modules 2 are replaced by an uplink differential switch module 46 located on the uplink side 4 and a downlink differential switch module 36 located on the downlink side 3;

[0140] The uplink differential module 42, the downlink differential module 32, the uplink interface and the downlink interface correspond one to one;

[0141] The first RF module 1 is respectively connected to the uplink port detection and control module 41 and the uplink differential module 42 via the uplink differential switch module 46 , and is respectively connected to the downlink port detection and control module 36 and the downlink differential module 32 via the downlink differential switch module 36 .

[0142] In another optional embodiment, two uplink differential modules 42 and two downlink differential modules 32 are included;

[0143] The uplink side 4 also includes an uplink PU / PD module 43;

[0144] The downstream side 3 also includes a downstream PU / PD module 33;

[0145] The uplink PU / PD module 43 is respectively connected to the uplink port detection and control module 41, one of the uplink interfaces and one of the uplink differential modules 42;

[0146] The downlink PU / PD module 33 is respectively connected to the downlink port detection and control module 31, one of the downlink interfaces and one of the downlink differential modules 32.

[0147] Wherein, the uplink differential switch module 46 includes an uplink Mux module 46-1 and an uplink De-Mux module 46-2;

[0148] The downstream differential switch module 36 includes a downstream Mux module 36-1 and a downstream De-Mux module 36-2;

[0149] The uplink Mux module 46 - 1 and the uplink De-Mux module 46 - 2 are respectively connected to the first RF module 1 , the uplink port detection and control module 41 and the uplink differential module 42 ;

[0150] The downlink Mux module 36 - 1 and the downlink De-Mux module 36 - 2 are connected to the first RF module 1 , the downlink port detection and control module 31 and the downlink differential module 32 , respectively.

[0151] Wherein, the uplink differential module 42 includes an uplink differential output module 42-1 and an uplink differential input module 42-2;

[0152] The downlink differential module 32 includes a downlink differential output module 32-1 and a downlink differential input module 32-2;

[0153] The uplink differential input module 42-2 is respectively connected to the uplink Mux module 46-1 and the corresponding uplink interface;

[0154] The uplink differential output module 42-1 is respectively connected to the uplink De-Mux module 46-2 and the corresponding uplink interface;

[0155] The downlink differential input module 32-2 is respectively connected to the downlink Mux module 36-1 and the corresponding downlink interface;

[0156] The downstream differential output module 32 - 1 is respectively connected to the downstream De-Mux module 36 - 2 and the corresponding downstream interface.

[0157] In this embodiment, the upstream interface includes two, and the upstream interface and its corresponding downstream interface constitute an interface 5; one of the interfaces 5 is a USB2.0 interface or a USB1.x interface, and the other interface 5 is a USB3.0 interface;

[0158] On the downlink side, Figure 2 As shown, the interfaces 5 from top to bottom can be represented as DD+ / DD- and DSSTX+ / DSSTX- / DSSRX+ / DSSRX- respectively;

[0159] On the upstream side, Figure 2 As shown, the interfaces 5 from top to bottom can be represented as UD+ / UD- and USSTX+ / USSTX- / USSRX+ / USSRX- respectively;

[0160] Then DD+ / DD- and DSSTX+ / DSSTX- / DSSRX+ / DSSRX- (downstream ports) are connected to USB3.0 / 2.0 / 1.xDevice, and UD+ / UD- and USSTX+ / USSTX- / USSRX+ / USSRX- (upstream ports) are connected to USB3.0 / 2.0 / 1.xHost;

[0161] Figure 2 The attack capabilities of each module are as follows:

[0162] 1. 33-downlink PU / PD module, 43-uplink PU / PD module:

[0163] According to the input control signal, the differential interface DD+ / DD- or UD+ / UD- is pulled up or down;

[0164] 2. 32-2-downstream differential input module, 42-2-upstream differential input module ( Figure 2 The first one from top to bottom):

[0165] Receive USB2.0 / 1.x signals on the D+ / D- interface and convert them into internal signals;

[0166] 3. 32-1- Downstream differential output module, 42-1- Upstream differential input module ( Figure 2 The first one from top to bottom):

[0167] Convert internal signals into USB2.0 / 1.x signals and output them to the D+ / D- interface;

[0168] 4. 32-2-downlink differential input module, 42-2-uplink differential input module ( Figure 2 The second one from top to bottom):

[0169] Receive USB3.0 signals on the SSRX+ / SSRX- interface and convert them into internal signals

[0170] 5. 32-1- Downstream differential output module, 42-1- Upstream differential input module ( Figure 2 The second one from top to bottom):

[0171] Convert the internal signal into USB3.0 signal and output it to SSTX+ / SSTX- interface

[0172] 6. Mux module:

[0173] According to the selection signal, a signal from a differential input or control module is selected to the first RF module;

[0174] 7. De-Mux module:

[0175] Outputting the signal of the first RF module to the detection and control module or the differential output module;

[0176] 8. Downlink port detection and control module:

[0177] According to the status of the downstream ports DD+ / DD- and DSSTX+ / DSSTX- / DSSRX+ / DSSRX- and the status information of the upstream side, the plug-in and unplugging and transmission direction detection are performed, and corresponding control signals are generated to perform plug-in control. At the same time, the generated status signals are transmitted to the upstream side via millimeter waves;

[0178] 9. Uplink port detection and control module:

[0179] According to the status of the upstream ports UD+ / UD- and USSTX+ / USSTX- / USSRX+ / USSRX- and the status information of the upstream side, the plugging and unplugging and transmission direction are detected, and the corresponding control signals are generated to control the plugging and unplugging. At the same time, the generated status signals are transmitted to the downstream side via millimeter waves.

[0180] The working process of this embodiment is as follows:

[0181] 1. When no device is connected, DD+ and DD- are pulled down to 0 by the PU / PD module using a 15kΩ resistor, and no termination resistor is detected on DSSTX+ / DSSTX-;

[0182] 2. When a USB3.0 device is connected, the termination resistor will be detected on DSSTX+ / DSSTX-; when a USB2.0 / 1.x device is connected, DD+ or DD- will be pulled up to 1 by the device's 1.5kΩ resistor (DD- is pulled up to 1 to indicate that the connected device is a low-speed device, and DD+ is pulled up to 1 to indicate that the connected device is a full-speed or high-speed device);

[0183] 3. The downlink port detection and control module transmits the status information of DD+ / DD- and DSSTX+ / DSSTX- to the uplink port detection and control module through the Mux and the first RF submodule 1a on the downlink side and the first RF submodule 1b and De-Mux on the uplink side. The uplink port detection and control module connects a termination resistor to USSRX+ / USSRX-, or pulls the corresponding UD+ or UD- up to 1 using a 1.5kΩ resistor through the PU / PD module;

[0184] 4. If the connected device is a USB 3.0 device, select the Mux and De-Mux modules on both the upstream and downstream sides. Figure 2 The second differential input and the second differential output from top to bottom, i.e., the DSSRX+ / DSSRX- on the downstream side is directly connected with the USSTX+ / USSTX- on the upstream side through the first RF module, and the USSRX+ / USSRX- on the upstream side is directly connected with the DSSTX+ / DSSTX- on the downstream side through the first RF module. At this time, USB3.0 overspeed mode communication can be performed until the termination resistor is not detected on the DSSTX+ / DSSTX- on the downstream side, and the upstream side and the downstream side return to the state where the device is not connected;

[0185] 5. If the connected device is a USB2.0 / 1.x device, the upstream port detection and control module waits for the reset signal from the host (UD+ and UD- are both pulled down to 0), and then transmits the reset signal to the downstream port detection and control module through the Mux and the first RF submodule 1b on the upstream side and the first RF submodule 1a and De-Mux on the downstream side. The downstream port detection and control module pulls DD+ and DD- down to 0 through the PU / PD module, thus generating a reset signal for the connected device;

[0186] 6. If the connected device is a high-speed device, similar to steps 3 and 4, according to the high-speed handshake process specified in the USB2.0 protocol, the status of DD+ and DD- is transferred to UD+ and UD-, or the status of UD+ and UD- is transferred to DD+ and DD-, thereby completing the high-speed identification handshake process;

[0187] After the above steps, the connection status and speed mode have been determined and remain unchanged; next, the downstream port detection and control module and the upstream port detection and control module detect the status of their respective D+ / D- in real time. The data transmission direction is determined by which side first detects that D+ / D- changes from the IDLE state to the data transmission state. If the downstream port detection and control module first detects that D+ / D- leaves the IDLE state, it first transmits this information to the upstream port detection and control module, and then selects the Mux to the differential input module. After the upstream port detection and control module receives the information, it enables the differential output module, thereby establishing data transmission in the direction of DD+ / DD- to UD+ / UD-. When the downstream port detection and control module detects that the data transmission is completed, it transmits this information to the upstream port detection and control module. The upstream port detection and control module turns off the differential output and sets UD+ / UD- to the IDLE state, and both sides begin to prepare for the next transmission;

[0188] In low-speed or full-speed mode, if DD+ and DD- are detected to be 0 and exceed 2us, the device is considered disconnected. In high-speed mode, if the differential voltage of DD+ / DD- is greater than 625mV, the device is considered disconnected. After detecting that the device is disconnected, DD+ / DD- is pulled down to 0 through 15kΩ, and the pull-up resistor on UD+ / UD- is removed, returning to the state where the device is not connected.

[0189] This implementation can achieve isolated transmission of USB3.0 / 2.0 / 1.x via millimeter waves.

[0190] In another optional implementation, a USB isolation chip is provided, on which the USB isolation circuit described in any one of the above implementations is integrated.

[0191] In another optional implementation, a USB isolation device includes the USB isolation circuit described in any one of the above implementations.

[0192] In another optional implementation, a USB device includes the USB isolation circuit described in any one of the above implementations.

[0193] Furthermore, when the USB isolation circuit includes two interfaces 5, the upstream interface corresponding to one interface and the corresponding downstream interface thereof are USB2.0 interfaces or USB1.x interfaces, and the upstream interface corresponding to the other interface and the corresponding downstream interface thereof are USB3.0 interfaces.

[0194] In summary, the USB isolation circuit, chip, device and USB equipment provided by the utility model can greatly improve the key isolation indicators such as voltage resistance, CMTI and bandwidth of multi-interface USB devices, and realize isolated transmission of USB3.0 / 2.0 / 1.x through millimeter waves.

[0195] The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent transformations made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in the relevant technical field, are also included in the patent protection scope of the present invention.

Claims

1. A USB isolation circuit, characterized in that: It includes a first RF module, a plurality of second RF modules, an uplink side and a downlink side; The uplink side includes an uplink port detection and control module, multiple uplink differential modules and multiple uplink interfaces; The downstream side includes a downstream port detection and control module, multiple downstream differential modules and multiple downstream interfaces; The uplink port detection and control module is connected to the downlink port detection and control module via the first RF module; The second RF module, the uplink differential module, the downlink differential module, the uplink interface and the downlink interface correspond to each other one by one; The uplink differential module is connected to the corresponding downlink differential module through the corresponding second RF module; The uplink port detection and control module is connected to one of the uplink differential modules; The downstream port detection and control module is connected to one of the downstream differential modules; The uplink interface is connected to the corresponding uplink differential module; The downlink interface is connected to the corresponding downlink differential module; The first RF module and the second RF module both communicate using millimeter waves.

2. A USB isolation circuit according to claim 1, characterized in that: including two second RF modules; One of the uplink differential modules is connected to one of the downlink differential modules via one of the second RF modules; One of the uplink interfaces is connected to one of the uplink differential modules; One of the downlink interfaces is connected to one of the downlink differential modules; Another said uplink differential module is connected to another said downlink differential module through another said second RF module; Another of the uplink interfaces is connected to another of the uplink differential modules; Another of the downstream interfaces is connected to another of the downstream differential modules.

3. A USB isolation circuit according to claim 2, characterized in that: The uplink side also includes an uplink PU / PD module, and the downlink side also includes a downlink PU / PD module; The uplink PU / PD module is respectively connected to the uplink port detection and control module, one of the uplink differential modules and one of the uplink interfaces; The downlink PU / PD module is respectively connected to the downlink port detection and control module, one of the downlink differential modules and one of the downlink interfaces.

4. A USB isolation circuit according to claim 1 or 2, characterized in that: The uplink differential module includes an uplink differential input module and an uplink differential output module; The downlink differential module includes a downlink differential input module and a downlink differential output module; The second RF module is connected to the corresponding uplink interface through the corresponding uplink differential input module and the uplink differential output module respectively; The second RF module is connected to the corresponding downlink interface through the corresponding downlink differential input module and the downlink differential output module respectively.

5. A USB isolation circuit according to claim 1, characterized in that: The plurality of second RF modules are replaced by an upstream differential switch module located on the upstream side and a downstream differential switch module located on the downstream side; The uplink differential module, the downlink differential module, the uplink interface and the downlink interface correspond one to one; The first RF module is respectively connected to the upstream port detection and control module and the upstream differential module via the upstream differential switch module, and is respectively connected to the downstream port detection and control module and the downstream differential module via the downstream differential switch module.

6. A USB isolation circuit according to claim 5, characterized in that: It includes two uplink differential modules and two downlink differential modules; The uplink side also includes an uplink PU / PD module; The downstream side also includes a downstream PU / PD module; The uplink PU / PD module is respectively connected to the uplink port detection and control module, one of the uplink interfaces and one of the uplink differential modules; The downlink PU / PD module is respectively connected to the downlink port detection and control module, one of the downlink interfaces and one of the downlink differential modules.

7. A USB isolation circuit according to claim 5 or 6, characterized in that: The uplink differential switch module includes an uplink Mux module and an uplink De-Mux module; The downstream differential switch module includes a downstream Mux module and a downstream De-Mux module; The uplink Mux module and the uplink De-Mux module are respectively connected to the first RF module, the uplink port detection and control module and the uplink differential module; The downlink Mux module and the downlink De-Mux module are respectively connected to the first RF module, the downlink port detection and control module and the downlink differential module.

8. A USB isolation circuit according to claim 7, characterized in that: The uplink differential module includes an uplink differential output module and an uplink differential input module; The downlink differential module includes a downlink differential output module and a downlink differential input module; The uplink differential input module is respectively connected to the uplink Mux module and the corresponding uplink interface; The uplink differential output modules are respectively connected to the uplink De-Mux module and the corresponding uplink interface; The downlink differential input module is respectively connected to the downlink Mux module and the corresponding downlink interface; The downstream differential output modules are respectively connected to the downstream De-Mux modules and the corresponding downstream interfaces.

9. A USB isolation chip, characterized in that: The USB isolation circuit described in any one of claims 1 to 8 is integrated thereon.

10. A USB isolation device, characterized in that: It includes the USB isolation circuit described in any one of claims 1 to 8.

11. A USB device, characterized in that: It includes the USB isolation circuit described in any one of claims 1 to 8.

12. A USB device according to claim 11, characterized in that: When it includes the USB isolation circuit described in 2 or 6, one of the upstream interfaces and its corresponding downstream interface is a USB2.0 interface or a USB1.x interface, and the other upstream interface and its corresponding downstream interface is a USB3.0 interface.

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