Image acquisition system adopting independent acquisition box comprising multiple output interfaces
By designing independent acquisition boxes with multiple output interfaces, using high-performance FPGA chips and high-speed circuits, the problem that the existing technology cannot meet the needs of image acquisition equipment separation settings and multiple output methods is solved, and efficient and stable image data acquisition is achieved and transmission, adapt to a variety of application scenarios and high standards.
Patent Information
- Application Number
- CN202420787554.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-16
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2034-04-16
AI Technical Summary
The existing image acquisition cards cannot adapt to the separation and setting requirements of image sensors, image acquisition equipment and image processing display equipment, and cannot meet the data acquisition requirements of different output methods.
An independent acquisition box including multiple output interfaces is designed, using high-performance FPGA chips, reliable data storage circuits and high-speed image transceiver circuits. Image data is collected and output to USB, network ports and The FPD-LINK interface meets high standards for optical, infrared or radar image acquisition and processing.
It realizes efficient and stable image data acquisition and transmission, adapts to a variety of application scenarios and needs, is suitable for internal and external field testing and maneuverability needs, and is small and easy to carry.
Smart Images
Figure CN222356435U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of image acquisition, in particular to an image acquisition system using an independent acquisition box including multiple output interfaces. Background Art
[0002] With the development of various imaging technologies, image acquisition devices have been widely used in daily production and life. In addition, to meet the needs of work, image sensors, image acquisition devices, and image processing and display devices need to be set up separately, and the collected data can be output in different ways. The commonly used image acquisition cards cannot meet this need. Utility Model Content
[0003] In view of the above analysis, the utility model aims to provide an image acquisition system using an independent acquisition box including multiple output interfaces to solve the above problems.
[0004] The purpose of this utility model is mainly achieved through the following technical solutions:
[0005] The utility model discloses an image acquisition system using an independent acquisition box with multiple output interfaces; the system comprises: a sensor, an acquisition box and a host computer;
[0006] The acquisition box includes an input interface, a first output interface, a second output interface and a third output interface;
[0007] The image output interface of the sensor is connected to the input interface of the acquisition box; the first output interface and the second output interface are respectively connected to the corresponding interfaces of the host computer; the third output interface is an image test interface;
[0008] The sensor is an optical, infrared or radar sensor. After optical, infrared or radar imaging, the image data is output to the input interface of the acquisition box through the image output interface according to the FPD-LINK interface standard; the acquisition box acquires the image data received from the input interface; and outputs the acquired image data through the first, second or third output interface respectively; wherein the image data output from the first or second output interface is output to the host computer through the corresponding interface of the host computer respectively; the image data from the third output interface is used for testing;
[0009] Among them, the first output interface of the acquisition box is a USB port; the second output interface of the acquisition box is a network port; and the third output interface of the acquisition box adopts the FPD-LINK interface standard.
[0010] Furthermore, the collection box includes a shell and a circuit board placed in the shell;
[0011] The circuit board carries an FPGA chip, a data storage chip, a data receiving chip, a first data sending chip, a second data sending chip and a third data sending chip;
[0012] The input interface, the first output interface, the second output interface and the third output interface are located on the shell of the collection box;
[0013] Among them, the data storage chip is connected to the FPGA chip; the data receiving chip is connected between the input interface of the acquisition box and the FPGA chip; the first data sending chip is connected between the FPGA chip and the first output interface of the acquisition box, the second data sending chip is connected between the FPGA chip and the second output interface of the acquisition box, and the third data sending chip is connected between the FPGA chip and the third output interface of the acquisition box.
[0014] Furthermore, the FPGA chip is the XC7A100T-2FGG484I in the Xilinx A7 series FPGA.
[0015] Furthermore, the data storage chip includes one EEPROM and two SDRAMs.
[0016] Furthermore, the EEPROM uses the AT24C02 chip; the SDRAM uses the HY57V281620HC chip.
[0017] Furthermore, the data receiving chip is a DC balanced bidirectional control deserializer chip; the first data sending chip is a USB chip, the second data sending chip is a Gigabit Ethernet chip; and the third data sending chip is a DC balanced bidirectional control serializer chip.
[0018] Furthermore, the data receiving chip is GM8914; the USB chip is FT601Q; the Gigabit Ethernet chip is KSZ9031RNXIA; and the third data sending chip is GM8913.
[0019] Furthermore, the input interface of the acquisition box adopts HJ30J-12ZKW, the first output interface is a Type-A USB port; the second output interface is an RJ45 Gigabit network port, and the third output interface adopts HJ30J-12ZKW.
[0020] Furthermore, the acquisition box also includes a JTAG connector connected to the FPGA chip.
[0021] Furthermore, the JTAG connector is J30J-9ZKWJ.
[0022] The beneficial effects of the utility model are as follows:
[0023] The image acquisition system disclosed by the utility model, which adopts an independent acquisition box including multiple output interfaces, takes into account multiple application scenarios and requirements, and realizes efficient and stable image data acquisition and transmission by adopting high-performance chips and diversified interface designs. Through high-performance FPGA chips, reliable data storage circuits, high-speed image transceiver circuits and multiple data transmission interfaces, the device can meet the high standard requirements of optical, infrared or radar image acquisition and processing, adopts an independent acquisition box structure, is compact and easy to carry, and is suitable for indoor and outdoor field testing and mobility needs. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components.
[0025] Figure 1 This is a schematic diagram of the connection components of the image acquisition system in the embodiment of the utility model;
[0026] Figure 2 This is a schematic diagram of the appearance of the collection box in the embodiment of the utility model;
[0027] Figure 3 This is a schematic diagram of an FPGA clock circuit in an embodiment of the utility model;
[0028] Figure 4 This is a schematic diagram of the FPGA SPI configuration circuit in the embodiment of the utility model;
[0029] Figure 5 This is the circuit diagram of HY57V281620HC in the embodiment of the utility model;
[0030] Figure 6 This is the circuit diagram of AT24C02 in the embodiment of the utility model;
[0031] Figure 7 This is a functional block diagram of GM8914 in an embodiment of the utility model;
[0032] Figure 8 The GM8914 circuit diagram in the embodiment of the utility model is shown in FIG.
[0033] Fig. 9 This is a functional block diagram of GM8913 in an embodiment of the utility model;
[0034] Fig.10 This is the circuit diagram of GM8913 in the embodiment of the utility model;
[0035] Fig.11 It is a functional block diagram of FT601Q in the embodiment of the utility model;
[0036] Fig.12 This is a functional block diagram of KSZ9031RNXIA in an embodiment of the present utility model. DETAILED DESCRIPTION
[0037] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present application and are used together with the embodiments of the present invention to illustrate the principles of the present invention.
[0038] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved more clearly, the technical solutions of the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention,
[0039] All other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present utility model.
[0040] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0041] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0042] A specific embodiment of the utility model discloses an image acquisition system using an independent acquisition box including multiple output interfaces; Figure 1 As shown, it includes: sensor, acquisition box and host computer;
[0043] The acquisition box includes an input interface, a first output interface, a second output interface and a third output interface;
[0044] The image output interface of the sensor is connected to the input interface of the acquisition box; the first output interface and the second output interface are respectively connected to the corresponding interfaces of the host computer; the third output interface is an image test interface;
[0045] The sensor is an optical, infrared or radar sensor. After optical, infrared or radar imaging, the image data is output to the input interface of the acquisition box through the image output interface according to the FPD-LINK interface standard; the acquisition box acquires the image data received from the input interface; and outputs the acquired image data through the first, second or third output interface respectively; wherein the image data output from the first or second output interface is output to the host computer through the corresponding interface of the host computer respectively; the image data from the third output interface is used for testing;
[0046] Among them, the first output interface of the acquisition box is a USB port; the second output interface of the acquisition box is a network port; and the third output interface of the acquisition box adopts the FPD-LINK interface standard.
[0047] Specifically, the collection box includes a shell and a circuit board placed in the shell;
[0048] The circuit board carries an FPGA chip, a data storage chip, a data receiving chip, a first data sending chip, a second data sending chip and a third data sending chip; and supporting connecting components and connecting lines of the above chips;
[0049] The input interface, the first output interface, the second output interface and the third output interface are located on the shell of the collection box;
[0050] Among them, the data storage chip is connected to the FPGA chip; the data receiving chip is connected between the input interface of the acquisition box and the FPGA chip; the first data sending chip is connected between the FPGA chip and the first output interface of the acquisition box, the second data sending chip is connected between the FPGA chip and the second output interface of the acquisition box, and the third data sending chip is connected between the FPGA chip and the third output interface of the acquisition box.
[0051] Each interface on the housing is welded with each connection point on the circuit board through cables to form a circuit path.
[0052] In addition, the shell is also equipped with a power interface and corresponding indicator lights. The color and number of the indicator lights can be set according to specific needs.
[0053] In addition, all chips for image acquisition are placed on a circuit board, and measures such as reinforcement, moisture-proof, mildew-proof, salt spray-proof, wind-proof, dust-proof and rust-proof are adopted to improve the reliability of the device. Moreover, these measures are mature in technology and have lower costs compared with the test system structure based on PXI and PCI buses.
[0054] This embodiment provides a specific acquisition box; its dimensions are 122.5*88*30 (mm), it is made of aluminum alloy, and its color is oxidized black. The left side of the acquisition box is equipped with 1 power interface, 1 network port (second output interface), 1 USB interface (first output interface), and 4 indicator lights, and the right side of the device is equipped with 1 image input interface and 1 JTAG debugging port.
[0055] Figure 2 This is a schematic diagram of the appearance of a collection box (the third output interface is not shown in the figure, and the position of the interface can be set according to the situation).
[0056] Specifically, the FPGA chip on the circuit board is the XC7A100T-2FGG484I in the Xilinx A7 series FPGA. This is a high-performance programmable logic device that can handle complex algorithms and logic control, and is very suitable for real-time processing and analysis of images.
[0057] Specifically, the data storage chips on the circuit board include one EEPROM and two SDRAMs.
[0058] Specifically, the data receiving chip on the circuit board is a DC balanced bidirectional control deserializer chip; the first data sending chip is a USB chip, the second data sending chip is a Gigabit Ethernet chip; and the third data sending chip is a DC balanced bidirectional control serializer chip.
[0059] More specifically, in the design of the FPGA clock circuit, the clock circuit uses an active crystal oscillator, and the clock signal is connected to the FPGA global clock pin. Figure 4 As shown,
[0060] More specifically, in the FPGA configuration circuit design, the solution of this embodiment adopts the SPI serial configuration method, that is, the FPGA chip is the master device and the SPI serial FLASH is the slave device.
[0061] SPI signal names and function descriptions are shown in Table 1.
[0062]
[0063] FPGA SPI configuration circuit interface diagram as shown below Figure 3 shown.
[0064] More specifically, the design of FPGA general IO mainly involves the control design of data storage chips, deserializer chips, USB chips, Gigabit Ethernet chips and serializer chips, as well as the design of LED indicator lights. Among them, the Bank_13 pins are distributed as the network port signals of the Gigabit Ethernet chip and the EEPROM signals in the data storage circuit. The Bank_14 pins are distributed as the USB signals of the FPGA configuration part, LED indicators and USB chips. The Bank_15 and 16 pins are mainly distributed as SDRAM signals in the data storage circuit, and there are also a small number of USB signals. The Bank34 pins are distributed as DDR3 signals. The Bank_35 signal distribution is the transceiver signals of the deserializer chip and the serializer chip.
[0065] Since high-speed signals are not involved in this embodiment, the FPGA high-speed IO part is not used.
[0066] Specifically, the data storage circuit includes 1 EEPROM and 2 SDRAMs. The fastest image receiving rate is 62.5MB per second, and the SDRAM memory is 320M bytes in total. When the host computer does not read data, the SDRAM memory can cache for 5 seconds. It has been verified that the effective upload rate of the USB interface in this solution can reach 260MB / s, and the effective transmission rate of the Gigabit Ethernet interface can reach 100MB / s. Both interface modes can meet the requirements of data transmission.
[0067] More specifically, in the SDRAM circuit design, SDRAM uses two HY57V281620HC chips.
[0068] like Figure 5 Shown is the circuit diagram of HY57V281620HC.
[0069] More specifically, in the EEPROM circuit design, the EEPROM uses the AT24C02 chip from Microchip, Inc. AT24C02 is a 2K-bit serial CMOS EEPROM with 256 8-bit bytes inside.
[0070] like Figure 6 Shown is the circuit diagram of AT24C02.
[0071] Specifically, the DC balanced bidirectional control deserializer chip can be GM8914 of Chengdu Zhenxin Technology Co., Ltd.; it converts the high-speed differential serial coded data of the FPD-LINK interface standard into parallel data and synchronously outputs a clock signal; Figure 7 This is the functional block diagram of GM8914. Figure 8 This is the circuit diagram of GM8914.
[0072] Specifically, the DC balanced bidirectional control serializer chip may be GM8913 produced by Chengdu Zhenxin Technology Co., Ltd., which converts parallel data and clock information into high-speed differential serial data of the FPD-LINK interface standard. Fig. 9 This is the functional block diagram of GM8913. Fig.10 This is the circuit diagram of GM8913.
[0073] Specifically, the USB chip uses the FT601Q chip of FTDI Company; USB3.0 communication between FPGA and USB is realized;
[0074] Fig.11 This is the functional block diagram of the FT601Q.
[0075] Specifically, the Gigabit Ethernet chip uses the KSZ9031RNXIA chip from Microchip, USA, to realize the communication function between the network port and the FPGA;
[0076] Fig.12 This is the functional block diagram of KSZ9031RNXIA.
[0077] Specifically, the input interface on the acquisition box adopts HJ30J-12ZKW;
[0078] The first output interface is a Type-A USB3.0 connector; the USB3.0 connector uses XKB's U231-091N-1BLRC19-F5;
[0079] The second output interface is the RGMII interface, which supports data transmission at 10 / 100 / 1000Mbps. The RGMII interface uses XKB's X01AQ066BA2AD, with indicator light, and is RJ45 type.
[0080] The third output interface adopts HJ30J-12ZKW;
[0081] The pins of the third output interface may also be connected to the free pins of the input interface, so that the sensor can receive the high-speed differential serial data of the FPD-LINK interface standard output by the third output port to perform image self-test.
[0082] Furthermore, the acquisition box also includes a JTAG connector connected to the FPGA chip, which is used to test and debug the functions of the FPGA chip.
[0083] Furthermore, the JTAG connector is J30J-9ZKWJ.
[0084] Specifically, the acquisition box of this embodiment needs to use 5V to power the circuit board. There are two ways to obtain 5V power. One is powered by USB3.0, and the other is powered by the power supply interface (push-pull self-locking connector). The core controller of the circuit board is Xilinx 7 series FPGA. In order to meet the normal operation of FPGA, the voltages that the board needs to provide are VCCINT_1V0, VCC_1V5, VCC_1V8, VCCAUX_1V8 and VCC_3V3. The voltages that DDR3 needs to provide are DDR_VTT, DDR_VREF, and VCC1V5. The voltage that GM8913 and GM8914 need to provide is VCC_1V8. The voltage that EEPROM, SDRAM, and USB chips need to provide is VCC_3V3. The voltages required by Ethernet chips are VCC1V2 and VCC3V3.
[0085] In summary, the image acquisition system disclosed in this embodiment, which uses an independent acquisition box with multiple output interfaces, takes into account a variety of application scenarios and requirements, and realizes efficient and stable image data acquisition and transmission by adopting high-performance chips and diversified interface designs. Through high-performance FPGA chips, reliable data storage circuits, high-speed image transceiver circuits, and multiple data transmission interfaces, the device can meet the high standards for optical, infrared, or radar image acquisition and processing, and adopts an independent acquisition box structure with a compact shape and easy to carry, which is suitable for indoor and outdoor field testing and mobility needs.
[0086] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention.
Claims
1. An image acquisition system using an independent acquisition box including multiple output interfaces, characterized in that: include: Sensor, acquisition box and host computer; The acquisition box includes an input interface, a first output interface, a second output interface and a third output interface; The image output interface of the sensor is connected to the input interface of the acquisition box; the first output interface and the second output interface are respectively connected to the corresponding interfaces of the host computer; the third output interface is an image test interface; The sensor is an optical, infrared or radar sensor. After optical, infrared or radar imaging, the image data is output to the input interface of the acquisition box through the image output interface according to the FPD-LINK interface standard; the acquisition box acquires the image data received from the input interface; and outputs the acquired image data through the first, second or third output interface respectively; wherein the image data output from the first or second output interface is output to the host computer through the corresponding interface of the host computer respectively; the image data from the third output interface is used for testing; Among them, the first output interface of the acquisition box is a USB port; the second output interface of the acquisition box is a network port; and the third output interface of the acquisition box adopts the FPD-LINK interface standard.
2. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 1, characterized in that: The collection box comprises a shell and a circuit board placed in the shell; The circuit board carries an FPGA chip, a data storage chip, a data receiving chip, a first data sending chip, a second data sending chip and a third data sending chip; The input interface, the first output interface, the second output interface and the third output interface are located on the shell of the acquisition box; Among them, the data storage chip is connected to the FPGA chip; the data receiving chip is connected between the input interface of the acquisition box and the FPGA chip; the first data sending chip is connected between the FPGA chip and the first output interface of the acquisition box, the second data sending chip is connected between the FPGA chip and the second output interface of the acquisition box, and the third data sending chip is connected between the FPGA chip and the third output interface of the acquisition box.
3. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 2, characterized in that: The FPGA chip is the XC7A100T-2FGG484I from the Xilinx A7 series FPGA.
4. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 3, characterized in that: The data storage chip includes 1 EEPROM and 2 SDRAM chips.
5. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 4, characterized in that: The EEPROM uses the AT24C02 chip; the SDRAM uses the HY57V281620HC chip.
6. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 2, characterized in that: The data receiving chip is a DC balanced bidirectional control deserializer chip; the first data sending chip is a USB chip, the second data sending chip is a Gigabit Ethernet chip; and the third data sending chip is a DC balanced bidirectional control serializer chip.
7. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 6, characterized in that: The data receiving chip is GM8914; the USB chip is FT601Q; the Gigabit Ethernet chip is KSZ9031RNXIA; and the third data sending chip is GM8913.
8. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 2, characterized in that: The input interface of the acquisition box adopts HJ30J-12ZKW, the first output interface is a Type-A USB port; the second output interface is an RJ45 Gigabit network port, and the third output interface adopts HJ30J-12ZKW.
9. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 8, characterized in that: The acquisition box also includes a JTAG connector connected to the FPGA chip.
10. The image acquisition system using an independent acquisition box with multiple output interfaces according to claim 9, characterized in that: The JTAG connector is J30J-9ZKWJ.