Active clamping circuit and switching power supply

Abstract

The utility model discloses an active clamping circuit and a switching power supply. The switching power supply comprises an inverter circuit, a transformer, a secondary rectification circuit, a clamping capacitor, a main power inductor and a clamping tube. The clamping tube is an NMOS tube, and the active clamping circuit comprises a signal selecting and processing circuit, a pulse width limiting circuit and a bootstrap driving circuit which are connected in sequence; the signal selecting and processing circuit is used for accessing driving signals of a first main power tube and a second main power tube of the inverter circuit and outputting a first level signal when the driving signals meet a preset condition, the first level signal is subjected to pulse width limitation by the pulse width limiting circuit and bootstrapped by the bootstrap driving circuit, and then a pulse signal is output to the clamping tube; therefore, the clamping tube is driven to be conducted. According to the utility model, when the clamping circuit absorbs high-speed large current, the voltage stress peak is effectively absorbed and clamped through the clamping tube; and meanwhile, the problem of damage caused by too small current stress of the P MOS tube is effectively avoided.

Description

Technical Field

[0001] The present application relates to the technical field of power supply, and in particular to an active clamping circuit and a switching power supply. Background Art

[0002] In the topology of switching power conversion, the bridge topology is widely used in our switching power modules due to its advantages of high efficiency and high output power. When the bridge topology outputs high power, the output current is large. Due to the resonance of leakage inductance, capacitance and parasitic parameters, a high stress spike is generated at VBUS, and the oscillation frequency of the stress spike is an inherent parasitic parameter of the product. Therefore, a clamping circuit is needed to absorb the stress spike and improve the reliability of the switching power module.

[0003] At present, the traditional active clamping circuit is to perform active clamping through the P MOS tube model. The biggest disadvantage of this model is that the conventional P MOS tubes on the market are all small current tubes, and it is difficult to select tubes of 200V and above. In some occasions with high current and high withstand voltage, it is difficult to select active clamping circuit devices; in addition, the traditional active clamping circuit samples the rising edge signal of the VBUS voltage and obtains the driving signal of the clamped Pmos tube after logical processing of the signal. At this time, the driving time of the Pmos tube has lagged behind the rising time of the VBUS voltage. The lag time mainly includes two parts: sampling delay and logical processing delay, such as Figure 1 As shown in the figure, it is a waveform diagram of the Pmos tube and VBUS voltage using a traditional active clamping circuit. The lag time makes the Pmos tube still not turned on when the stress spike of VBUS arrives at t0. At this time, the energy of the stress spike can only be absorbed by the body diode of the Pmos tube. The diode injects a large current at time t0, and there is a conductivity modulation effect. The PN junction resistivity is very large, which causes a high conduction voltage drop at both ends of the diode, resulting in poor absorption effect of traditional active clamping. VBUS still has a large stress spike, affecting the reliability of the power module. Utility Model Content

[0004] In view of the above background, the utility model provides an active clamping circuit and a switching power supply. The circuit changes the previous solution of using a PMOS tube as a clamp, and optimizes the clamping Nmos tube to be turned on before the VBUS voltage spike, avoiding the conductivity modulation effect of the diode and achieving a significant absorption effect.

[0005] In order to achieve the above purpose, the utility model proposes the following technical solutions:

[0006] In a first aspect, an active clamping circuit is provided, which is applied to a switching power supply, wherein the switching power supply includes an inverter circuit, a transformer, a secondary rectifier circuit, a clamping capacitor, a main power inductor, and a clamping tube; the clamping tube is an NMOS tube, and the active clamping circuit includes: a signal selection and processing circuit, a pulse width limiting circuit, and a bootstrap driving circuit connected in sequence; the bootstrap driving circuit includes a driving module, a capacitor C3, and a diode D3, wherein an input terminal HI of the driving module is connected to an output terminal of the pulse width limiting circuit, an output first terminal VB of the driving module is connected to an anode of the diode D3, a cathode of the diode D3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to an output third terminal VS of the driving module and then connected to a D pole of the clamping tube, and an output second terminal HO of the driving module is connected to a G pole of the clamping tube;

[0007] The signal selection and processing circuit is used to access the drive signals of the first main power tube and the second main power tube of the inverter circuit, and output a first level signal when the drive signal meets the preset conditions. The first level signal is pulse-width limited by the pulse width limiting circuit, and then bootstrapped by the bootstrap driving circuit to output a pulse signal to the clamp tube to drive the clamp tube to conduct.

[0008] Preferably, the pulse width limiting circuit includes a resistor R2, a diode D2 and a capacitor C2, one end of the capacitor C2 serves as the input end of the pulse width limiting circuit and is connected to the output end of the signal selection and processing circuit, the other end of the capacitor C2 is connected to one end of the resistor R2 and the cathode of the diode D2, and then serves as the output end of the pulse width limiting circuit and is connected to the input end of the bootstrap drive circuit, the other end of the resistor R2 and the anode of the diode D2 are both grounded.

[0009] Preferably, the signal selection and processing circuit is an OR gate, and the first input terminal and the second input terminal of the OR gate are respectively used to access the drive signals of the first main power tube and the second main power tube of the inverter circuit; when the drive signal meets the preset conditions, the signal selection and processing circuit outputs a first level signal, specifically including:

[0010] When any driving signal of the first main power tube and the second main power tube is at a high level, a first level signal of a high level is output.

[0011] In a second aspect, an active clamping circuit is provided, which is applied to a switching power supply, wherein the switching power supply includes an inverter circuit, a transformer, a secondary rectifier circuit, a clamping capacitor, a main power inductor, and a clamping tube; the clamping tube is an NMOS tube, and the active clamping circuit includes: a signal selection and processing circuit, a pulse width limiting circuit, and a bootstrap driving circuit connected in sequence; the signal selection and processing circuit is an OR gate; the pulse width limiting circuit includes a resistor R2, a diode D2, and a capacitor C2; the bootstrap driving circuit includes a driving module, a capacitor C3, and a diode D3;

[0012] The first input end and the second input end of the OR gate are respectively used to access the driving signals of the first main power tube and the second main power tube of the inverter circuit, and the output end of the OR gate is connected to one end of the capacitor C2; the other end of the capacitor C2 is connected to one end of the resistor R2, the cathode of the diode D2, and the input end HI of the driving module, and the other end of the resistor R2 and the anode of the diode D2 are both grounded; the output first end VB of the driving module is connected to the anode of the diode D3, the cathode of the diode D3 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the output third end VS of the driving module, and then connected to the D pole of the clamping tube, and the output second end HO of the driving module is connected to the G pole of the clamping tube.

[0013] In a third aspect, a switching power supply is provided, comprising an inverter circuit, a transformer, a secondary rectifier circuit, a clamping capacitor, a main power inductor, a clamping tube and the active clamping circuit as described above, wherein the inverter circuit, the transformer and the secondary rectifier circuit are connected in sequence, the clamping tube is an NMOS tube, the S pole of the clamping tube is connected to one end of the main power inductor, the third end of the secondary rectifier circuit and the VBUS end of the bootstrap drive circuit, the G pole of the clamping tube is connected to the output end Y3 of the bootstrap drive circuit, the D pole of the clamping tube is connected to the first end of the clamping capacitor, the other end of the clamping capacitor and the fourth end of the secondary rectifier circuit are both grounded, and the other end of the main power inductor serves as the output end of the switching power supply.

[0014] Preferably, the D pole of the clamp tube is connected to the first end of the clamp capacitor through a surge resistor R1.

[0015] Compared with the prior art, the utility model has the following beneficial effects:

[0016] (1) The utility model samples the driving signal of the primary bridge arm of the switching power supply for logic processing, and then controls the on-time of the clamped Nmos tube driving signal through the pulse width limiting circuit, thereby controlling the clamped Nmos tube to be turned on before the secondary side VBUS stress spike arrives, effectively avoiding the problem of the previous active clamping circuit turning on the body diode of the clamping tube when a large current is injected, the conductivity modulation effect, and the generation of a higher conduction voltage drop at both ends of the diode, and well absorbing the voltage stress spike;

[0017] (2) By adjusting the RC parameters, the conduction time of the clamp tube can be changed, effectively reducing the loss of the active clamp circuit; this is conducive to improving the flexibility of switching power supply debugging;

[0018] (3) Changing from Pmos to Nmos clamping effectively solves the problem of selecting PMOS tubes with a withstand voltage of 200V and above; and the problem of small Pmos impact current, effectively improving the reliability of mos. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The waveform diagram of the Pmos tube and VBUS voltage using the traditional active clamping circuit in the prior art;

[0020] Figure 2 A circuit schematic diagram of the active clamping circuit applied to a switching power supply;

[0021] Figure 3 A control timing diagram of the active clamping circuit applied to a switching power supply;

[0022] Figure 4 Another circuit schematic diagram of the active clamping circuit applied to a switching power supply. DETAILED DESCRIPTION

[0023] The following is a more clear and complete description of the technical solution of the present utility model in conjunction with the accompanying drawings in the present embodiment. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0024] Any feature disclosed in this specification (including any abstract and drawings), unless otherwise stated, may be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

[0025] It should be noted that the terms "including" and "having" and any variations thereof described in the specification and claims of the present application are intended to cover non-exclusive inclusions. For example, the inclusion of a series of components or unit circuits is not necessarily limited to those components or unit circuits explicitly listed, but may include components or unit circuits that are not explicitly listed or inherent to these circuits.

[0026] Figure 2 The figure shows a circuit schematic diagram of the active clamping circuit of the present embodiment applied to a switching power supply. In the present embodiment, an active clamping circuit is provided, which is applied to a switching power supply. The switching power supply includes an inverter circuit, a transformer, a secondary rectifier circuit, a clamping capacitor C200, a main power inductor L1, and a clamping tube TR20. The clamping tube TR20 is an NMOS tube. The active clamping circuit includes: a signal selection and processing circuit, a pulse width limiting circuit, and a bootstrap driving circuit connected in sequence. The bootstrap driving circuit includes a driving module, a capacitor C3, and a diode D3. The input terminal HI of the driving module is connected to the output terminal of the pulse width limiting circuit. The output first terminal VB of the driving module is connected to the anode of the diode D3. The cathode of the diode D3 is connected to one end of the capacitor C3. The other end of the capacitor C3 is connected to the output third terminal VS of the driving module and then connected to the D pole of the clamping tube. The output second terminal HO of the driving module is connected to the G pole of the clamping tube.

[0027] The pulse width limiting circuit comprises a resistor R2, a diode D2 and a capacitor C2, one end of the capacitor C2 is used as an input end of the pulse width limiting circuit, and is connected to the output end of the signal selection and processing circuit, the other end of the capacitor C2 is connected to one end of the resistor R2 and the cathode of the diode D2, and then is used as the output end of the pulse width limiting circuit and is connected to the input end HI of the bootstrap driving circuit, and the other end of the resistor R2 and the anode of the diode D2 are both grounded;

[0028] The signal selection and processing circuit is used to access the driving signals of the first main power tube and the second main power tube on the primary side of the switching power supply, and output a first level signal when the driving signal meets the preset conditions. The first level signal is pulse-width limited by the pulse width limiting circuit, and then bootstrapped by the bootstrap driving circuit to output a pulse signal to the active clamping circuit of the switching power supply to drive the clamping MOS tube to turn on.

[0029] Specifically, the schematic diagram of the switching power supply is as follows Figure 2 As shown, the inverter circuit, transformer, secondary side rectifier circuit, clamp capacitor C200, main power inductor L1, clamp tube TR20 and the active clamp circuit as described above are connected in sequence. The S pole of the clamp MOS tube TR20 is connected to one end of the main power inductor L1 and the third end of the secondary side rectifier circuit. The G pole of the clamp tube TR20 is connected to the output end Y3 of the bootstrap drive circuit. The D pole of the clamp tube TR20 is connected to the first end of the clamp capacitor C200. The other end of the clamp capacitor and the fourth end of the secondary side rectifier circuit are both grounded. The other end of the main power inductor serves as the output end of the switching power supply.

[0030] Specifically, the inverter circuit may be a full-bridge circuit, including MOS transistors TR21, TR22, TR23, and TR24, and the secondary rectifier circuit includes MOS transistors TR1, TR2, TR3, and TR4. The specific connection relationship between each component in the inverter circuit and the secondary rectifier circuit and other components is as follows: Figure 2 As shown, no further details are given here; the inverter circuit can also be a half-bridge circuit, including a MOS tube TR22 and a MOS tube TR24 (not shown in the figure); wherein the first main power tube of the primary side of the switching power supply connected to the signal selection and processing circuit is the MOS tube TR22, and the second main power tube is the MOS tube TR24.

[0031] In this embodiment, the signal selection and processing circuit is an OR gate, and the first input terminal A and the second input terminal B of the OR gate are respectively used to access the driving signals of the first main power tube and the second main power tube of the primary side of the switching power supply; when the driving signal meets the preset conditions, the signal selection and processing circuit outputs a first level signal, specifically including:

[0032] When any driving signal of the first main power tube and the second main power tube is at a high level, a first level signal of a high level is output.

[0033] In the specific implementation process, the OR gate is connected to the drive signal HSG of the first main power tube and the drive signal LSG of the second main power tube through an isolation device UA. Taking the inverter circuit as a full-bridge circuit as an example, the A input terminal and the B input terminal of the isolation device UA are respectively connected to the drive signal HSG of the primary MOS tube TR22 of the full-bridge circuit and the drive signal LSG of the MOS tube TR24; the output terminals A1 and B2 of the isolation device UA are respectively connected to the input terminals A and B of the OR gate U1.

[0034] In this embodiment, the bootstrap driving circuit includes a driving module, a capacitor C3, and a diode D3. The input terminal HI of the driving module is connected to the output terminal of the pulse width limiting circuit, the output first terminal VB is connected to the anode of the diode D3, the cathode of the diode D3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the output third terminal VS of the driving module. The VBUS terminal of the bootstrap driving circuit is connected to the D pole of the clamping tube TR20, and the output second terminal HO of the driving module is connected to the G pole of the clamping tube TR20 as the output terminal Y3 of the bootstrap driving circuit.

[0035] Taking the inverter circuit as a full-bridge circuit as an example, the working principle of the above specific implementation method is analyzed as follows:

[0036] like Figure 3 The control timing diagram of this embodiment is shown. When the driving signals HSG and LSG of the lower MOS tubes of the two bridge arms of the primary side of the full-bridge circuit are at a high level, the driving signals are sent to the OR gate through the isolation device UA for logic judgment. According to the truth table of the OR gate, when any input is at a high level, the output of the OR gate is at a high level, that is, at this time, the output Y1 signal (the first level signal in this embodiment) of the OR gate is at a high level; after the Y1 signal passes through the differential circuit composed of the resistor R2 and the capacitor C2, only the transient waveforms of the rising and falling edges of the Y1 signal are obtained. , while the constant part has no output and is clamped by diode D2, clamping the level of the falling edge transient waveform of the Y1 signal to the conduction voltage drop of diode D2. The sharp pulse falling slope of the output Y2 signal is related to the time constant of resistor R2 and capacitor C2. Adjusting the parameters of resistor R2 and capacitor C2 can adjust the sharp pulse falling slope of the Y2 signal. This sharp pulse waveform passes through the bootstrap drive circuit to obtain a width-adjustable square wave Y3, and its pulse width t2 can be changed by adjusting the parameters of resistor R2 and capacitor C2. The amplitude of the high-level signal is defined as V H , the threshold voltage determined by the driver module is V L ,Right now The Y3 signal cooperates with the VS terminal to control the clamping tube TR20. When the positive pulse of the Y3 signal arrives, the clamping tube TR20 is turned on, thereby absorbing the voltage stress peak of the secondary rectifier circuit VBUS.

[0037] Preferably, by controlling the pulse to be generated at a certain moment before the voltage stress spike is generated on the secondary side VBUS, the clamping tube TR20 is turned on in advance, so that a high-speed and large current flows through the drain-source conductive channel of the clamping tube, which can effectively avoid the stress spike from charging the clamping capacitor C200 and generating a large voltage drop on the body diode of the clamping tube TR20, thereby causing a higher stress spike; and the pulse width limiting module can ensure that the control timing of the clamping tube does not affect the normal working mode of the power stage circuit, and can realize the release of the energy on the absorption capacitor to the output end during the demagnetization stage of the main power inductor, thereby realizing lossless absorption.

[0038] like Figure 4 , which is another principle diagram of the active clamping circuit described in this embodiment applied to a switching power supply. In this embodiment, the D pole of the clamping tube TR20 is connected to the first end of the clamping capacitor through a surge resistor R1.

[0039] Preferably, the addition of the surge resistor R1 reduces the high-speed and large current accordingly after passing through the surge resistor, thereby effectively improving the loss of the clamping MOS tube and the clamping capacitor, and avoiding the problem of the clamping MOS tube being damaged due to the high-speed and large current.

[0040] The above are only preferred embodiments of the present invention, and those skilled in the art to which the present invention belongs may also make changes and modifications to the above specific embodiments. Therefore, the present invention is not limited to the specific control methods disclosed and described above, and some modifications and changes to the present invention should also fall within the scope of protection of the claims of the present invention. In addition, although some specific terms are used in this specification, these terms are only for the convenience of description and do not constitute any limitation to the present invention.

Claims

1. An active clamping circuit, applied to a switching power supply, the switching power supply comprising an inverter circuit, a transformer, a secondary rectifier circuit, a clamping capacitor, a main power inductor, and a clamping tube; characterized in that: The clamping tube is an NMOS tube, and the active clamping circuit includes: a signal selection and processing circuit, a pulse width limiting circuit, and a bootstrap driving circuit connected in sequence; the bootstrap driving circuit includes a driving module, a capacitor C3, and a diode D3, the input end HI of the driving module is connected to the output end of the pulse width limiting circuit, the output first end VB of the driving module is connected to the anode of the diode D3, the cathode of the diode D3 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the output third end VS of the driving module, and is used to be connected to the D pole of the clamping tube, and the output second end HO of the driving module is connected to the G pole of the clamping tube; The signal selection and processing circuit is used to access the drive signals of the first main power tube and the second main power tube of the inverter circuit, and output a first level signal when the drive signal meets the preset conditions. The first level signal is pulse-width limited by the pulse width limiting circuit, and then bootstrapped by the bootstrap driving circuit to output a pulse signal to the clamp tube to drive the clamp tube to conduct.

2. The active clamping circuit according to claim 1, characterized in that: The pulse width limiting circuit includes a resistor R2, a diode D2 and a capacitor C2. One end of the capacitor C2 serves as the input end of the pulse width limiting circuit and is connected to the output end of the signal selection and processing circuit. The other end of the capacitor C2 is connected to one end of the resistor R2 and the cathode of the diode D2, and then serves as the output end of the pulse width limiting circuit and is connected to the input end of the bootstrap drive circuit. The other end of the resistor R2 and the anode of the diode D2 are both grounded.

3. The active clamping circuit according to claim 1, characterized in that: The signal selection and processing circuit is an OR gate, and the first input terminal and the second input terminal of the OR gate are respectively used to access the driving signals of the first main power tube and the second main power tube of the inverter circuit; when the driving signal meets the preset conditions, the signal selection and processing circuit outputs a first level signal, specifically including: When any driving signal of the first main power tube and the second main power tube is at a high level, a first level signal of a high level is output.

4. An active clamping circuit, applied to a switching power supply, the switching power supply comprising an inverter circuit, a transformer, a secondary rectifier circuit, a clamping capacitor, a main power inductor, and a clamping tube; characterized in that: The clamping tube is an NMOS tube, and the active clamping circuit includes: a signal selection and processing circuit, a pulse width limiting circuit, and a bootstrap driving circuit connected in sequence; the signal selection and processing circuit is an OR gate; the pulse width limiting circuit includes a resistor R2, a diode D2, and a capacitor C2; the bootstrap driving circuit includes a driving module, a capacitor C3, and a diode D3; The first input end and the second input end of the OR gate are respectively used to access the driving signals of the first main power tube and the second main power tube of the inverter circuit, and the output end of the OR gate is connected to one end of the capacitor C2; the other end of the capacitor C2 is connected to one end of the resistor R2, the cathode of the diode D2, and the input end HI of the driving module, and the other end of the resistor R2 and the anode of the diode D2 are both grounded; the output first end VB of the driving module is connected to the anode of the diode D3, the cathode of the diode D3 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the output third end VS of the driving module, and then connected to the D pole of the clamping tube, and the output second end HO of the driving module is connected to the G pole of the clamping tube.

5. A switching power supply, characterized in that: The invention comprises an inverter circuit, a transformer, a secondary rectifier circuit, a clamping capacitor, a main power inductor, a clamping tube and an active clamping circuit as described in any one of claims 1 to 4, wherein the inverter circuit, the transformer and the secondary rectifier circuit are connected in sequence, the clamping tube is an NMOS tube, the S pole of the clamping tube is connected to one end of the main power inductor, the third end of the secondary rectifier circuit and the VBUS end of the bootstrap drive circuit, the G pole of the clamping tube is connected to the output end Y3 of the bootstrap drive circuit, the D pole of the clamping tube is connected to the first end of the clamping capacitor, the other end of the clamping capacitor and the fourth end of the secondary rectifier circuit are both grounded, and the other end of the main power inductor serves as the output end of the switching power supply.

6. The switching power supply according to claim 5, characterized in that: The D pole of the clamp tube is connected to the first end of the clamp capacitor through a surge resistor R1.

Images