Packaging structure, quantum processor and quantum computer

Abstract

The utility model discloses a packaging structure, a quantum processor and a quantum computer, and belongs to the field of superconducting quantum chip manufacturing. The packaging structure comprises: a superconducting quantum chip having a ground surface and a plurality of signal ports located in a peripheral area; the substrate is used for bearing superconducting quantum, and a first connecting layer and a second connecting layer are arranged in an area close to the superconducting quantum chip; wherein the first connecting layer and the second connecting layer are alternately provided with a plurality of first bonding pads and a plurality of second bonding pads; the connecting piece is provided with a plurality of first connecting wires for electrically connecting the first bonding pads with the signal ports one by one, and a plurality of second connecting wires for electrically connecting the second bonding pads with the ground surface; wherein in the thickness direction of the superconducting quantum chip, the superconducting quantum chip, the first connecting layer and the second connecting layer are in a stepped form in sequence. Through the above mode, the structure of the utility model is beneficial to signal transmission and crosstalk reduction, and the bonding is regular and the space is large, so that an automatic bonding machine can be used, and time and labor are saved.

Description

Technical Field

[0001] The present application belongs to the technical field of superconducting quantum chip manufacturing, and in particular, relates to a packaging structure, a quantum processor and a quantum computer. Background Art

[0002] For superconducting quantum chips, they need to be initialized with control signals and their signals need to be led out. Packaging is often chosen to enable lead connection between the superconducting quantum chip and substrate structures such as printed circuit boards outside the chip. For this purpose, structures such as signal ports that participate in lead connection are often set at the end of the superconducting quantum chip circuit, and the signal ports and the chip's external substrate are respectively connected by telecommunications at both ends of the wire, thereby achieving the purpose of signal transmission between the superconducting quantum chip and the external structure.

[0003] At present, as the number of bits in superconducting quantum chips increases, the number of signal control lines required also increases. Among these signal control lines, high-frequency signal lines account for nearly half, and in order to reduce losses, ground wires must be bonded on both sides of the high-frequency signal lines, and ground wires must also be bonded between adjacent high-frequency signal lines to improve isolation between channels and reduce signal crosstalk.

[0004] However, it is very difficult to lead out numerous control lines and connect external devices and / or bond ground wires on a smaller superconducting quantum chip. In the current packaging structure, the chip's signal port does not correspond to the pads of the substrate outside the chip, so that the bonding wires connecting the chip and the substrate are at a certain angle to the chip boundary (i.e., not completely perpendicular). This will make it difficult to have space between the pads for bonding ground wires, which is obviously not conducive to signal transmission and reducing crosstalk between wires. In addition, due to the small space, the bonding wires cannot be bonded using an automatic bonding machine, which undoubtedly increases the difficulty of manufacturing and processing the package. Utility Model Content

[0005] The purpose of the present application is to provide a packaging structure, a quantum processor and a quantum computer to solve the problem that the bonding wire connecting the chip and the substrate has a certain oblique angle with the chip boundary in the prior art, resulting in that it is difficult to have space between the pads for bonding the ground wire, which is not conducive to signal transmission and reducing the crosstalk between the wires, and the problem that it is time-consuming and labor-intensive because an automatic bonding machine cannot be used. A first connection layer and a second connection layer are arranged in an area of ​​the substrate close to the superconducting quantum chip, and the superconducting quantum chip, the first connection layer and the second connection layer are arranged in a stepped manner in sequence, so that the packaging space can be arranged more reasonably, so that there is space between the pads of the packaging structure to bond the ground wire, which is conducive to signal transmission and reducing the crosstalk between the wires. The wiring of the packaging structure is regular and has a large space, so an automatic bonding machine can be used, saving time and labor.

[0006] In order to solve the above technical problems, the utility model provides a packaging structure, including: a superconducting quantum chip, having a ground surface and a plurality of signal ports located in the peripheral area;

[0007] A substrate for carrying superconducting quantum chips, wherein a first connection layer and a second connection layer are arranged in an area close to the superconducting quantum chip; wherein the first connection layer and the second connection layer are both alternately provided with a plurality of first pads and a plurality of second pads;

[0008] A connector, comprising a plurality of first connection lines electrically connecting the first pads to the signal ports one by one, and a plurality of second connection lines electrically connecting the second pads to the ground surface;

[0009] Wherein, in the thickness direction of the superconducting quantum chip, the superconducting quantum chip, the first connecting layer and the second connecting layer are sequentially stepped.

[0010] Preferably, there are a first row of signal ports and a second row of signal ports in parallel in the direction of the boundary line between the superconducting quantum chip and the first connecting layer;

[0011] The second row of signal ports is located between the first row of signal ports and the boundary line.

[0012] Preferably, in a direction parallel to the boundary line, the spacing between any two adjacent signal ports is the same;

[0013] In a direction parallel to the surface of the superconducting quantum chip and perpendicular to the boundary line, the first row of signal ports and the second row of signal ports are staggered in distribution.

[0014] Preferably, in a direction parallel to the surface of the superconducting quantum chip and perpendicular to the boundary line, the length of the first pad is greater than the length of the second pad.

[0015] Preferably, all the first pads in the first connection layer are connected to the ports in the first row of signal ports in a one-to-one correspondence.

[0016] All the first pads in the second connection layer are connected to the ports in the second row of signal ports in a one-to-one correspondence.

[0017] Preferably, the second connecting lines correspond to the second pads one by one, and any one of the second connecting lines includes two non-intersecting conductors, one end of the two conductors is electrically connected to the same second pad, and the other end is electrically connected to the ground plane.

[0018] Preferably, any one of the second connecting wires used to connect the second pad located on the first connecting layer and the ground surface, the ends of the two wires away from the second pad are respectively electrically connected to the ground surfaces on both sides of a corresponding second row signal port;

[0019] Any one of the second connecting wires used to connect the second pad located on the second connecting layer and the ground surface, wherein one end of the two wires away from the second pad is electrically connected to the ground surfaces on both sides of a corresponding first row signal port;

[0020] And / or, in a direction perpendicular to the superconducting quantum chip, adjacent second connecting lines cross each other in a non-contact manner.

[0021] Preferably, the material of the connecting piece is gold or aluminum;

[0022] The first connecting line is perpendicular to a boundary line between the superconducting quantum chip and the first connecting layer.

[0023] The present application also provides a quantum processor, comprising: a box;

[0024] The packaging structure described in any of the above items;

[0025] Wherein, the packaging structure is installed in the box body.

[0026] The present application also provides a quantum computer, characterized in that it includes: the quantum processor described above.

[0027] Compared with the prior art, the present application provides a packaging structure, that is, a first connection layer and a second connection layer are arranged in an area of ​​the substrate close to the superconducting quantum chip, and the superconducting quantum chip, the first connection layer and the second connection layer are arranged in a step-by-step manner in sequence, so that the packaging space can be arranged more reasonably, so that there is space for bonding the ground wire, which is beneficial to signal transmission and reducing crosstalk between wires. In addition, the packaging structure has regular wiring and a large space, and an automatic bonding machine can be used, saving time and effort. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 An overall schematic diagram of the packaging structure provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a portion of the packaging structure provided in an embodiment of the present application (step-by-step);

[0030] Figure 3 A schematic diagram of a packaging structure provided in an embodiment of the present application having one side of a superconducting quantum chip;

[0031] Figure 4 A schematic diagram of the signal port and pad configuration provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the connection between the signal port and the pad provided in an embodiment of the present application.

[0033] Explanation of the reference numerals: 1 - superconducting quantum chip, 11 - ground surface, 12 - signal port, 2 - substrate, 21 - first connection layer, 22 - second connection layer, 23 - first pad, 24 - second pad, 3 - connector, 31 - first connection line, 32 - second connection line, 4 - boundary line. DETAILED DESCRIPTION

[0034] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0035] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0037] There is a description of the structure of a superconducting quantum chip, in which the core component is the bit. In order to realize the information input and output accompanying the bit test, the bit is generally introduced or led out to the edge of the superconducting quantum chip through various transmission lines, and then through connection structures such as signal ports set at the peripheral position of the chip, and finally through leads and other means to connect to structures such as pads of the substrate outside the chip.

[0038] For previous superconducting quantum chips, the number of bits they carried was relatively small, and the requirements for the number of chip ports, leads, and pads were also relatively small, so that these devices occupied a very small space in the entire superconducting quantum chip packaging structure, and they could be arranged at will to achieve their transmission and other functions. However, now or in the future, with the development of superconducting quantum chips, the number of bits carried will gradually increase with the progress of technology and science. When the number of bits increases to a certain number, the number of chip ports, leads and pads set up with the bits will increase, so that the space of the chip packaging structure is no longer sufficient to support the arbitrary arrangement of these structures; or, in some packaging environments, there are a high proportion of high-frequency signals in the control lines of the bits, such as: xy control lines and bus buses (frequency greater than 1Ghz, such as 4-6GHz), and some low-frequency signals, such as: z lines (such as below 500MHz), where ground wires must be bonded on both sides of the high-frequency signal transmission lines to reduce losses, and ground wires must be bonded between the high-frequency signal transmission lines to improve the isolation between channels, thereby reducing signal crosstalk; in this regard, it is relatively difficult or difficult to achieve to complete packaging bonding on smaller chips and meet the above requirements for current processes.

[0039] It can be seen from this that when a quantum chip is designed to include a large number of quantum bits, how to reasonably configure the positions of these necessary leads, pads, and ports is a problem that needs to be considered at present.

[0040] For some current manufacturing processes, many control lines or signal pins are brought out on a smaller chip and connected to external instruments and equipment. The more mature and less difficult process is wire bonding. However, in current packaging, since the positions of the chip port and the chip's external substrate pad are not one-to-one corresponding, the bonding wire between the chip port and the external substrate pad has a certain inclination angle (not completely vertical) to the chip boundary, which will make it difficult for some pads to have space to bond the ground wire, which is not conducive to signal transmission and reducing crosstalk between lines. In addition, the small space and irregular wiring will also make it impossible to use automatic bonding machines in the production process, which is time-consuming, labor-intensive and inefficient.

[0041] The above situation is sufficient to illustrate that the increase in the number of quantum bits has led to tight space for the layout of transmission lines and pads, and the increase cannot be simply solved by increasing the chip size because the chip size is limited by the processing size of the wafer. Therefore, the above situation has greatly restricted the future development of multi-bit superconducting quantum chips.

[0042] In response to the current problems, in this application, the inventors have proposed a new solution that can arrange the packaging space more reasonably, so that there is space for bonding the ground wire, which is conducive to signal transmission and reduces crosstalk between wires. The packaging structure has regular wiring and a larger space, and can use an automatic bonding machine, saving time and effort.

[0043] Please refer to Figure 1 and Figure 3 The present application provides a packaging structure, comprising a superconducting quantum chip 1 and a substrate 2 for placing the superconducting quantum chip 1, wherein the superconducting quantum chip 1 is located at a relatively central portion of a surface of the substrate 2, that is, the center point of the superconducting quantum chip 1 coincides with the center point of the substrate 2, or the distances between the edges of the superconducting quantum chip 1 and the edges of the substrate 2 tend to be equal; and a ground plane and a plurality of signal ports 12 in the peripheral area of ​​the surface are arranged on the surface of the superconducting quantum chip 1 away from the substrate 2; wherein the bits in the superconducting quantum chip 1 transmit signals to the signal port 12 through structures such as leads, thereby realizing a partial path for information exchange between the superconducting quantum chip 1 and an external mechanism; in order to complete its path For the substrate 2 for carrying the superconducting quantum chip 1, a first connection layer 21 and a second connection layer 22 are arranged in a region close to the superconducting quantum chip 1, and a plurality of first pads 23 and a plurality of second pads 24 are arranged on the first connection layer 21 and the second connection layer 22; it is worth noting that in order to bond the ground wire so that it has space and is arranged in accordance with requirements, the first pads 23 and the second pads 24 are alternately arranged one by one, wherein the first pads 23 are used to be electrically connected to the above-mentioned signal port 12 to transmit signals, and the second pads 24 are used to be electrically connected to the ground surface 11 to realize the grounding function, thereby reducing energy loss, improving isolation between channels, and reducing signal crosstalk between lines. For the connection between the first pad 23, the second pad 24, the signal port 12 and the ground surface 11, a connecting member 3 is provided, such as a first connecting wire 31 and a second connecting wire 32; wherein there are multiple first connecting wires 31, which connect the first pad 23 and the signal port 12 one by one to realize the signal exchange function between the two, and there are multiple second connecting wires 32, which electrically connect the second pad 24 and the ground surface 11 to realize the wire bonding grounding. It is worth noting that please refer to Figure 2 In the thickness direction of the superconducting quantum chip 1, the superconducting quantum chip 1, the first connection layer 21 and the second connection layer 22 are sequentially stepped, such as: step-up, or it can be interpreted that, in the direction from the substrate 2 to the superconducting quantum chip 1, the first connection layer 21 is higher than the surface of the superconducting quantum chip 1 away from the substrate 2, and the first connection layer 21 is lower than the second connection layer 22.

[0044] Please refer to Figure 4In one embodiment of the present application, the superconducting quantum chip 1 is positioned at the boundary line 4 between the first connection layer 21, and in the direction in which the superconducting quantum chip 1 is away from the substrate 2 and parallel to the boundary line 4, the first row of signal ports 12 and the second row of signal ports 12 are arranged at the peripheral position of the superconducting quantum chip 1, and the second row of signal ports 12 are located between the first row of signal ports 12 and the boundary line 4; wherein the first signal port 12 and the second signal port 12 are both arranged close to the edge region of the superconducting quantum chip 1.

[0045] Furthermore, in the direction parallel to the boundary line 4, the spacing between any two adjacent signal ports 12 in the first row of signal ports 12 and the second row of signal ports 12 is the same (see Figure 4 For the portion of the signal ports 12 below the middle boundary line 4, for the first row of signal ports 12 and / or the second row of signal ports 12, the spacing between any two model ports 12 in the same row is equal to the spacing between N (N is any positive integer) adjacent signal ports 12, where adjacent signal ports 12 can be arbitrarily selected in the same row), which is specifically manifested as a uniform arrangement. This setting is conducive to saving space and parameter setting of the automatic bonding machine.

[0046] In addition, in a direction parallel to the surface of the superconducting quantum chip 1 and perpendicular to the boundary line 4, the first row of signal ports 12 and the second row of signal ports 12 are staggered, that is, the first row of signal ports 12 are perpendicular to the boundary line and the bonding wires to the first pads 23 in the first connection layer 21 or the second connection layer 22 can directly pass between the two signal ports 12 of the second row of signal ports 12 without intersecting or contacting them.

[0047] It is worth noting that the first pad 23 is used to connect to the first signal port 12 or the second signal port 12 (power on, signal on) to realize signal exchange, and the second pad 24 is used to connect to the ground surface 11 of the superconducting quantum chip 1 (power on) to realize indirect grounding of the transmission line, but the material of the first pad 23 and the second pad 24 is essentially the same. Therefore, in order to distinguish the two and prevent misconnection, the length of the first pad 23 is greater than the length of the second pad 24 in a direction parallel to the surface of the superconducting quantum chip 1 and perpendicular to the boundary line 4. For example, at one end close to the superconducting quantum chip 1, the second pad 24 is 0.1 mm shorter than the first pad 23 (please refer again Figure 4 , the first pad 23 and the second pad 24 are on the surface of the corresponding first connection layer 21 or the second connection layer 22 and in the direction perpendicular to the junction line 4, the first pad 23 is longer than the second pad 24, and the ends of the first pad 23 and the second pad 24 away from the junction line 4 are both against the boundary of the corresponding connection layer away from the junction line 4).

[0048] Please refer to Figure 5, the connection relationship between the connector 3 and each signal port 12 or pad or ground surface 11 is not arbitrary or purposeless, but has basic arrangement requirements; in one embodiment of the present application, all the first pads 23 in the first connection layer 21 are connected to each port in the first row of signal ports 12 in a one-to-one correspondence; all the first pads 23 in the second connection layer 22 are connected to each port in the second row of signal ports 12 in a one-to-one correspondence; the above "one-to-one correspondence" can be interpreted as: the straight connection line between the one-to-one corresponding first pads 23 in the first connection layer 21 and the first row of signal ports 12 is perpendicular to the boundary line, and the straight connection line between the one-to-one corresponding first pads 23 in the second connection layer 22 and the second row of signal ports 12 is perpendicular to the boundary line, so that this packaging structure can use an automatic bonding machine when being manufactured to improve manufacturing efficiency.

[0049] Furthermore, each second connecting line 32 corresponds one-to-one to the second solder pad 24, and it can be understood that one end of each second connecting line 32 is electrically connected to only one corresponding second solder pad 24; and, in order to make the connection more reliable, the second connecting line 32 includes two non-intersecting wires, one end of which is electrically connected to the same second solder pad 24, and the other end is electrically connected to the ground surface 11; this setting can reduce transmission loss, and can also improve the isolation between signal channels and reduce signal crosstalk between signal transmission lines. The signal transmission line can be understood here as the first connecting line 31.

[0050] Please refer again Figure 5 , part of the second connecting line 32, one end of which is connected to the second pad 24 of the first connecting layer 21, and the other end of which is connected to the ground surface 11. It is worth noting that the second connecting line 32 includes two non-intersecting wires, and one end of the two wires away from the second pad 24 is separated and electrically connected to the ground surface 11 on both sides of a signal port 12 in the corresponding second row of signal ports 12.

[0051] Furthermore, another part of the second connecting line 32 has one end connected to the second solder pad 24 of the second connecting layer 22, and the other end connected to the ground surface 11. It is worth noting that this second connecting line 32 also includes two non-intersecting wires, and one end of the two wires away from the second solder pad 24 is separated and electrically connected to the ground surface 11 on both sides of a signal port 12 in the corresponding first row of signal ports 12.

[0052] Furthermore, the vertical projections of adjacent or any other plurality of second connecting lines 32 on the surface of the superconducting quantum chip 1 have a probability of intersecting. In one embodiment of the present application, two conductors of two adjacent second connecting lines 32 are in a non-contact intersection state, thereby avoiding contact and causing signal interference between the lines.

[0053] In one embodiment of the present application, the material of the connector 3 is a metal material such as gold or aluminum to achieve functions such as signal transmission and current path. In addition, the first connecting line 31 is perpendicular to the boundary line 4 between the superconducting quantum chip 1 and the first connecting layer 21. This setting is to meet the working requirements of the automatic bonding machine, that is, wiring rules; it can improve manufacturing efficiency and save time.

[0054] The embodiment of the present application also provides a quantum processor, including the aforementioned packaging structure and a box body for loading the packaging structure, wherein the packaging structure with the superconducting quantum chip is installed in the box body, and then signals are exchanged with external equipment through a signal transmission channel of the box body to realize its computing function, which will not be described in detail here.

[0055] The embodiments of the present application also provide a quantum computer, including the aforementioned quantum processor, with reference to existing quantum computers and other embodiments of the present application, which will not be described in detail here.

[0056] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "specific example" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0057] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.

Claims

1. A packaging structure, characterized in that: include: A superconducting quantum chip (1) has a ground surface (11) and a plurality of signal ports (12) located in a peripheral region; A substrate (2) for carrying a superconducting quantum chip, wherein a first connection layer (21) and a second connection layer (22) are arranged in a region close to the superconducting quantum chip (1); wherein the first connection layer (21) and the second connection layer (22) are both alternately provided with a plurality of first pads (23) and a plurality of second pads (24); A connecting member (3) having a plurality of first connecting wires (31) for electrically connecting the first pads (23) and the signal ports (12) one by one, and a plurality of second connecting wires (32) for electrically connecting the second pads (24) and the ground surface (11); Wherein, in the thickness direction of the superconducting quantum chip (1), the superconducting quantum chip (1), the first connecting layer (21) and the second connecting layer (22) are sequentially arranged in a stepped manner.

2. The packaging structure according to claim 1, characterized in that: There are parallel first row signal ports (12) and second row signal ports (12) in the direction of the boundary line (4) between the superconducting quantum chip (1) and the first connection layer (21); The second row of signal ports (12) is located between the first row of signal ports (12) and the boundary line (4).

3. The packaging structure according to claim 2, characterized in that: In a direction parallel to the boundary line (4), the spacing between any two adjacent signal ports (12) is the same; In a direction parallel to the surface of the superconducting quantum chip (1) and perpendicular to the boundary line (4), the first row of signal ports (12) and the second row of signal ports (12) are staggered in distribution.

4. The packaging structure according to claim 2, characterized in that: In a direction parallel to the surface of the superconducting quantum chip (1) and perpendicular to the boundary line (4), the length of the first pad (23) is greater than the length of the second pad (24).

5. The packaging structure according to claim 2, characterized in that: All the first pads (23) in the first connection layer (21) are connected to the ports in the first row of signal ports (12) in a one-to-one correspondence; All the first pads (23) in the second connection layer (22) are connected to each port in the second row of signal ports (12) in a one-to-one correspondence.

6. The packaging structure according to claim 2, characterized in that: The second connecting lines (32) correspond to the second soldering pads (24) one by one, and any one of the second connecting lines (32) comprises two non-intersecting conductive wires, one end of the two conductive wires is electrically connected to the same second soldering pad (24), and the other end is electrically connected to the ground plane.

7. The packaging structure according to claim 6, characterized in that: Any one of the second connecting wires (32) for connecting the second pad (24) located on the first connecting layer (21) and the ground surface (11), wherein one end of the two wires away from the second pad (24) is electrically connected to the ground surface (11) on both sides of a corresponding second row signal port (12); Any one of the second connecting wires (32) for connecting the second pad (24) located on the second connecting layer (22) and the ground surface (11), wherein one end of the two wires away from the second pad (24) is electrically connected to the ground surface (11) on both sides of a corresponding first row signal port (12); And / or, in a direction perpendicular to the superconducting quantum chip (1), adjacent second connecting lines (32) cross each other in a non-contact manner.

8. The packaging structure according to claim 1, characterized in that: The material of the connecting piece (3) is gold or aluminum; The first connecting line (31) is perpendicular to a boundary line (4) between the superconducting quantum chip (1) and the first connecting layer (21).

9. A quantum processor, characterized in that: include: Box body; The packaging structure according to any one of claims 1 to 8; Wherein, the packaging structure is installed in the box body.

10. A quantum computer, characterized in that: include: The quantum processor of claim 9.

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