Embedded key logic implementation circuit

Abstract

The utility model discloses an embedded key logic implementation circuit, which relates to the field of key control and comprises a first switch SW1, a second switch SW2 and a third switch SW3, and the first switch SW1 and the second switch SW2 are connected in parallel. According to the embedded key logic implementation circuit, the product cost is reduced by reducing product structure, circuit and process negative complexity, improving design and research and development efficiency, shortening the research and development period, reducing the number of keys and auxiliary circuits for the keys and reducing consumption of electronic elements, connection with a controller can be achieved only through at least one IO, and the embedded key logic implementation circuit is simple in structure, convenient to use and high in practicability. The interface resource demand of the controller is reduced, more controller models can be selected, software only needs fewer resources to judge the key state change, the software overhead when no key is pressed down is reduced, the software efficiency is improved, meanwhile, input data can only be selected in an effective range, the problem of system abnormity caused by input of invalid data is avoided, and the user experience is improved. The product stability is improved.

Description

Technical Field

[0001] The utility model relates to a key control technology, in particular to an embedded key logic realization circuit. Background Art

[0002] With the development of microelectronics technology, embedded products are becoming more and more common. The most common input device for electronic products is the keyboard or keypad. However, due to the limited functional units and hardware resources of embedded devices, they do not need and cannot implement computer-like keyboard input. Usually, a few keys are used to implement all key input functions of the product. For most embedded products, key input is an indispensable part, but the number of times it is used in the life cycle of the device is very few, or even only once or twice.

[0003] Some devices that need to input numbers need to support numeric keys from 0 to 9 and other function keys. Some numeric keys may not be used throughout the life cycle of the device, but the product's functional requirements require these keys. The connection between these keys and the controller also requires corresponding auxiliary circuits. The complex key design in embedded products has the following defects: (1) Increase the complexity of product design, including the complexity of structure, circuit design, and process. (2) Increase the cost of the product. Both the key itself and the auxiliary circuit required by the key require corresponding cost investment. (3) Waste software resources. Duplicate key design requires more software resources to determine and process the input status of the key, but the actual frequency of use of the key is extremely low, which greatly wastes controller resources. (4) Complex key design may input some unknown states that cannot be processed, causing the product to work abnormally. Utility Model Content

[0004] The purpose of the utility model is to provide an embedded key logic implementation circuit to solve the above-mentioned deficiencies in the prior art.

[0005] In order to achieve the above-mentioned object, the utility model provides the following technical solutions: an embedded key logic implementation circuit, comprising a first switch SW1, a second switch SW2 and a third switch SW3, wherein the first switch SW1 is connected in parallel with the second switch SW2, the second switch SW2 and the third switch SW3 are connected in parallel, the first switch SW1, the second switch SW2 and the third switch SW3 are defined as an S key, an UP key and a DOWN key respectively, and the logic implementation circuit further comprises a controller IO:

[0006] Furthermore, the first switch SW1 is connected in series with a resistor R1, and the resistor R1 is grounded.

[0007] Furthermore, the second switch SW2 is connected in series with a resistor R2, and the resistor R2 is grounded.

[0008] Furthermore, the third switch SW3 is connected in series with a resistor R3, and the resistor R3 is grounded.

[0009] Further, the first switch SW1, the second switch SW2 and the third switch SW3 are all connected to the power supply terminal VCC through the pull-up resistor R0, and the controller IO is connected to the first switch SW1, the second switch SW2 and the third switch SW3.

[0010] Furthermore, the resistor R1, the resistor R2 and the resistor R3 have different resistance values.

[0011] Compared with the prior art, the utility model provides an embedded key logic implementation circuit, which improves design and development efficiency and shortens the development cycle by reducing the negative complexity of product structure, circuit and process. It reduces the number of keys and corresponding auxiliary circuits, reduces the consumption of electronic components, and reduces product cost. Only one IO is required to connect to the controller, reducing the resource requirements of the controller interface, making more controller models available. The software only needs fewer resources to judge the change of key status, reducing the software overhead when no key is pressed, and improving software efficiency. At the same time, input data can only be selected within the valid range, avoiding system abnormalities caused by inputting invalid data, and improving product stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present utility model. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0013] Figure 1 The present invention is a schematic diagram of the overall structure of an embodiment of the present invention. DETAILED DESCRIPTION

[0014] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0015] See also Figure 1 , an embedded key logic implementation circuit, including a first switch SW1, a second switch SW2 and a third switch SW3, the first switch SW1 is connected in parallel with the second switch SW2, the second switch SW2 and the third switch SW3 are connected in parallel, the first switch SW1, the second switch SW2 and the third switch SW3 are defined as an S key, an UP key and a DOWN key respectively, and the logic implementation circuit also includes a controller IO:

[0016] The first switch SW1 is serially connected to a resistor R1 , and the resistor R1 is grounded.

[0017] The second switch SW2 is connected in series with a resistor R2, and the resistor R2 is grounded.

[0018] The third switch SW3 is serially connected to a resistor R3 , and the resistor R3 is grounded.

[0019] The first switch SW1, the second switch SW2 and the third switch SW3 are all connected to the power supply terminal VCC through the pull-up resistor R0, and the controller 10 is connected to the first switch SW1, the second switch SW2 and the third switch SW3.

[0020] The resistors R1, R2, and R3 have different resistance values.

[0021] The pull-down resistor value connected to each button is different. When different buttons are pressed, the voltage value connected to one end of the controller is different. The controller determines the different button states by collecting the voltage on the analog IO.

[0022] The corresponding voltage calculation formula on IO when different buttons are pressed is as follows:

[0023]

[0024]

[0025] The detailed software processing process is as follows:

[0026] S1, if there is no button status update, exit the button processing logic. If there is a button status update, confirm the button status first to eliminate jitter. If the tracking status is confirmed, enter the button processing logic;

[0027] S2: If the button status after update is no button pressed (button released), and the previous button status (pre-release status) has been processed, then exit the button processing logic;

[0028] S3, if the state of the last key has not been processed, it is necessary to determine the state of the last key and select appropriate processing according to the state of the last key;

[0029] S4, if the previous key state is S key pressed, if the temporary data is data information, the temporary data is saved to the corresponding parameters according to the current state of the system, and the parameters are saved to the flash. The system state returns to the previous state;

[0030] S5, if the temporary data is the system state, then update the system state according to the temporary variable;

[0031] S6, if the previous key state is the UP key, and the temporary variable value is less than the maximum value, then the temporary variable value is increased by one;

[0032] S7, if the previous key state is the DOWN key, and the temporary variable value is greater than the minimum value, the grain variable value is reduced by one;

[0033] S8, if the previous key state is not a separate S, UP, or DOWN key, then enter the special processing of the key combination according to the system state. Different system states can independently define the functions and processing flows of different key combinations to meet more complex key requirements;

[0034] S9, if the button state is pressed after the status is updated in step 1, first determine whether the button pressing time reaches the long pressing time defined in the current state. If the long pressing time is not reached, return to step S1;

[0035] S10, if the key press time reaches the long press time defined in the current state, and the key pressed is the S key, enter the selected working state or confirm to save the data value;

[0036] S11, if the key press time reaches the long press time defined in the current state, and the key pressed is the UP key, the temporary data is the data value, and the time from the last temporary data is greater than the minimum interval, and the current temporary data value is less than the maximum value, the temporary data value is increased by one;

[0037] S12: If the key press time reaches the long press time defined in the current state, and the key pressed is the DOWN key, the temporary data is the data value, and the time from the last temporary data is greater than the minimum interval, the current temporary data value is greater than the minimum value, and the temporary data value is reduced by one.

[0038] The above only describes some exemplary embodiments of the present invention by way of illustration. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. An embedded key logic implementation circuit, characterized in that: It includes a first switch SW1, a second switch SW2 and a third switch SW3, the first switch SW1 is connected in parallel with the second switch SW2, the second switch SW2 and the third switch SW3 are connected in parallel, the first switch SW1, the second switch SW2 and the third switch SW3 are defined as an S key, an UP key and a DOWN key respectively, and the logic implementation circuit also includes a controller IO.

2. The embedded key logic implementation circuit according to claim 1, characterized in that: The first switch SW1 is connected in series with a resistor R1 , and the resistor R1 is grounded.

3. The embedded key logic implementation circuit according to claim 2, characterized in that: The second switch SW2 is connected in series with a resistor R2, and the resistor R2 is grounded.

4. The embedded key logic implementation circuit according to claim 3, characterized in that: The third switch SW3 is connected in series with a resistor R3, and the resistor R3 is grounded.

5. The embedded key logic implementation circuit according to claim 1, characterized in that: The first switch SW1, the second switch SW2 and the third switch SW3 are all connected to the power supply terminal VCC through the pull-up resistor R0, and the controller IO is connected to the first switch SW1, the second switch SW2 and the third switch SW3.

6. The embedded key logic implementation circuit according to claim 4, characterized in that: The resistors R1 , R2 and R3 have different resistance values.

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