Package substrate

Abstract

A package substrate includes a board body, a heterogeneous layer formed on the board body, a circuit structure formed on the heterogeneous layer, and then the board body is removed, so that the circuit layer of the circuit structure is not micro-etched during subsequent removal of the heterogeneous layer, and solder balls can be effectively bonded on the circuit layer in a subsequent process to avoid missing solder.

Description

Technical Field

[0001] The present application relates to a semiconductor packaging process, and more particularly to a packaging substrate capable of improving reliability. Background Art

[0002] With the rapid development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing towards high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] Figures 1A to 1F It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate 1 .

[0004] like Figure 1A As shown, a carrier 9 is provided, which has release layers 91 on two surfaces of a plate body 90 respectively, and a copper foil 92 is formed on the release layer 91 .

[0005] like Figure 1B As shown, a patterning process is performed on the copper foil 92 to form a first circuit layer 11 .

[0006] like Figure 1C As shown, a dielectric layer 12 is formed on the first circuit layer 11 , and a plurality of blind holes 120 are formed in the dielectric layer 12 .

[0007] like Figure 1D As shown, copper is electroplated on the dielectric layer 12 and in the blind hole 120 to form a second circuit layer 13 on the dielectric layer 12, and a plurality of conductive blind holes 14 electrically connecting the first circuit layer 11 and the second circuit layer 13 are formed in the blind hole 120 to form a coreless circuit structure 1a.

[0008] like Figure 1E As shown, the board 90 and the circuit structure 1 a are separated by the release layer 91 , and the copper foil 92 is retained on the dielectric layer 12 and the first circuit layer 11 .

[0009] like Figure 1F As shown, the copper foil 92 is removed by etching, and part of the material of the first circuit layer 11 is micro-etched to avoid short circuits caused by connection between adjacent circuits, thereby forming a plurality of grooves 15 on the dielectric layer 12 .

[0010] like Figure 1GAs shown, a solder mask 10 having a plurality of openings 100 is formed on opposite sides of the dielectric layer 12, so that a portion of the surface of the first circuit layer 11 and the second circuit layer 13 is exposed through the openings 100, so that an electronic device 3 can be connected to the first circuit layer 11 through a plurality of solder balls 16.

[0011] However, in the conventional package substrate 1, when the copper foil 92 is removed by etching, the first circuit layer 11 is also microetched, resulting in inconsistent depths D of the grooves 15, making it difficult to effectively combine all solder balls 16, and thus the reliability of the package substrate 1 is poor. For example, the depth of some grooves 15 is too deep, making it difficult for the solder balls 16 to combine with the first circuit layer 11, resulting in empty soldering or non-wetting problems.

[0012] Furthermore, since the first circuit layer 11 is also micro-etched when the copper foil 92 is removed by etching, part of the first circuit layer 11 may be undercut, causing the first circuit layer 11 to be damaged or even disconnected, thereby causing poor signal transmission between the first circuit layer 11 and the solder ball 16 .

[0013] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Utility Model Content

[0014] In view of the various deficiencies of the above-mentioned prior art, the present application provides a packaging substrate, comprising: a dielectric layer having a first surface and a second surface opposite to each other; a first circuit layer embedded in the first surface of the dielectric layer, wherein the first circuit layer is flush with the first surface of the dielectric layer; a heterogeneous layer formed on the first surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive blind vias formed in the dielectric layer and electrically connecting the first circuit layer and the second circuit layer.

[0015] The present application also provides a method for manufacturing a packaging substrate, including: providing a board having a heterogeneous layer thereon; forming a first circuit layer on the heterogeneous layer; forming a dielectric layer on the heterogeneous layer and the first circuit layer, and the dielectric layer is defined with a first surface and a second surface relative to each other so that the first surface of the dielectric layer is bonded to the heterogeneous layer; forming a second circuit layer on the second surface of the dielectric layer, and forming a plurality of conductive blind holes in the dielectric layer that electrically connect the first circuit layer and the second circuit layer; and removing the board.

[0016] In the aforementioned manufacturing method, a release layer is first formed on the plate, and then the heterogeneous layer is formed on the release layer.

[0017] The aforementioned manufacturing method further includes removing the heterogeneous layer.

[0018] In the aforementioned packaging substrate and its manufacturing method, the material forming the first circuit layer is different from the material forming the heterogeneous layer.

[0019] In the aforementioned packaging substrate and its manufacturing method, the heterogeneous layer is a conductive material other than a copper layer. For example, the conductive material is an anisotropic conductive film.

[0020] As can be seen from the above, the packaging substrate of the present application mainly adopts the configuration of the heterogeneous layer so that the first circuit layer will not be micro-etched when the heterogeneous layer is removed. Therefore, when the heterogeneous layer is removed, the thickness of the first circuit layer can be effectively controlled. Therefore, compared with the prior art, in the subsequent process of the present application, the solder balls can be effectively combined with the first circuit layer, thereby avoiding the problem of empty soldering or non-wetting, thereby improving reliability.

[0021] Furthermore, through the configuration of the heterogeneous layer, part of the material of the first circuit layer will not be removed when the heterogeneous layer is removed, thereby effectively preventing the first circuit layer from undergoing side corrosion. Therefore, compared to the prior art, the present application can avoid the problem of damage to the first circuit layer (such as disconnection) to improve the yield of signal transmission between the first circuit layer and the solder ball. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1A to 1G It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate.

[0023] Figures 2A to 2G It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present application.

[0024] Main component symbols

[0025] 1,2 Package substrate

[0026] 1a,2a Line structure

[0027] 10 Solder mask

[0028] 100,200 Opening

[0029] 11,21 First circuit layer

[0030] 12,22 Dielectric layer

[0031] 120,220 Blind holes

[0032] 13,23 Second circuit layer

[0033] 14,24 Conductive blind vias

[0034] 15 Grooves

[0035] 16 Solder balls

[0036] 20 Insulation protection layer

[0037] 22a First surface

[0038] 22b Second surface

[0039] 26 Conductive elements

[0040] 3 Electronic devices

[0041] 9 Bearing

[0042] 90 plate body

[0043] 91 Release layer

[0044] 92 Copper Foil

[0045] 93 Heterogeneous Layer

[0046] D Depth. DETAILED DESCRIPTION

[0047] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0048] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0049] Figures 2A to 2G It is a cross-sectional schematic diagram of a method for manufacturing the packaging substrate 2 of the present application.

[0050] like Figure 2A As shown, a carrier 9 is provided, wherein a release layer 91 is disposed on two opposite surfaces of a plate body 90 , and a heterogeneous layer 93 is formed on each of the release layers 91 .

[0051] In this embodiment, the heterogeneous layer 93 is a conductive material other than a copper layer, such as anisotropic conductive film (ACF).

[0052] like Figure 2BAs shown, a patterning process is performed to form a first wiring layer 21 on the heterogeneous layer 93 .

[0053] In this embodiment, the first circuit layer 21 is made of copper, so that the material forming the first circuit layer 21 is different from the material forming the heterogeneous layer 93. For example, the first circuit layer 21 adopts the specification of redistribution layer (RDL).

[0054] like Figure 2C As shown, a dielectric layer 22 is formed on the heterogeneous layer 93 of the carrier 9, and the dielectric layer 22 is defined with a first surface 22a and a second surface 22b opposite to each other, so that the first surface 22a of the dielectric layer 22 is combined with the heterogeneous layer 93, and then a plurality of blind holes 220 are formed on the second surface 22b of the dielectric layer 22.

[0055] In this embodiment, the dielectric layer 22 is Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0056] like Figure 2D As shown, a second circuit layer 23 is formed on the second surface 22b of the dielectric layer 22, and a plurality of conductive blind vias 24 electrically connecting the first circuit layer 21 and the second circuit layer 23 are formed in the blind vias 220 of the dielectric layer 22 to form a coreless circuit structure 2a.

[0057] In this embodiment, the second circuit layer 23 is manufactured by electroplating metal (such as copper) or other methods using a build-up process. For example, a plurality of blind holes 220 are first formed on the second surface 22b of the dielectric layer 22 using a laser, and then copper is electroplated on the dielectric layer 22 and in the blind holes 220 to form the second circuit layer 23 and the conductive blind holes 24 as a whole.

[0058] Furthermore, the second circuit layer 23 and the conductive blind via 24 are made of copper. For example, the second circuit layer 23 and the conductive blind via 24 adopt the specification of redistribution layer (RDL).

[0059] It should be understood that, by using the build-up method, the number of layers of the dielectric layer 22 of the circuit structure 2a can be designed according to the requirements to manufacture the required number of second circuit layers 23.

[0060] like Figure 2EAs shown, the plate body 90 of the carrier 9 and the circuit structure 2 a are separated by the release layer 91 to retain the heterogeneous layer 93 on the first surface 22 a of the dielectric layer 22 .

[0061] In this embodiment, the release layer 91 is removed by peeling or other methods.

[0062] like Figure 2F As shown, the heterogeneous layer 93 is removed by etching, so that the first circuit layer 21 is embedded in the dielectric layer 22 and exposed on the first surface 22 a of the dielectric layer 22 , and the first circuit layer 21 is flush with the first surface 22 a of the dielectric layer 22 .

[0063] In this embodiment, the etchant capable of etching the heterogeneous layer 93 (Ni material) includes free hydrogen, nitrate, phosphate and / or metal ions, so when etching the heterogeneous layer 93, the first circuit layer 21 will not be etched.

[0064] like Figure 2G As shown, an insulating protection layer 20 , such as a solder mask, having a plurality of openings 200 is formed on the first surface 22 a and the second surface 22 b of the dielectric layer 22 , respectively, so that portions of the surfaces of the first circuit layer 21 and the second circuit layer 23 are exposed through the openings 200 .

[0065] In addition, in the subsequent process, an electronic device 3 may be combined on the first circuit layer 21 or the second circuit layer 23. In this embodiment, the electronic device 3 is connected and electrically connected to the first circuit layer 21 through a plurality of conductive elements 26. The electronic device 3 is, for example, a semiconductor chip, a passive component, a silicon interposer, a circuit board or other components to form an electronic package.

[0066] Therefore, the packaging substrate of the present application is mainly formed by forming a heterogeneous layer 93 whose material is different from that of the first circuit layer 21, so that the first circuit layer 21 will not be micro-etched when the heterogeneous layer 93 is removed. Therefore, after removing the heterogeneous layer 93, the first circuit layer 21 is flush with the first surface 22a of the dielectric layer 22, and no grooves are formed on the first surface 22a of the dielectric layer 22, so that the multiple conductive elements 26 can be effectively combined on the first circuit layer 21, thereby avoiding the problem of empty soldering (i.e., the electronic device 3 is not soldered) or non-wetting.

[0067] Furthermore, since the material used to form the first circuit layer 21 is different from the material used to form the heterogeneous layer 93, when the heterogeneous layer 93 is removed, part of the material of the first circuit layer 21 will not be removed, thereby effectively preventing the first circuit layer 21 from being lateral etched, thereby avoiding damage (such as disconnection) and further avoiding the problem of poor signal transmission between the first circuit layer 21 and the conductive element 26.

[0068] The present application also provides a packaging substrate 2 , comprising: at least one dielectric layer 22 , a first circuit layer 21 , a heterogeneous layer 93 , at least one second circuit layer 23 , and a plurality of conductive blind vias 24 .

[0069] The dielectric layer 22 has a first surface 22 a and a second surface 22 b opposite to each other.

[0070] The first circuit layer 21 is embedded in the first surface 22 a of the dielectric layer 22 , wherein the first circuit layer 21 is flush with the first surface 22 a of the dielectric layer 22 .

[0071] The heterogeneous layer 93 is formed on the first surface 22 a of the dielectric layer 22 .

[0072] The second circuit layer 23 is formed on the second surface 22 b of the dielectric layer 22 .

[0073] The conductive blind via 24 is formed in the dielectric layer 22 and electrically connects the first circuit layer 21 and the second circuit layer 23 .

[0074] In one embodiment, the material forming the first circuit layer 21 is different from the material forming the heterogeneous layer 93 .

[0075] In one embodiment, the heterogeneous layer 93 is a conductive material other than a copper layer, such as an anisotropic conductive film.

[0076] In summary, the packaging substrate of the present application effectively controls the thickness of the first circuit layer to be consistent through the configuration of the heterogeneous layer, so that the conductive element can be effectively combined with the first circuit layer, thereby avoiding the problem of empty soldering or non-wetting, and the present application can improve reliability.

[0077] Furthermore, through the configuration of the heterogeneous layer, part of the material of the first circuit layer will not be removed when the heterogeneous layer is removed, thereby effectively preventing the first circuit layer from undergoing side corrosion. Therefore, the present application can avoid the problem of damage to the first circuit layer (such as disconnection) to improve the yield of signal transmission between the first circuit layer and the solder ball.

[0078] The above embodiments are only used to illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application should be as listed in the claims.

Claims

1. A packaging substrate, comprising: A dielectric layer having a first surface and a second surface opposite to each other; A first circuit layer embedded in the first surface of the dielectric layer, wherein the first circuit layer is flush with the first surface of the dielectric layer; a heterogeneous layer formed on the first surface of the dielectric layer; A second circuit layer formed on the second surface of the dielectric layer; and A plurality of conductive blind vias are formed in the dielectric layer and electrically connect the first circuit layer and the second circuit layer.

2. The packaging substrate according to claim 1, wherein: The material forming the first circuit layer is different from the material forming the heterogeneous layer.

3. The packaging substrate according to claim 1, wherein: The heterogeneous layer is a conductive material other than the copper layer.

4. The packaging substrate according to claim 3, wherein: The conductive material is an anisotropic conductive film.

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