38results about How to "Solve communication bottlenecks" patented technology

The invention relates to an automatic frequency tracking method and a system for an ultrasonic transducer. A direct digital frequency synthesizer is used as a signal source, wherein the direct digital frequency synthesizer can be an independent integrated chip and also be achieved by the method that a digital part of a DDS is integrated in a site programmable logical element FPGA and then a digital-analog converter is additionally added. The design of the invention adopts a frequency sweeping and tracking policy, and an automatic frequency controller achieved by the programmable element controls the output frequency of the DDS according to a feedback signal sampled from the self transducer end so as to achieve the full digitization automatic frequency tracking and ensure that the ultrasonic transducer work near a resonance point all the time to obtain the optimal efficiency. A phase comparator utilizes a trigger to give out the arriving time difference of two riser edge signals of twoinput signals I ph and V ph aiming to the sensitive characteristics of the riser edge signals, and the sequence of the riser edge signals of the two input signals I ph and V ph is given out by a Dirrect pin.

The invention relates to an intracorporal ultrasonic lithotripter consisting of an ultrasonic transducer and an automatic frequency tracking system, wherein, the ultrasonic transducer comprises more than two groups of piezoelectric ceramic pieces, a counterweight, the piezoelectric ceramic pieces and an amplitude transformer are connected together through hollow bolts, and the ultrasonic transducer is installed in the housing handle made of fire-resistant resin materials. A broken stone probe is connected with the front end of the amplitude transformer, a back cover is connected with the backend of the housing handle by screw threads, a pneumatic stone breaking device or a laser stone breaking device can be connected after the back cover is took down, an air regulation device which can regulate the adsorptive pressure in the operation process conveniently is installed on the side of the back end of the housing handle. The whole transducer can be fumigated in 125 DEG C. The automatic frequency tracking system adopts DDS and large-scale programmable devices, a direct digital frequency synthesizer to generate driving signals of the ultrasonic transducer and a strategy of autotracking after scanning search, thus, the automatic frequency tracking system adapts to the discreteness of the transducer and overcomes effects of a variety of causes on the resonance points.

The invention discloses a cell array calculation system, comprising a main control CPU, a cell array, a cell array bus and at least one memory unit array; the cell array is a two-dimension cell array consisting of at least one cell having functions of calculation and storage, wherein each cell comprises a microprocessor and a nonvolatile random storage device; the memory array is a two dimension array consisting of more than one memory unit; the cell array stacks with the memory unit array to form a three-dimension structure; the memory units in each memory unit are connected to the cells of the cell array in one-to-one correspondence; the memory unit cooperates with the nonvolatile random storage device to commonly perform random storage of the data related to the calculation of the microprocessor; a main control CPU performs communication with each cell in the cell array through the cell array bus; a communication interface is arranged between the adjacent cells in the cell array for transmitting data. The invention can overcome the communication bottleneck between the CPU and the memory and storage in the current computer architecture and improves the integral performance of the system.

The invention discloses a cell array calculation system and a communication method between cells. The cell array calculation system comprises a main control CPU, a cell array, a cell array bus and at least one memory unit array; the cell array is a two-dimension cell array consisting of at least one cell having functions of calculation and storage; the main control CPU performs communication with each cell in the cell array through the cell array bus; a communication interface is arranged between the adjacent cells in the cell array for transmitting data; the cells participating the communication between cells in the cell array comprises starting point cells, terminal point cells and transfer cells; the starting point cell transmits data to the terminal point cell; the terminal point cell finally receives the data transmitted from the starting point; and the forwarding cells are adjacent along the communication path between the cells and transfers the data transmitted by the starting point cell through the communication cell. The invention can overcome the communication bottleneck between the CPU and the memory and storage in the current computer architecture and improves the integral performance of the system.

The invention discloses a fluid machinery parallel simulation program process mapping method based on genetic algorithm, includes such steps as linking process communication stake library when fluid mechanical parallel simulation program is compiled, capturing communication information of MPI communication during program running, and obtaining log file with message size and communication frequencyof inter-process transmission; Constructing a process communication mode matrix according to the communication log file; constructing a communication distance matrix of computing unit to test the communication cost of computing resources applied by users; Defining the communication overhead model of parallel simulation programs for fluid machinery; using hybrid parallel genetic algorithm to solvethe optimal process mapping strategy; according to the optimal process mapping strategy obtained from the hybrid parallel genetic algorithm, statically binding the MPI process to the specified compute node, and rerunning the fluid mechanical parallel simulation program.

The invention disclose a cell array calculation system and a communication method wherein, comprising a main control CPU, a cell array and a cell array bus; the cell array is a three-dimension cell array obtained through stacking more than one two-dimension cell array; the two-dimension cell array consists of more than one cell having functions of calculation and storage, wherein each cell comprises a microprocessor and a nonvolatile random storage device; the nonvolatile random storage device is used for random access of the data related to the calculation of the microprocessor and is used for storing the software code and the data needed to be stored permanently; each cell stores the position of itself in the cell array as an ID for the software or the hardware in the cell to read; the main control CPU performs communication with each cell in the cell array through the cell array bus; and a communication interface is arranged between the adjacent cells in the cell array for transmitting data. The invention can overcome the communication bottleneck between the CPU and the memory and storage in the current computer architecture and improves the integral performance of the system.

The invention discloses a route node microstructure of a network on chip, which comprises a head decode module, an input buffer module, an input control module, an output arbitration module, an output buffer module and an output control module. The head decode module performs the head analysis to data entering the route node from the upper route node, and inputs the data to the input buffer module; the input buffer module is used for the temporary storage of the data, and outputs the data to the output arbitration module under the action of the input control module. After the data enters the output arbitration module, the output arbitration module determines whether outputting the data to the output buffer module according to the state of the input control module, and the output arbitration module controls the whole output link so as to realize that the data is transmitted to the next route node. Through the route node microstructure of the invention, the data transmission among the route nodes of the network on chip can be realized, and the transmission efficiency can be greatly improved.

The invention relates to a cell array calculation system and a communication method thereof. The cell array calculation system comprises a main-control central processing unit (CPU), a cell array and a cell array bus, wherein the cell array is a two-dimensional array comprising more than one cell compatible with functions of calculation and storage, the main-control CPU is in communication with each cell in the cell array through the cell array bus, a communication interface is arranged between adjacent cells and can be used for sending data, cells participating communication among cells comprise a starting cell, a terminal cell and transit cells, the starting cell is the cell for sending data to the terminal cell, the terminal cell is the cell for finally receiving the data sent from the starting cell, the transit cells are cells which are sequentially adjacent to one another along a communication path among the cells and are used for transiting the data sent from the starting cell through the communication interface, and an arbitrary cell also can be taken as the starting cell for group-sending communication to all cells in a target region. By the cell array calculation system, the communication bottleneck existing between the CPU and the memory and storage of a conventional computer framework can be overcome, and the comprehensive performance of the system is improved.

The application provides a method for coordinating distributed power flow optimization of the main distribution network and related equipment, wherein the method of the application includes: according to the topological relationship of the distribution network system model, the distribution network system model is divided into a main network model and a distribution network model Model; according to the preset power flow optimization target threshold, the main distribution coordination power flow optimization model is established, and the main network ADMM iterative optimization model and the distribution network ADMM iterative optimization model are respectively established through the alternate direction multiplier calculation method according to the main distribution coordination power flow optimization model ; The main network ADMM iterative optimization model and the distribution network ADMM iterative optimization model are iteratively calculated to obtain the current main network optimization parameters and distribution network optimization parameters. This application is based on the target-synchronized alternating direction multiplier method of the master-coordinated distributed power flow optimization method, which does not require a unified upper-level optimization center, and solves the calculation and communication bottleneck problems of the existing centralized optimization degree method with a distributed calculation mode , which improves the power flow optimization efficiency of the main distribution coordination.