Method and system for preventing error locking of DLL (Delay-Locked Loop)

Abstract

The invention provides a method and system for preventing the error locking of a DLL (Delay-Locked Loop). The method comprises the following steps: (1) a continuous delay increasing step; and (2) a trimming step, wherein the step (1) concretely comprising the following steps of : (1.1) dividing the frequency of an input clock by an input clock frequency dividing circuit and respectively inputtingthe acquired divided-frequency input clocks into a phase discriminator (I) and a phase discriminator (II) of a control logical circuit; ( 1.2) differentially dividing the frequency of a feedback clock by a feedback clock frequency dividing circuit to acquire two paths of differential feedback clocks and respectively inputting the two paths of differential feedback clocks into the phase discriminator (I) and the phase discriminator (II) of the control logical circuit; and (1.3) sampling and comparing the divided-frequency input clock and the two paths of differential feedback clocks by the phase discriminator (I) and the phase discriminator (II) and emitting a locking signal when the outputs of the phase discriminator (I) and the phase discriminator (II) jump from 1 to 0 or from 0 to 1. The method and system provided by the invention can effectively prevent the error locking phenomenon of the DLL in case of the jitter of the input clock, are simple in control logic and can accelerate the locking process.

Description

technical field [0001] The invention belongs to the field of delay-locked loops, in particular to a method and system for preventing wrong locking of delay-locked loops. Background technique [0002] A delay-locked loop is a delay-output system that generates an input clock through a delay line. [0003] see figure 1 , the specific basic working principle of the delay-locked loop is as follows: [0004] Step 1: The output clock of the delay-locked loop passes through the clock distribution network to generate a feedback clock, and the feedback clock is re-input into the delay-locked loop. [0005] Step 2: The phase detector of the delay-locked loop samples and compares the input clock and the feedback clock, and outputs the comparison result to the control logic circuit, [0006] Step 3: The control logic circuit adjusts the delay of the variable delay line according to the comparison result, so as to realize zero transmission delay between the feedback clock and the inpu...

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