Cache partitioning method

Abstract

The invention discloses a cache partitioning method, which comprises the following steps of: partitioning, namely dividing a cache of the last stage into a first area and a second area with a same size logically; addition of cache data block information bits, namely adding accessed frequency bits, wherein the accessed frequency of a cache data block is represented by using two bits; and addition of a historical access record chart, namely adding the horizontal access record chart to record accessed cache data blocks, wherein each record represents information flag bits and significant bits of the cache data blocks. By the method, the cache of the last stage is partitioned, so that the utilization efficiency of the cache of the last stage is improved; and for a high-capacity cache, relatively more frequently accessed cache data blocks are stored in the cache, and relatively less frequently accessed cache data blocks are transferred to a main memory, thereby increasing the cache access hit rate and improving system performance.

Description

technical field [0001] The invention belongs to the technical field of storage, and relates to a large-capacity cache and a cache partition method under a multi-core architecture. Background technique [0002] At present, the performance of most computer systems is largely determined by the average memory access latency. Improving the cache hit rate can reduce the number of memory accesses and improve system performance. The current processors all use a cache mechanism, and the function of the cache is mainly to alleviate the speed and performance mismatch between the adjustment processor and the low-speed main memory. The cache implements a hierarchical mechanism. Most current processors use three-level cache (L1, L2, L3), and the last level cache (L3) is close to the main memory. As the capacity of the last-level cache continues to increase, the corresponding management strategy must also be continuously improved to increase the utilization of the cache and reduce the num...

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