A sampling clock selection method and device

A sampling clock and clock technology, applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, etc., can solve the problem that the middle value of the clock window cannot be sampled to the correct data, the acquisition clock window changes, and the data Low sampling accuracy and other issues, to achieve the effect of improving data sampling accuracy, improving work efficiency, and reducing the number of selections

Active Publication Date: 2016-03-30
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In the process of realizing the above sampling clock selection, the inventors found that there are at least the following problems in the prior art: when the change of environmental factors such as temperature will cause a relatively large offset of the received data signal, the sampling clock window will change, and the That is, the correct data cannot be sampled using the middle value of the current sampling clock window
As a result, whenever the acquisition clock window changes due to changes in environmental factors, we need to re-determine a new acquisition clock window and a acquisition clock, which makes the selection of sampling clocks too many times, which affects the low accuracy of data sampling, which in turn affects system efficiency

Method used

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  • A sampling clock selection method and device

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Embodiment 1

[0025] The embodiment of the present invention provides a sampling clock selection method, such as figure 1 As shown, the method includes:

[0026] 101. Obtain all current clock configuration values ​​that can be used to correctly sample data.

[0027] Wherein, the clock configuration value may be obtained by dividing the frequency, phase or delay of the sampling clock adjustable by the device into N equal parts, where N is a positive integer. The specific implementation of N equal division depends on the adjustment accuracy that the device can achieve. For example, if the minimum adjustment accuracy of the delay unit in the device is 1ns, the delay of the adjustable sampling clock for the device can be divided into 1ns N copies. Certainly, different devices may be set to different implementation methods, which is not limited in this embodiment of the present invention.

[0028] Wherein, the realization method of acquiring all current clock configuration values ​​that can b...

Embodiment 2

[0047] The embodiment of the present invention provides a sampling clock selection method, such as figure 2 shown, including:

[0048] 201. Acquire all current clock configuration values ​​that can be used to correctly sample data.

[0049] Wherein, the related description of the clock configuration value and the corresponding acquisition method is the same as the related description in the step 101, which will not be repeated in this embodiment of the present invention.

[0050] 202. Add an adjustment value to the stored first weights corresponding to the clock configuration values ​​respectively, generate second weights corresponding to the clock configuration values, and replace the first weights with the The second weight is stored.

[0051] Wherein, the related description of the first weight value and the adjustment value is the same as the related description in the step 102, which will not be repeated in this embodiment of the present invention.

[0052] 203. Deter...

Embodiment 3

[0072] The embodiment of the present invention provides a sampling clock selection device, such as image 3 As shown, the device includes: a clock controller 31 , a weight comparator 32 , and a weight register 33 .

[0073] The clock controller 31 is configured to obtain all current clock configuration values ​​that can be used to correctly sample data. and adding an adjustment value to the first weights corresponding to the stored clock configuration values, generating second weights corresponding to the clock configuration values, and replacing the first weights with the first weights Two weights are stored.

[0074] The weight comparator 32 is configured to judge whether the second weights corresponding to the clock configuration values ​​generated by the clock controller 31 are the same.

[0075] The clock controller 31 is configured to select from the second weights corresponding to the clock configuration values ​​when the weight comparator 32 determines that the secon...

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Abstract

The invention discloses a method and device for selecting a sampling clock and relates to the technical field of communication. The method and device for selecting the sampling clock reduces the number of selecting times of the sampling clock, improves data sampling accuracy and further improves the working efficiency of a system. The method for selecting the sampling clock comprises the steps of acquiring all current clock configuration values which can be used for sampling data accurately, adding adjusting values to first weights corresponding to all the stored clock configuration values respectively, generating second weights corresponding to the clock configuration values respectively, replacing the first weights to the second weights and carrying out storage, judging whether all the second weights corresponding to the clock configuration value respectively are identical or not, if the fact that not all the second weights corresponding to the clock configuration values respectively are identical is confirmed, selecting a maximum value from the second weights corresponding to the clock configuration values respectively, and determining the clock configuration value corresponding to the selected maximum value to be the current sampling clock. The method and device for selecting the sampling clock is mainly applied to the selecting process of the sampling clock.

Description

technical field [0001] The present invention relates to the technical field of communications, in particular to a sampling clock selection method and device. Background technique [0002] When two modules in the chip interact with each other, it is necessary to synchronize the clock used for sampling data and the clock used for receiving data in the sampling module to ensure that the data can be sampled correctly. During the use of the chip, there will be changes in environmental factors such as temperature, which will cause the received data signal to shift, making the sampling module in the chip unable to accurately sample data when sampling data on the sampling clock that can accurately sample data. [0003] In order to synchronize the clock used for sampling data with the clock used for receiving data, a solution is provided in the prior art, which specifically includes: obtaining all clocks that can correctly sample data, these clocks constitute a clock window for corre...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0185
Inventor 何世明王瑞
Owner HUAWEI TECH CO LTD
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