Pixel circuit, driving method thereof, organic light-emitting display panel, and display device
A pixel circuit and light-emitting device technology, applied in static indicators, instruments, etc., can solve problems such as inconsistent brightness of the first frame, and achieve the effects of avoiding inconsistent threshold capture, consistent brightness, and preventing afterimages
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Embodiment 1
[0084] by Figure 4a The pixel circuit shown is taken as an example, wherein the fourth transistor M4 and the fifth transistor M5 have a single gate structure; the corresponding input timing diagram is as follows Figure 7a shown. Specifically, the main selection of Figure 7a In the shown input timing diagram, there are three stages: the initialization stage T1, the data writing stage T2 and the light emitting stage T3.
[0085] In the initialization phase T1, Scan1=0, Scan2=1, CS01=0, CS02=1, EMIT=1.
[0086] Since Scan1=0, the first transistor M1 is turned on and provides the signal of the reference signal terminal VREF to the first node N1, so that the voltage of the first node N1 is the voltage V of the reference signal terminal VREF ref . Since CS01=0, the fourth transistor M4 is turned on to connect the first node N1 and the third node N3, so the voltage of the third node N3 is also V ref , and make the drive transistor M0 in a diode structure. The voltage V of th...
Embodiment 2
[0094] by Figure 4c The pixel circuit shown is taken as an example, wherein the fourth transistor M4 and the fifth transistor M5 have a single gate structure; the corresponding input timing diagram is as follows Figure 7b shown. Specifically, the main selection of Figure 7b In the shown input timing diagram, there are three stages: the initialization stage T1, the data writing stage T2 and the light emitting stage T3.
[0095] In the initialization phase T1, Scan1=0, Scan2=1, EMIT=1.
[0096] Since Scan1=0, the first transistor M1 is turned on and provides the signal of the reference signal terminal VREF to the first node N1, so that the voltage of the first node N1 is the voltage V of the reference signal terminal VREF ref . Since EMIT=1, the fourth transistor M4 is turned on to connect the first node N1 and the third node N3, so the voltage of the third node N3 is also V ref , and make the drive transistor M0 in a diode structure. The voltage V of the first node N1 ...
Embodiment 3
[0103] by Figure 6a The pixel circuit shown is taken as an example, wherein the sixth transistor M6 has a single gate structure; its corresponding input timing diagram is as follows Figure 7c shown. Specifically, the main selection of Figure 7c In the shown input timing diagram, there are three stages: the initialization stage T1, the data writing stage T2 and the light emitting stage T3.
[0104] In the initialization phase T1, Scan1=0, Scan2=1, CS0=0, EMIT=1.
[0105] Since Scan1=0, the first transistor M1 is turned on and provides the signal of the reference signal terminal VREF to the first node N1, so that the voltage of the first node N1 is the voltage V of the reference signal terminal VREF ref . Since CS0=0, the sixth transistor M6 is turned on to connect the first node N1 and the third node N3, so the voltage of the third node N3 is also V ref , and make the drive transistor M0 in a diode structure. The voltage V of the first node N1 ref The second node N2 i...
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