PCIe Error Enabling test method

Abstract

The invention provides a PCIe Error Enabling test method. Firstly a topological port of a PCIe device identifiable for a Python language tool is queried by using a debug tool ITP; and secondly a PCIeError Enabling test is performed. The method is suitable for an X86 server product having an XDP interface and supporting a PCIe Error Enabling function. Under the condition of starting the PCIe ErrorEnabling function, correctable errors are injected into the PCIe device to simulate PCIe device Errors occurring in an actual application; by reading the value of a register, whether the PCIe Error Enabling function is successfully realized or not is judged; and when the Error number reaches a threshold, the phenomena of disk identification incapability and the like of the server do not occur. The test method is simple in operation and relatively high in practicality, and effectively ensures the reliability and security of the server.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a PCIe Error Enabling testing method. Background technique [0002] With the Internet and other major industries' requirements for big data and the rapid development of servers, the requirements for server security and reliability are getting higher and higher. As a server product provider, whether a server is in the R&D stage or the production stage, it is necessary to simulate the customer's use process to test the security of the product, and the security test is mainly reflected in the RAS performance. [0003] An important point in the RAS feature is the RAS feature of the PCIe device. The PCIe device is an important electronic device in the server. With the high performance and high scalability requirements of the server, there are more and more PCIe expansion devices in the server, so errors will inevitably occur during its work, and for stability For users with high p...

AI Technical Summary

Problems solved by technology

[0005] There are various testing methods for RAS performance, but the topology of PCIe devices is relatively complex. The tools under the system or the port ports of PCIe devices read out by the debug tool are related to the actual hardware design. BIOS will read from the hardware device. However, the topology port cannot be identified by the Python language tool, so traditional pure software testing methods such as Intel's IDK tool are difficult to implement. There must be a way to find the topology port that the Python language tool can identify

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