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Instruction coupling device, method, equipment and storage medium for processor core verification

A processor core and coupling device technology, which is applied in program control devices, electrical digital data processing, special data processing applications, etc., can solve the problem of low convergence of test coverage

Active Publication Date: 2021-02-05
PENG CHENG LAB
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The main purpose of the present invention is to provide an instruction coupling device, method, equipment and storage medium for processor core verification, aiming to solve the technical problem of low convergence of test coverage in the current processor core verification instruction coupling method

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  • Instruction coupling device, method, equipment and storage medium for processor core verification
  • Instruction coupling device, method, equipment and storage medium for processor core verification
  • Instruction coupling device, method, equipment and storage medium for processor core verification

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Embodiment Construction

[0036] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0037] The present invention provides an instruction coupling device for processor core verification, referring to figure 1 , figure 1 A schematic diagram of a preferred structure of the instruction coupling device for processor core verification of the present invention.

[0038] The instruction coupling device verified by the processor core is applied to a RISC-V processor, and the instruction coupling device verified by the processor core includes: a configuration information parser 10, a constraint solver 20, an instruction generator 30 and an instruction transmitter 40 , wherein, the configuration information parser 10 is used to resolve the configuration information corresponding to the test case in the RISC-V processor core into corresponding first constraint data; the constraint solver 20 is used to analyze t...

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Abstract

The invention discloses an instruction coupling device, method, equipment and storage medium for processor core verification. The instruction coupling device for processor core verification includes: a configuration information parser, a constraint solver, an instruction generator, and an instruction transmitter. The information parser is used to parse the configuration information of the test case in the processor core into the first constraint data; the constraint solver is used to solve the constraints based on the first constraint data, determine the result of solving the constraints, and generate the second constraint data based on the first constraint data The instruction generator is used to generate coupled instructions or uncoupled instructions based on the second constraint data; the instruction transmitter is used to send the coupled instructions or uncoupled instructions to the driver, and feed back the generated instruction information to the constraint solver. The invention couples the configuration information with the instruction information in the instruction transmitter, so that each instruction is correlated and dependent on each other, and the convergence efficiency of the test coverage rate is improved.

Description

technical field [0001] The invention relates to the field of instruction coupling and logic testing, in particular to an instruction coupling device, method, equipment and storage medium for processor core verification. Background technique [0002] At present, the processor core verification command coupling method is mainly to generate configuration information from test cases and send the configuration information to the configuration information parser. The configuration information parser parses the received configuration information into constraints, and the constraints are processed by the constraint solver. The instruction generator can generate instructions within the set specified by the constraints. The generated commands are sent by the command transmitter to the driver for processing. The constraint solver, instruction generator, and instruction emitter run for multiple rounds, generating one instruction per round, until the total number of issued instructions ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/445G06F30/327G06F11/36
CPCG06F9/4451G06F11/3676G06F11/3684G06F30/327
Inventor 张延飞张凡李睿高峰
Owner PENG CHENG LAB
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