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Digital driver, feedback circuit for analog-to-digital converter and digital-to-analog converter

A digital driver and analog-to-digital converter technology, applied in the electronic field, can solve problems such as slow speed, and achieve the effect of reducing delay time and power consumption

Pending Publication Date: 2022-05-13
UNIVERSITY OF MACAU +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the limitation of digital SAR logic delay time per cycle, slo

Method used

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  • Digital driver, feedback circuit for analog-to-digital converter and digital-to-analog converter
  • Digital driver, feedback circuit for analog-to-digital converter and digital-to-analog converter
  • Digital driver, feedback circuit for analog-to-digital converter and digital-to-analog converter

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] An embodiment of the present disclosure provides a digital driver.

[0038] Specifically, see figure 1 , figure 1 Shown is a schematic structural diagram of the digital driver 10, the digital driver 10 includes: an input terminal IN, an output terminal OUT, a first P-type metal-oxide-semiconductor (P-Metal-Oxide-Semiconductor, PMOS) transistor M P1 , the second PMOS transistor M P2 , the third PMOS transistor M P3 , the fourth PMOS transistor M P4 , the first N-type metal oxide semiconductor (N-Metal-Oxide-Semiconductor, NMOS) transistor M N1 , the second NMOS transistor M N2 , the third NMOS transistor M N3 and the fourth NMOS transistor M N4 ;

[0039] The input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor;

[0040] The first PMOS transistor M P1 The drain of the first NMOS transistor M N1 The drain of the second PMOS transistor M P2 gate of the second NMOS transistor M N2 The gate of is connecte...

Embodiment 2

[0074] An embodiment of the present disclosure also provides a feedback circuit for an analog-to-digital converter.

[0075] Specifically, see Figure 4A , Figure 4A Shown is a schematic structural diagram of a feedback circuit for an analog-to-digital converter, and the feedback circuit 40 for an analog-to-digital converter includes:

[0076] Capacitive DAC401, comparison circuit 402, asynchronous logic control circuit 403 and DAC switch control circuit 404;

[0077] The capacitive DAC includes multiple capacitors C 1 、C 2 ,...,C i , ..., and a plurality of digital drivers 4011, each of which is the digital driver provided in Embodiment 1;

[0078] The asynchronous logic control circuit 403 includes a plurality of flip-flops DFF A ; The DAC switch control circuit 404 includes a plurality of flip-flops DFF D ;

[0079] Each capacitor C i It is connected to the input terminal of the corresponding digital driver 4011, and the output terminal of the capacitive DAC401 is...

Embodiment 3

[0106] In addition, an embodiment of the present disclosure provides an analog-to-digital converter, and the analog-to-digital converter includes the feedback circuit for the analog-to-digital converter provided in Embodiment 2.

[0107] The analog-to-digital converter provided in this embodiment includes the feedback circuit for the analog-to-digital converter provided in Embodiment 2, so it has the corresponding structure and function of the feedback circuit for the analog-to-digital converter provided in Embodiment 2 And beneficial effects, in order to avoid repetition, do not repeat them here.

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PUM

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Abstract

The embodiment of the invention provides a digital driver. The digital driver comprises an input terminal, an output terminal, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, the input terminal, the first PMOS tube and the first NMOS tube are connected; the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube are connected to a first node; the second PMOS tube, the second NMOS tube, the third PMOS tube and the third NMOS tube are connected to a second node; the third PMOS tube, the third NMOS tube, the fourth PMOS tube and the fourth NMOS tube are connected to a third node; the fourth PMOS tube and the fourth NMOS tube are connected with the output terminal; and the width of each PMOS tube and each NMOS tube is determined according to the mobility and a preset reduction coefficient. Therefore, the size of the transistor is adjusted by adopting the preset reduction factor, and delay time and power consumption can be reduced.

Description

technical field [0001] The present application relates to the field of electronic technology, and in particular to a digital driver, a feedback circuit for an analog-to-digital converter, and a digital-to-analog converter. Background technique [0002] The existing traditional successive approximation analog-to-digital converter (Successive Approximation Register Analog-to-Digital Converter, SAR ADC) includes a tracking sample and hold circuit (T / H), a comparator, SAR logic circuit and a capacitive digital-to-analog converter (Digital-to-Analog Converter, DAC), this traditional structure has the advantages of low complexity, low power consumption and high energy efficiency topology with reduced process technology, which makes the traditional structure widely used in high-speed applications. For example, the traditional structure can be used In time-interleaved successive approximation analog-to-digital converter (TI-SAR ADC). Some existing solutions speed up the conversion ...

Claims

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Application Information

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IPC IPC(8): H03M1/12H03M1/46
CPCH03M1/129H03M1/46H03M1/462
Inventor 郭铭强冼世荣肖刚军赵伟兵许登科马许愿
Owner UNIVERSITY OF MACAU