GaN transistor structure and preparation method thereof

Abstract

The invention discloses a GaN transistor structure and a preparation method thereof, a grid electrode in a GaN transistor is of a closed frame structure, the grid electrode surrounds a source electrode, a drain electrode and the source electrode can be thoroughly isolated, electric field distribution between the grid electrode and a channel is optimized, forward bias grid electrode voltage of the transistor is remarkably improved, formation of an electric leakage channel is effectively restrained, and the reliability of the transistor is improved. The leakage current is greatly reduced, and the stability and reliability of the device in a circuit are enhanced. Besides, the grid electrode adopting the structure can optimize electric field distribution around the grid electrode, reduces generation and propagation paths of high-energy electrons, and can remarkably enhance robustness of the grid electrode under a high-temperature condition, so that damage of an impact ionization effect to the grid electrode is effectively inhibited.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device design, and in particular relates to a GaN transistor structure and a preparation method thereof. Background Art

[0002] High electron mobility transistors (HEMTs) are widely used in high-frequency and high-power electronic devices, and have attracted much attention due to their excellent electrical properties under high-frequency, high-power and high-temperature environments. However, the traditional HEMT structure still faces many challenges under certain conditions, and is prone to gate leakage current surges under high temperatures or strong electric fields. This is mainly due to the increase in gate leakage current (current in the passive region) caused by the impact ionization effect, which seriously affects the stability and reliability of the device. Please refer to Figure 1 , especially under illumination, it has a great impact on the gate leakage current of traditional GaN HEMT (gallium nitride high electron mobility transistor), mainly through the generation of photogenerated carriers, surface state charging and discharging, and trap state filling and release mechanisms, which lead to an increase in gate leakage current.

[0003] In order to solve the above technical problems, in the prior art, GaN HEMT design introduces optimizations such as high-K dielectric materials, passivation layers and field plates, and electric field distribution into the structure. For example, high-K dielectric materials such as HfO2 (hafnium dioxide) and Al2O3 (aluminum oxide) are deposited in the gate region to replace traditional SiO2 (silicon nitride) or Si3N4. High-K dielectric materials have a higher dielectric constant and can achieve the same channel modulation effect at a lower gate voltage, reducing leakage current and gate voltage stress; passivation layer deposition: a passivation layer (such as SiN (silicon nitride), AlN (aluminum nitride)) is deposited on the GaN surface and the AlGaN (aluminum gallium nitride) / GaN heterojunction interface. The passivation layer can reduce the surface state density and reduce the gate leakage current. A double-layer metal gate structure is used in the gate region, with the upper layer being the gate metal and the lower layer being the protective metal layer under the gate. An insulating layer is sandwiched between the two metal layers; buried gate design: the gate is partially buried in the GaN material, and the passivation layer is covered above the gate. The buried gate design reduces the surface electric field source by changing the electric field distribution; the field plate design: adds a field plate in the source area, and the source field plate is used in combination with the gate field plate to further optimize the electric field distribution, etc.

[0004] In addition, the traditional HEMT structure consists of an AlGaN / GaN heterojunction, which grows a GaN layer on the buffer layer as the main conductive channel, and deposits a layer of AlGaN on the GaN layer to form a high-density, high-mobility two-dimensional electron gas (2DEG), thereby providing high conductivity and low on-resistance. This structure makes HEMT have broad prospects in high-voltage and high-frequency applications. However, under high temperature or strong electric field environment, the traditional HEMT has no additional insulating layer because the gate is in direct contact with the AlGaN layer. This structure is simple to prepare, but it is susceptible to impact ionization at high voltage, resulting in higher leakage current and lower breakdown voltage, affecting the stability and reliability of the device; and under illumination conditions, photogenerated carriers will directly form a low-resistance path between the 2DEG channel and the top gate metal, thereby changing the potential and affecting the device performance. In addition, there are some deep energy level traps in GaN and AlGaN materials, which may capture photogenerated carriers and increase the gate leakage current, affecting circuit performance.

[0005] The p-GaN HEMT (gallium phosphide high electron mobility transistor) introduces a p-type GaN layer on the AlGaN / GaN heterojunction below the traditional device gate. The p-GaN cap layer can increase the energy band at the AlGaN / GaN heterojunction interface, making it higher than the Fermi level when the gate bias is 0 V, thereby achieving enhanced (E-mode) operation, which can solve the above-mentioned problems of increased leakage current and reduced breakdown voltage to a certain extent. Therefore, p-GaN HEMT performs well under high temperature and high frequency conditions and is suitable for high-power and high-frequency application scenarios. Although p-GaN HEMT has good electrical properties, its gate leakage current problem still needs to be further solved, especially under high temperature conditions, this leakage current will increase significantly; in order to obtain a p-type conductive GaN layer, magnesium is usually used as a dopant to obtain a p-type conductive GaN layer, but the Mg dopant has low solubility in GaN and high ionization energy, so it is difficult to achieve a sufficiently high hole concentration, resulting in the p-GaN layer being difficult to completely deplete the 2DEG under the gate in practical applications. At the same time, during the high-temperature growth process, Mg inevitably diffuses into the AlGaN barrier layer and the GaN channel layer. This diffusion behavior will greatly hinder the increase of the device threshold voltage, thereby damaging the device performance.

[0006] MIS HEMT (Metal-Insulator-Semiconductor High Electron Mobility Transistor) uses high-K gate dielectric materials, such as HfO2 (hafnium dioxide) and Al2O3 (aluminum oxide), instead of traditional SiO2 (silicon dioxide) or Si3N4 (silicon nitride), to increase gate capacitance, reduce gate leakage current, and enhance gate withstand voltage and thermal stability. By introducing an insulating layer between the gate and the AlGaN layer, the gate leakage current is effectively reduced and the electrical performance of the device is improved. In addition, high-K dielectric materials have a higher dielectric constant and can achieve the same channel modulation effect at a lower gate voltage, reducing leakage current and gate voltage stress. However, the gate dielectric reliability of MIS HEMT (Metal-Insulator-Semiconductor High Electron Mobility Transistor) in high temperature environments needs further research and resolution. In addition, under ultraviolet light irradiation, ultraviolet light will induce excessive trap states in the insulating layer, making charge capture in the gate dielectric more serious, while charge capture in the GaN buffer is significantly suppressed. Summary of the invention

[0007] The invention discloses a GaN transistor structure and a preparation method thereof, which avoids the gate leakage problem under high temperature, strong electric field and light conditions.

[0008] The present invention discloses a GaN transistor structure, comprising: A gate having a closed frame structure; The gate surrounds the source and isolates the source from the drain.

[0009] Furthermore, the gate, the source and the drain are all located in the active area.

[0010] Further, the active region is located between the source and the drain; Part of the gate extends into the inactive region.

[0011] Furthermore, the gate is made of at least one of titanium, aluminum and tungsten.

[0012] Furthermore, the gate is deposited on the surface of the insulating layer, and the insulating layer is located on the gate region.

[0013] Furthermore, the gate is in direct contact with the p-type doped layer, the metal layer and / or the insulating layer.

[0014] Further, the GaN transistors include: p-GaN HEMT, GaN HEMT, MIS-HEMT and GaN MOSFET.

[0015] The present invention also provides a method for preparing a GaN transistor structure, the method comprising: Provide a front-end structure; forming an insulating layer in a gate region within the front-end structure; forming a closed groove on the insulating layer, A gate metal is deposited in the groove to form a gate, which surrounds the source and isolates the source from the drain.

[0016] Furthermore, providing the front-end structure includes: providing a substrate; A channel layer, a barrier layer, a passivation layer, and a p-type doping layer are sequentially stacked on the substrate; Determining growth regions of a source electrode and a drain electrode on the p-type doped layer; removing the p-type doped layer in the growth region; A metal layer is deposited on the surface of the barrier layer to form the source electrode and the drain electrode.

[0017] Furthermore, after depositing gate metal in the groove to form the gate, the method further comprises: Use plasma enhanced chemical vapor deposition of p-type doped layers for passivation and protection; Device isolation using fluoride ion implantation; Determine the pad area, remove the p-type doped layer and deposit the pad metal electrode.

[0018] Compared with the prior art, the present invention can at least achieve the following technical effects: The present invention introduces a gate with a closed frame structure, and the gate surrounds the source, which can completely isolate the drain and the source, optimize the electric field distribution between the gate and the channel, significantly improve the forward bias gate voltage of the transistor, and effectively suppress the formation of the leakage channel, greatly reduce the leakage current, and enhance the stability and reliability of the circuit. In addition, the gate with the above structure can also optimize the electric field distribution around the gate, reduce the generation and propagation path of high-energy electrons, and significantly enhance the robustness of the gate under high temperature conditions, thereby effectively suppressing the damage to the gate caused by the impact ionization effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a gate structure in the prior art; Figure 2 Schematic diagram of the gate structure of a GaN transistor in Embodiment 1 of the present invention; Figure 3 Schematic diagram of another GaN transistor gate structure in Embodiment 1 of the present invention; Figure 4 Schematic diagram of the structure of a p-GaN HEMT in Embodiment 1 of the present invention; Figure 5 This is a flow chart of the method for preparing p-GaN HEMT in Example 2 of the present invention. DETAILED DESCRIPTION

[0020] A GaN transistor structure and a method for manufacturing the same according to the present invention will be described below in conjunction with a schematic diagram, wherein preferred embodiments of the present invention are shown. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation to the present invention.

[0021] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the scope of protection of the present invention. The embodiments of the present invention are described in detail below in conjunction with the drawings.

[0023] Please refer to Figure 2-Figure 3 The present invention discloses a GaN transistor structure, comprising: a gate in a closed frame structure; the gate surrounds a source and isolates the source from a drain.

[0024] In this embodiment, by introducing a gate with a closed frame structure, and the gate surrounds the source, the drain and the source can be completely isolated, thereby significantly improving the forward bias gate voltage of the transistor. The fully surrounded gate structure not only effectively suppresses the formation of leakage channels in the passive area, greatly reduces leakage current, but also enhances the stability and reliability of the circuit. In addition, the gate using the above structure can also optimize the electric field distribution around the gate, reduce the generation and propagation path of high-energy electrons, and significantly enhance the robustness of the gate under high temperature conditions, thereby effectively suppressing the damage to the gate caused by the impact ionization effect.

[0025] In a specific embodiment, please refer to Figure 2 , the gate, the source and the drain can all be arranged in the active area.

[0026] In another specific embodiment, please refer to Figure 3, a portion of the gate may be located in the inactive region, the active region is located between the source and the drain, and the distance between two parallel outer sides of the gate is greater than the width of the active region.

[0027] In a specific embodiment, the gate of the closed frame structure can be a rectangular frame structure, a circular ring structure or an elliptical ring structure, and can also be adjusted to other closed frame structures of different shapes according to the electrical isolation requirements of the source and the drain. In addition, the specific size of the closed frame is not specifically limited here, and those skilled in the art can optimize and adjust it according to the electrical isolation requirements.

[0028] Furthermore, in this embodiment, the gate is deposited on the surface of the insulating layer, and the insulating layer is located above the gate region.

[0029] In this embodiment, the gate can be in direct contact with the p-type doped layer, the metal layer and / or the insulating layer.

[0030] In a specific embodiment, the material that may be used for the insulating layer includes but is not limited to silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0031] The transistor gate structure can be used in various types of GaN transistors, such as p-GaN HEMT, GaN HEMT, MIS-HEMT and GaN MOSFET.

[0032] In a specific embodiment, please refer to Figure 4 The structure of the p-GaN HEMT includes: a GaN buffer layer, an AlGaN barrier layer, a p-GaN layer and a dielectric layer (i.e., an insulating layer) deposited on a substrate in sequence, a source and a drain formed at both ends of the AlGaN barrier layer; and a gate of the above structure formed on the surface of the p-GaN layer, the gate of the above structure surrounding the source.

[0033] In another specific embodiment, the structure of the GaN HEMT includes: a GaN buffer layer, an AlGaN barrier layer, a Schottky metal layer and an insulating layer deposited in sequence on a substrate; a source and a drain formed at both ends of the AlGaN barrier layer; and a gate of the above structure formed on the surface of the Schottky metal layer, wherein the gate of the above structure surrounds the source.

[0034] In another specific embodiment, the structure of the MIS-HEMT includes: a GaN buffer layer, an AlGaN barrier layer, and a SiN3N4 insulating layer deposited sequentially on a substrate; a source and a drain formed at both ends of the AlGaN barrier layer; and a gate of the above structure formed on the surface of the SiN3N4 insulating layer, wherein the gate of the above structure surrounds the source.

[0035] In another specific embodiment, the structure of the GaN MOSFET includes: a GaN buffer layer, a GaN layer, an AlGaN layer and an insulating layer deposited in sequence on a substrate; a source and a drain formed at both ends of the AlGaN layer; and a gate of the above structure formed on the surface of the insulating layer, the gate of the above structure surrounding the source.

[0036] Embodiment 2 Please refer to Figure 5 This embodiment discloses a preparation method for preparing a transistor structure as disclosed in Embodiment 1, the preparation method comprising: S1. Provide a front-end structure; S2. forming an insulating layer on the gate region of the front-end structure; S3. forming a closed groove on the insulating layer; S4. Depositing gate metal in the groove to form a gate, the gate surrounds the source and isolates the source from the drain.

[0037] In this embodiment, the front-end structure includes but is not limited to GaN devices such as p-GaN HEMT, GaNHEMT, MIS-HEMT and GaN MOSFET without metal gate deposition. Those skilled in the art can set the above transistor gate structure on different GaN devices according to actual conditions.

[0038] In a specific embodiment, a method for preparing a p-GaN HEMT with the above-mentioned gate structure is as follows: S11. Provide a substrate; wherein the substrate is usually made of single crystal silicon, sapphire and other materials.

[0039] S12. A channel layer, a barrier layer, a passivation layer, and a p-type doping layer are sequentially stacked on the substrate; in addition, a buffer layer and a conversion layer can be introduced between the channel layer and the substrate according to actual conditions.

[0040] Among them, the channel layer is made of GaN material. The barrier layer is made of AlGaN material, with a thickness of generally 10-20 nm, and the Al component doped is generally 10%-30%. The barrier layer is used to reduce the lattice mismatch and thermal expansion coefficient difference between the substrate and the active layer material, and reduce the defect density. The passivation layer uses but is not limited to Si3N4 to protect the device surface. The p-type doped layer is generally p-type GaN formed by Mg doping, with a thickness of generally 50-100 nm, and the Mg doping concentration is generally 1018cm -3 Up to 1020 cm -3 The p-type doped layer can deplete the two-dimensional electron gas in the channel layer 2 to achieve a “normally off” state of the GaN device under zero gate-source bias.

[0041] It will be appreciated by those skilled in the art that the doping concentration, doped metal elements and thickness in the p-type doping layer and the barrier layer include but are not limited to the above, and may be selected differently according to actual needs. In addition, by precisely controlling the Mg and Al doping concentrations in the p-type doping layer and the AlGaN barrier layer, the formation and migration of 2DEG can be optimized.

[0042] S13. Determine the growth region of the source and the drain on the p-type doping layer; remove the p-type doping layer in the growth region; after depositing a metal layer on the surface of the barrier layer, anneal to form the source and the drain.

[0043] S14. Determine a gate region on the p-type doped layer, form an insulating layer in the gate region within the front-end structure, and form a gate region with a closed frame structure on the surface of the insulating layer through photolithography and etching techniques, and finally deposit a gate metal in the gate region to obtain a gate.

[0044] S15. Use a plasma enhanced chemical vapor deposition p-type doping layer for passivation and protection, and then use fluorine ion implantation to isolate the device. After determining the pad area, remove the p-type doping layer and deposit the pad metal electrode.

[0045] In this embodiment, the electrical isolation effect and the gate control capability can be optimized by adjusting the gate thickness and the insulating layer thickness.

[0046] In summary, in the GaN HEMT with the above-mentioned gate structure, the movement of photogenerated carriers in the gate region is strictly restricted, reducing their impact on the gate surface state and trap state. This optimization not only significantly reduces the gate leakage current caused by photogenerated carriers, but also improves the overall stability and reliability of the device under illumination conditions. Through this thorough isolation measure, effective control of photogenerated carriers is achieved, minimizing their impact on the gate surface state and trap state. Therefore, not only is the reliability of the device enhanced in optoelectronic applications, but it also exhibits excellent stability and durability in non-photoelectric environments.

[0047] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A GaN transistor structure, characterized in that: include: A gate having a closed frame structure; The gate surrounds the source and isolates the source from the drain.

2. The GaN transistor structure according to claim 1, wherein: The gate, the source and the drain are all located in the active area.

3. The GaN transistor structure according to claim 1, wherein: The active region is located between the source and the drain; Part of the gate extends into the inactive region.

4. The GaN transistor structure according to claim 1, wherein: The gate is made of at least one of titanium, aluminum and tungsten.

5. The GaN transistor structure according to claim 1, wherein: The gate is deposited on the surface of the insulating layer, and the insulating layer is located on the gate region.

6. The GaN transistor structure according to claim 1, wherein: The gate is in direct contact with the p-type doped layer, the metal layer and / or the insulating layer.

7. The GaN transistor structure according to claim 1, wherein: The GaN transistors include: p-GaN HEMT, GaN HEMT, MIS-HEMT and GaN MOSFET.

8. A method for preparing a GaN transistor structure, characterized in that: The preparation method comprises: Provide front-end structure; forming an insulating layer on a gate region of the front-end structure; forming a closed groove on the insulating layer; A gate metal is deposited in the groove to form a gate, which surrounds the source and isolates the source from the drain.

9. The method for preparing a GaN transistor structure according to claim 8, characterized in that: The provision of the front-end structure comprises: providing a substrate; A channel layer, a barrier layer, a passivation layer, and a p-type doping layer are sequentially stacked on the substrate; Determining growth regions of a source electrode and a drain electrode on the p-type doped layer; removing the p-type doped layer in the growth region; A metal layer is deposited on the surface of the barrier layer to form the source electrode and the drain electrode.

10. The method for preparing a GaN transistor structure according to claim 9, characterized in that: After depositing gate metal in the groove to form a gate, the method further comprises: Use plasma enhanced chemical vapor deposition of p-type doped layers for passivation and protection; Device isolation using fluoride ion implantation; Determine the pad area, remove the p-type doped layer and deposit the pad metal electrode.

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