LED epitaxial wafer, LED chip and preparation method of LED epitaxial wafer

Abstract

The invention provides an LED epitaxial wafer, an LED chip and a preparation method of the LED epitaxial wafer, and belongs to the technical field of light emitting diodes, the LED epitaxial wafer comprises a substrate and an epitaxial layer, the epitaxial layer comprises an n-type electronic layer, an n-type electronic barrier layer, an active layer, a p-type hole barrier layer, a p-type hole layer and a p-type window layer which are sequentially stacked, the p-type window layer comprises two tunnel junction structures and superlattice units which are clamped between the two tunnel junction structures and are periodically distributed in the stacking direction, each tunnel junction structure comprises a p-type doped InP sub-layer, an undoped InP sub-layer and an n-type doped InP sub-layer which are sequentially stacked, and each superlattice unit comprises an Al < x > P sub-layer and a Ga < 1-x > P sub-layer which are sequentially stacked. The tunnel junction structure and the superlattice structure formed by the superlattice units are introduced into the p-type window layer, so that the injection efficiency of current carriers can be improved, the resistance can be reduced, and the current expansion capability can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of light emitting diodes, and in particular to an LED epitaxial wafer, an LED chip and a method for preparing the LED epitaxial wafer. Background Art

[0002] In recent years, AlGaInP quaternary high-brightness light emitting diodes (LEDs) have been widely used. Compared with traditional GaP, GaAs and GaAlAs materials, this material has the advantages of wide direct transition band gap, high luminous efficiency, strong current carrying capacity, good stability and good temperature resistance. It plays an increasingly important role in signal lights, interior and exterior indicator lights for vehicles, traffic lights, mobile phones, electronic instruments, indoor and outdoor displays, information processing, communications and other fields.

[0003] The common structure of the current AlGaInP quaternary high-brightness light-emitting diode includes substrate, DBR Bragg reflector, n-type electron layer, n-type electron blocking layer, active layer, p-type hole blocking layer, p-type electron layer, and p-type window layer, among which the main component of the p-type window layer is GaP doped with Mg, which mainly acts as a current spreading layer.

[0004] However, when the light-emitting diode is working, the current is expanded laterally through the p-type window layer, and the current is injected into the active layer in the process. Since the current expansion capacity of the p-type window layer, whose main component is GaP, is limited, the current density of the p-type current expansion layer is higher near the bottom of the p-type electrode, while the current density of the area farther from the p-type electrode is lower, resulting in low overall current injection efficiency, which reduces the light extraction efficiency of the LED. In addition, the thickness of the p-type window layer, whose main component is GaP, is usually set to be relatively thick, which absorbs the emitted light to a greater extent, further reducing the light extraction efficiency of the light-emitting diode. Summary of the invention

[0005] Based on this, the purpose of the present invention is to provide an LED epitaxial wafer, an LED chip and a method for preparing an LED epitaxial wafer, aiming to innovatively design the p-type window layer to improve the current injection efficiency of the p-type window layer and reduce the light absorption degree of the p-type window layer, so as to achieve the purpose of improving the light extraction efficiency of the light-emitting diode.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides an LED epitaxial wafer, comprising a substrate and an epitaxial layer, wherein the epitaxial layer is arranged on one side of the substrate, the epitaxial layer comprises an n-type electron layer, an n-type electron blocking layer, an active layer, a p-type hole blocking layer, a p-type hole layer and a p-type window layer stacked in sequence, the p-type window layer comprises two tunnel junction structures and a superlattice unit periodically distributed along a stacking direction and sandwiched between the two tunnel junction structures, the tunnel junction structure comprises a p-type doped InP sublayer, an undoped InP sublayer, and an n-type doped InP sublayer stacked in sequence, and the superlattice unit comprises an Al2O3 stacked in sequence. x P sublayer and Ga 1-x P sublayer, where the value range of x is 0.5≤x<1.

[0007] Furthermore, the Al x The P sublayer and the Ga 1-x The doping sources of the P sublayer are Mg or Zn.

[0008] Furthermore, the Al x The P sublayer and the Ga 1-x The concentration of the doping source of the P sublayer is 5.0×10 18 atoms / cm 3 ~1.0×10 20 atoms / cm 3 .

[0009] Furthermore, the thickness of the superlattice unit is 50nm~100nm.

[0010] Furthermore, the doping source of the p-type doped InP sublayer is Mg, and the doping source of the n-type doped InP sublayer is Si.

[0011] Furthermore, the concentration of the doping source of the p-type doped InP sublayer is 1.0×10 19 atoms / cm 3 ~1.0×10 20 atoms / cm 3 The concentration of the doping source of the n-type doped InP sublayer is 1.0×10 17 atoms / cm 3 ~1.0×10 19 atoms / cm 3 .

[0012] Furthermore, the thickness of the p-type doped InP sublayer is 10 nm to 50 nm, the thickness of the undoped InP sublayer is 10 nm to 50 nm, and the thickness of the n-type doped InP sublayer is 10 nm to 50 nm.

[0013] Furthermore, the period number of the superlattice unit is 2-10.

[0014] In a second aspect, the present invention further provides an LED chip, comprising the aforementioned LED epitaxial wafer, and connecting electrodes formed on the LED epitaxial wafer.

[0015] In a third aspect, the present invention further provides a method for preparing an LED epitaxial wafer, comprising the following steps: providing a substrate; growing an n-type electron layer on the substrate; growing an n-type electron blocking layer on the n-type electron layer; growing an active layer on the n-type electron blocking layer; growing a p-type hole blocking layer on the active layer; growing a p-type hole layer on the p-type hole blocking layer; A p-type window layer is grown on the p-type hole layer, wherein the p-type window layer includes two tunnel junction structures and a superlattice unit periodically distributed along the stacking direction and sandwiched between the two tunnel junction structures, the tunnel junction structure includes a p-type doped InP sublayer, an undoped InP sublayer, and an n-type doped InP sublayer stacked in sequence, and the superlattice unit includes an Al x P sublayer and Ga 1-x P sublayer, the value range of x is 0.5≤x<1.

[0016] The beneficial effects of the present invention include at least: by setting a tunnel junction structure, utilizing the tunnel effect of the tunnel junction structure to improve the injection efficiency of carriers, so that more carriers can pass through the p-type window layer and enter the interior of the device; at the same time, by setting a superlattice structure formed by a superlattice unit, utilizing the special band structure and carrier transport characteristics of the superlattice structure, the expansion and distribution of carriers in the p-type window layer can be further promoted, thereby helping to reduce the accumulation of carriers in the p-type window layer, achieving the purpose of reducing resistance and improving current expansion capability. Compared with the p-type window layer whose main component is GaP, which usually requires a thicker thickness to ensure sufficient current expansion capability and photoelectric conversion efficiency, the present application can achieve the same performance under a thinner p-type window layer by introducing a tunnel junction structure that can improve the carrier injection efficiency, and a superlattice structure formed by a superlattice unit that can optimize the transmission path and distribution state of the carriers, thereby achieving the purpose of thinning the thickness of the p-type window layer, thereby reducing the resistance and cost of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the structure of an LED epitaxial wafer in one embodiment of the present invention; Figure 2is a schematic structural diagram of a p-type window layer in one embodiment of the present invention; Figure 3 is a flow chart of a method for preparing an LED epitaxial wafer in one embodiment of the present invention; Description of main component symbols: Substrate 100, buffer layer 110, DBR reflective layer 120, epitaxial layer 200, n-type electron layer 210, n-type electron blocking layer 220, active layer 230, p-type hole blocking layer 240, p-type hole layer 250, p-type window layer 260, p-type contact layer 270; Tunnel junction structure 261, p-type doped InP sublayer 2611, undoped InP sublayer 2612, n-type doped InP sublayer 2613; Superlattice unit 262, Al x P sublayer 2621, Ga 1-x P sublayer 2622; The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0018] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0019] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0021] AlGaInP material is a wide bandgap material with the property of direct transition, high composite luminescence efficiency, and the bandgap width can be continuously adjusted with the change of In component, thereby realizing high-brightness luminescence of LED in the ultra-wide wavelength range of 560nm~650nm from red light to blue-green light. In addition, it can also transition from direct band gap to indirect band gap, with an energy level range of 1.9eV~2.3eV.

[0022] Based on the content in the background technology, the main component of the p-type window layer of the traditional light-emitting diode prepared based on AlGaInP material is GaP doped with Mg. When the light-emitting diode is working, the current is expanded laterally through the p-type window layer, thereby injecting the current into the active layer. However, the p-type window layer whose main component is GaP has limited current expansion capability, so that the current density of the p-type window layer in the area near the bottom of the p-type electrode is higher, while the current density of the area far from the p-type electrode is lower, which ultimately leads to low overall current injection efficiency and reduces the light extraction efficiency of the LED. Moreover, in order to provide better current distribution and reduce current aggregation, the thickness of the p-type window layer whose main component is GaP is usually set to be relatively thick, resulting in a greater degree of absorption of the outgoing light by the p-type window layer, further reducing the light extraction efficiency of the light-emitting diode.

[0023] Based on this, the present application provides an LED epitaxial wafer, an LED chip and a method for preparing an LED epitaxial wafer, by designing the p-type window layer as a tunnel junction structure with low resistance and high conductivity and tunneling effect on both sides, and a structure of periodically distributed superlattice units in the middle, so as to improve the photoelectric conversion efficiency and current expansion effect. At the same time, the thickness of the p-type window layer can be thinned, and the light absorption effect of the p-type window layer can be reduced, so as to achieve the purpose of improving the light extraction efficiency of the light-emitting diode.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] First, please refer to Figure 1 and Figure 2, an LED epitaxial wafer provided by an embodiment of the present invention, includes a substrate 100, an epitaxial layer 200, the epitaxial layer 200 is arranged on one side of the substrate 100, the epitaxial layer 200 includes an n-type electron layer 210, an n-type electron blocking layer 220, an active layer 230, a p-type hole blocking layer 240, a p-type hole layer 250 and a p-type window layer 260 stacked in sequence, the p-type window layer 260 includes two tunnel junction structures 261 and a superlattice unit 262 periodically distributed along the stacking direction and sandwiched between the two tunnel junction structures 261, the tunnel junction structure 261 includes a p-type doped InP sublayer 2611, an undoped InP sublayer 2612, and an n-type doped InP sublayer 2613 stacked in sequence, and the superlattice unit 262 includes an Al2O3 stacked in sequence. x P sublayer 2621 and Ga 1-x P sublayer 2622.

[0026] In this embodiment, when growing the superlattice unit 262, in order to maintain the continuity of the superlattice unit 262 and reduce interface defects, it is necessary to ensure that the Al x P sublayer 2621 and Ga 1-x The lattice constants between the P sublayers 2622 are matched or close. Preferably, the value range of x is set to 0.5≤x<1, so as to ensure that the lattice mismatch of the entire superlattice structure is minimized.

[0027] It should be noted that the substrate 100 can be any one or any combination of a sapphire substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium oxide substrate, and a gallium arsenide substrate. In addition, since the AlGaInP lattice perfectly matches the lattice of the gallium arsenide substrate, high-quality LED epitaxial wafers can be produced on the gallium arsenide substrate, so the substrate 100 is preferably a gallium arsenide substrate.

[0028] It should also be noted that the n-type electron layer 210 can be any one of a Si-doped AlGaInP electron layer, a Si-doped AlInP electron layer, or a combination of the two. The n-type electron blocking layer 220 can be an undoped AlGaInP electron blocking layer, and the active layer 230 can be a multi-quantum well structure, for example, an active layer in which GaInP semiconductor layers and AlGaInP semiconductor layers are alternately arranged, wherein the bandgap width of the AlGaInP material can be changed by changing the In component.

[0029] It should also be noted that the p-type hole blocking layer 240 is an undoped hole blocking layer. Optionally, the p-type hole blocking layer 240 can be an undoped AlGaInP hole blocking layer, and the p-type hole layer 250 can be a Mg-doped AlInP hole layer or a Zn-doped AlInP hole layer.

[0030] In this embodiment, the tunnel junction structure 261 can improve the injection efficiency of carriers through the tunnel effect, so that more carriers can pass through the p-type window layer 260 into the device, and the superlattice structure formed by the superlattice unit 262 can further promote the expansion and distribution of carriers in the p-type window layer 260 through its special band structure and carrier transmission characteristics. Such expansion and distribution help to reduce the accumulation of carriers in the p-type window layer 260, reduce resistance, and thus improve the current expansion capability. At the same time, in the traditional structure, the p-type window layer whose main component is GaP usually requires a thicker thickness to ensure sufficient current expansion capability and photoelectric conversion efficiency. However, a thicker p-type window layer 260 will increase the resistance and cost of the device. However, the present application can achieve the same performance with a thinner p-type window layer 260 by introducing a tunnel junction structure 261 that can improve the carrier injection efficiency and a superlattice structure formed by the superlattice unit 262 that can optimize the transmission path and distribution state of the carriers, thereby achieving the purpose of thinning the thickness of the p-type window layer 260.

[0031] In some optional embodiments, Al x P sublayer 2621 and Ga 1-x The doping source of the P sublayer 2622 is Mg or Zn.

[0032] Due to Al x P and Ga 1-x As a semiconductor material, the doping concentration of P directly affects the key physical parameters of the material, such as conductivity, band gap and carrier mobility. In order to ensure that the material has suitable electrical and optical properties, and to make Al x P and Ga 1-x The superlattice structure formed by P can achieve better optimization of the carrier transmission path and distribution state. In some optional embodiments, Al x P sublayer 2621 and Ga 1-x The concentration of the doping source of the P sublayer 2622 is controlled at 5.0×10 18 atoms / cm 3 ~1.0×10 20 atoms / cm 3 within the range.

[0033] In some optional embodiments, the thickness of the superlattice unit 262 is 50 nm-100 nm.

[0034] In some optional embodiments, the doping source of the p-type doped InP sublayer 2611 is Mg, and the doping source of the n-type doped InP sublayer 2613 is Si.

[0035] As part of the semiconductor device, the p-type doped InP sublayer 2611 and the n-type doped InP sublayer 2613 need to have sufficient conductivity to support the transport of carriers, ensuring that the p-type doped InP sublayer 2611 has an appropriate hole concentration and mobility, and the n-type doped InP sublayer 2613 has a sufficient electron concentration and mobility; at the same time, the p-type doped InP sublayer 2611 and the n-type doped InP sublayer 2613 also need to match other material layers, and the interface quality and carrier transport efficiency between different material layers need to be ensured in the process of forming the epitaxial layer. To this end, in some optional embodiments, the concentration of the doping source of the p-type doped InP sublayer 2611 is controlled to 1.0×10 19 atoms / cm 3 ~1.0×10 20 atoms / cm 3 In the range of 1.0×10 17 atoms / cm 3 ~1.0×10 19 atoms / cm 3 within the range.

[0036] In some optional embodiments, the thickness of the p-type doped InP sublayer 2611 is 10 nm to 50 nm, the thickness of the undoped InP sublayer 2612 is 10 nm to 50 nm, and the thickness of the n-type doped InP sublayer 2613 is 10 nm to 50 nm.

[0037] In some optional embodiments, the number of periods of the superlattice unit 262 is 2-10.

[0038] In a second aspect, the present invention further provides an LED chip, comprising the aforementioned LED epitaxial wafer, and an n-type electrode and a p-type electrode formed on the LED epitaxial wafer.

[0039] Exemplarily, the structure of the LED chip is a face-up structure, including a GaAs substrate, an epitaxial layer 200 grown on the GaAs substrate, and an n-type electrode and a p-type electrode connected to the epitaxial layer 200 .

[0040] Specifically, the epitaxial layer 200 includes an n-type electron layer 210, an n-type electron blocking layer 220, an active layer 230, a p-type hole blocking layer 240, a p-type hole layer 250 and a p-type window layer 260 stacked in sequence, the p-type window layer 260 includes two tunnel junction structures 261 and a superlattice unit 262 periodically distributed along the stacking direction and sandwiched between the two tunnel junction structures 261, the tunnel junction structure 261 includes a p-type doped InP sublayer 2611, an undoped InP sublayer 2612, and an n-type doped InP sublayer 2613 stacked in sequence, and the superlattice unit 262 includes an Al2O3 stacked in sequence. x P sublayer 2621 and Ga 1-x P sublayer 2622, where the value range of x is 0.5≤x<1.

[0041] In some optional embodiments, such as Figure 1 As shown, a buffer layer 110 is grown between the GaAs substrate and the n-type electron layer 210 . The buffer layer 110 may be a Si-doped GaAs buffer layer, the purpose of which is to improve the lattice defects of the GaAs substrate to facilitate subsequent epitaxial deposition.

[0042] In some optional embodiments, such as Figure 1 As shown, in order to prevent the light emitted by the active layer 230 from being absorbed by the GaAs substrate, a DBR reflective layer 120 is grown between the buffer layer 110 and the n-type electron layer 210. The DBR reflective layer 120 can be a Si-doped AlAs / AlGaAs reflective layer. By alternating the growth of AlAs and AlGaAs materials, the AlAs and AlGaAs materials with different refractive indices reflect the light, thereby effectively improving the brightness of the LED.

[0043] Thirdly, Figure 3 As shown, the embodiment of the present invention further provides a method for preparing the aforementioned LED epitaxial wafer, which specifically includes steps S10 to S70: Step S10, providing a substrate 100, the substrate 100 can be any one or any combination of a sapphire substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium oxide substrate, and a gallium arsenide substrate. Since the AlGaInP lattice perfectly matches the lattice of the gallium arsenide substrate, high-quality LED epitaxial wafers can be produced on the gallium arsenide substrate, and the gallium arsenide substrate preparation process is mature, has high stability, and has a high cost performance, so the substrate 100 is preferably a gallium arsenide substrate.

[0044] Step S20, growing an n-type electron layer 210 on the substrate 100, the n-type electron layer 210 is mainly used to provide free electrons, so as to generate radiation recombination with holes in the p-type layer to emit light. Optionally, the n-type electron layer 210 can be selected from any one of Si-doped AlGaInP electron layer and Si-doped AlInP electron layer or a combination of the two.

[0045] Exemplarily, the n-type electronic layer 210 is a Si-doped AlInP electronic layer, and the specific deposition process thereof using metal organic chemical vapor deposition (MOCVD) technology is as follows: the temperature of the reaction chamber is controlled at 650°C to 750°C, TMAl (trimethylaluminum) is used as the aluminum source, TMIn (trimethylindium) is used as the indium source, PH3 (phosphine) is used as the phosphorus source, Si2H6 (disilane) is used as the dopant, and the Si doping concentration is 1.0×10 17 atoms / cm 3 ~6.0×10 19 atoms / cm 3 .

[0046] Step S30, growing an n-type electron blocking layer 220 on the n-type electron layer 210, the n-type electron blocking layer 220 is mainly used to confine electrons in the active layer 230, thereby blocking electron leakage, so as to improve the carrier injection efficiency and the photoelectric conversion efficiency of the device. The n-type electron blocking layer 220 is undoped, and optionally, the n-type electron blocking layer 220 can be an undoped AlGaInP electron blocking layer.

[0047] Exemplarily, the specific deposition process of the undoped AlGaInP electron blocking layer using metal organic chemical vapor deposition (MOCVD) technology is as follows: the reaction chamber temperature is controlled at 650°C to 750°C, TMAl (trimethylaluminum) is used as the aluminum source, TMGa (trimethylgallium) is used as the gallium source, TMIn (trimethylindium) is used as the indium source, and PH3 (phosphine) is used as the phosphorus source, and the growth thickness of the deposited undoped AlGaInP electron blocking layer is controlled to be 20nm to 200nm.

[0048] Step S40, growing an active layer 230 on the n-type electron blocking layer 220, the active layer 230 allows electrons and holes to meet in a smaller space to generate radiation recombination and light emission. Optionally, the active layer 230 can be an active layer of GaInP / AlGaInP alternately arranged, wherein the bandgap width of the AlGaInP material can be changed by changing the Al component.

[0049] Exemplarily, the specific deposition process of the alternatingly arranged GaInP / AlGaInP active layer using metal organic chemical vapor deposition (MOCVD) technology is as follows: the reaction chamber temperature is controlled at 620°C to 720°C, the reaction chamber pressure is controlled at 40mbar to 60mbar, TMAl (trimethylaluminum) is used as the aluminum source, TMGa (trimethylgallium) is used as the gallium source, TMIn (trimethylindium) is used as the indium source, and PH3 (phosphine) is used as the phosphorus source. An AlGaInP barrier layer with a thickness of 30Å-80Å is first grown, and then the Al source is turned off to grow a GaInP well layer with a thickness of 60Å-200Å, and then the preparation process of the AlGaInP barrier layer and the GaInP well layer is repeated to obtain 8 to 15 periodically stacked and alternately grown GaInP / AlGaInP active layers.

[0050] Step S50, growing a p-type hole blocking layer 240 on the active layer 230, the p-type hole blocking layer 240 is mainly used to limit the diffusion of holes from the p-type region to the n-type region, while allowing electrons to pass through, thereby improving the injection efficiency of carriers and the overall performance of the device. The p-type hole blocking layer 240 is an undoped hole blocking layer, and optionally, the p-type hole blocking layer 240 can be an undoped AlGaInP hole blocking layer.

[0051] Exemplarily, the specific deposition process of the undoped AlGaInP hole blocking layer using metal organic chemical vapor deposition (MOCVD) technology is as follows: the reaction chamber temperature is controlled at 650°C to 750°C, TMAl (trimethylaluminum) is used as the aluminum source, TMGa (trimethylgallium) is used as the gallium source, TMIn (trimethylindium) is used as the indium source, PH3 (phosphine) is used as the phosphorus source, and the thickness of the grown undoped AlGaInP hole blocking layer is controlled at 20nm to 2000nm.

[0052] Step S60: grow a p-type hole layer 250 on the p-type hole blocking layer 240. The p-type hole layer 250 is mainly used to provide holes, so as to generate radiation recombination light with free electrons in the n-type layer. Optionally, the p-type hole layer 250 can be a Mg-doped AlInP hole layer or a Zn-doped AlInP hole layer.

[0053] For example, the specific deposition process of the Mg-doped AlInP vacancy layer using metal organic chemical vapor deposition (MOCVD) technology is as follows: the reaction chamber temperature is controlled at 650°C to 750°C, TMAl (trimethylaluminum) is used as the aluminum source, TMIn (trimethylindium) is used as the indium source, PH3 (phosphine) is used as the phosphorus source, CP2Mg (dipentyl magnesium) is used as the dopant, and the Mg doping concentration is 1.0×10 17 atoms / cm 3 ~1.0×1021 atoms / cm 3 , the thickness of the grown Mg-doped AlInP vacancy layer is controlled to be between 100 nm and 550 nm.

[0054] Step S70 , growing a p-type window layer 260 on the p-type hole layer 250 .

[0055] Specifically, Figure 2 As shown, the p-type window layer 260 includes two tunnel junction structures 261 and a superlattice unit 262 periodically distributed along the stacking direction sandwiched between the two tunnel junction structures 261. The tunnel junction structure 261 includes a p-type doped InP sublayer 2611, an undoped InP sublayer 2612, and an n-type doped InP sublayer 2613 stacked in sequence. The superlattice unit 262 includes an Al x P sublayer 2621 and Ga 1-x P sublayer 2622, where the value range of x is 0.5≤x<1.

[0056] For example, the specific deposition process of the p-type window layer 260 using metal organic chemical vapor deposition (MOCVD) technology is: Step S71: The temperature of the reaction chamber is controlled at 650°C to 800°C, the pressure of the reaction chamber is controlled at 40 mbar to 60 mbar, TMAl (trimethylaluminum) is used as the aluminum source, TMIn (trimethylindium) is used as the indium source, PH3 (phosphine) is used as the phosphorus source, CP2Mg (dipentyl magnesium) is used as the dopant, and the Mg doping concentration is 1.0×10 19 atoms / cm 3 ~1.0×10 20 atoms / cm 3 , growing a p-type doped InP sublayer 2611 of a certain thickness; Step S72: stop introducing CP2Mg (dipentyl magnesium) to grow an undoped InP sublayer 2612 of a certain thickness; Step S73: Si2H6 (disilane) is introduced as a dopant, wherein the Si doping concentration is 1.0×10 17 atoms / cm 3 ~1.0×10 19 atoms / cm 3 , growing an n-type doped InP sublayer 2613 of a certain thickness; Step S74: TMAl (trimethylaluminum) is used as the aluminum source, PH3 (phosphine) is used as the phosphorus source, CP2Mg (dipentyl magnesium) is used as the dopant, and the Mg doping concentration is 5.0×10 18 atoms / cm 3 ~1.0×10 20atoms / cm 3 , grow a certain thickness of Al x P sublayer 2621; Step S75: Stop introducing TMAl (trimethylaluminum) and grow Ga to a certain thickness 1-x P sublayer 2622; Step S76: Repeat steps S74 and S75 until 2 to 10 periodically stacked and alternately grown Al layers with a total thickness of 50 nm to 100 nm are grown. x P sublayer 2621 and Ga 1-x P sublayer 2622; Step S77: Repeat steps S71 to S73 once.

[0057] In some optional embodiments, the following step S11 is further included between step S10 and step S20: Step S11: growing a buffer layer 110 on the substrate 100. The purpose of the buffer layer 110 is to provide an intermediate layer between two different materials to improve the interface characteristics between them, reduce defects, and improve the stability and performance of the overall structure. Therefore, the buffer layer 110 needs to be determined according to the materials used for the substrate 100 and the n-type electron layer 210.

[0058] For example, the substrate 100 is a GaAs substrate, the n-type electron layer 210 is a Si-doped AlInP electron layer, and the buffer layer 110 is a Si-doped GaAs buffer layer. The specific deposition process using metal organic chemical vapor deposition (MOCVD) technology is as follows: the reaction chamber temperature is controlled at 650° C. to 750° C., TMGa (trimethylgallium) is used as a gallium source, AsH3 (arsenic) is used as an arsenic source, Si2H6 (disilane) is used as a dopant, and the Si doping concentration is 2.0×10 16 atoms / cm 3 ~7.0×10 20 atoms / cm 3 , grow a Si-doped GaAs buffer layer of a certain thickness.

[0059] In some optional embodiments, the following step S12 is further included between steps S11 and S20: Step S12: growing a DBR reflective layer 120 on the buffer layer 110. The DBR reflective layer 120 uses two materials with different refractive indices to reflect light, thereby preventing the light emitted by the active layer 230 from being absorbed by the GaAs substrate, thereby effectively improving the brightness of the LED. Optionally, the DBR reflective layer 120 can be a Si-doped AlAs / AlGaAs reflective layer.

[0060] Specifically, the Si-doped AlAs / AlGaAs reflective layer is deposited by metal organic chemical vapor deposition. The specific deposition process of MOCVD technology is as follows: the reaction chamber temperature is controlled at 650℃~750℃, TMAl (trimethylaluminum) is used as the aluminum source, AsH3 (arsenic hydrogen) is used as the arsenic source, Si2H6 (disilane) is used as the dopant, and the Si doping concentration is 2.0×10 16 atoms / cm 3 ~8.0×10 19 atoms / cm 3 , grow an AlAs layer of a certain thickness; then, introduce TMGa (trimethylgallium) as a gallium source to grow an AlGaAs layer of a certain thickness; finally, repeat the aforementioned steps of growing AlAs layers and AlGaAs layers until a periodically stacked and alternately grown DBR reflective layer 120 with a total thickness of 2.1 microns is grown.

[0061] In some optional embodiments, the following step S61 is further included between step S60 and step S70: Step S61: growing a p-type transition layer on the p-type hole layer 250. The p-type transition layer is mainly used to improve the electronic structure and interface characteristics of the LED, thereby improving the performance of the LED. Optionally, the p-type transition layer can be a Mg-doped AlGaInP transition layer or a Zn-doped AlGaInP transition layer, and the composition gradually transitions from AlInP to GaInP.

[0062] For example, the specific deposition process of the Mg-doped AlGaInP transition layer using metal organic chemical vapor deposition (MOCVD) technology is as follows: the reaction chamber temperature is controlled at 650°C to 750°C, the rotation speed is controlled at 6 to 10 r / s, TMAl (trimethylaluminum) is used as the aluminum source, TMGa (trimethylgallium) is used as the gallium source, TMIn (trimethylindium) is used as the indium source, PH3 (phosphine) is used as the phosphorus source, CP2Mg (dipentyl magnesium) is used as the dopant, and the Mg doping concentration is 1.0×10 17 atoms / cm 3 ~1.0×10 21 atoms / cm 3 A p-type transition layer is grown whose composition gradually transitions from AlInP to GaInP, and the thickness of the p-type transition layer is controlled in the range of 10nm~80nm.

[0063] In some optional embodiments, after step S70, step S80 is further included: Step S80: growing a p-type contact layer 270 on the p-type window layer 260. The p-type contact layer 270 is mainly used for ohmic contact to reduce contact resistance, thereby facilitating current conduction from the electrode input. Optionally, the p-type contact layer 270 can be a carbon-doped GaP contact layer.

[0064] For example, the specific deposition process of the carbon-doped GaP contact layer using metal organic chemical vapor deposition (MOCVD) technology is as follows: the reaction chamber temperature is controlled at 650°C to 680°C, TMGa (trimethylgallium) is used as the gallium source, PH3 (phosphine) is used as the phosphorus source, and the carbon doping concentration is 1.0×10 18 atoms / cm 3 ~1.0×10 20 atoms / cm 3 , the thickness of the p-type window layer 260 is controlled to be between 20 nm and 100 nm.

[0065] The present invention will be further described below with specific embodiments: Embodiment 1: The present embodiment provides an LED epitaxial wafer, which includes a substrate 100 and an epitaxial layer 200. The epitaxial layer 200 is arranged on one side of the substrate 100. The epitaxial layer 200 includes a buffer layer 110, a DBR reflective layer 120, an n-type electron layer 210, an n-type electron blocking layer 220, an active layer 230, a p-type hole blocking layer 240, a p-type hole layer 250, a p-type window layer 260, and a p-type contact layer 270, which are stacked in sequence. The p-type window layer 260 includes two tunnel junction structures 261 and a superlattice unit 262 periodically distributed along the stacking direction and sandwiched between the two tunnel junction structures 261. The tunnel junction structure 261 includes a p-type doped InP sublayer 2611, an undoped InP sublayer 2612, and an n-type doped InP sublayer 2613, which are stacked in sequence. The growth period of the superlattice unit 262 is 10, and the superlattice unit 262 includes Al2O3 stacked in sequence. x P sublayer 2621 and Ga 1-x The value range of x in the P sublayer 2622 is 0.5≤x≤0.9, and the concentration of the doping source Mg in the p-type doped InP sublayer 2611 is 1.0×10 19 atoms / cm 3 , the thickness of the p-type doped InP sublayer 2611 is 40 nm, the thickness of the undoped InP sublayer 2612 is 40 nm, and the concentration of the doping source Si of the n-type doped InP sublayer 2613 is 1.0×10 17 atoms / cm 3 The thickness of the n-type doped InP sublayer 2613 is 35 nm, and the Al x The concentration of the doping source Mg in the P sublayer 2621 is 5.0×1018 atoms / cm 3 , Al x The bandgap of the P sublayer 2621 is 2.15eV to 2.40eV. x The thickness of the P sublayer 2621 is 80 nm, and Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 5.0×10 18 atoms / cm 3 , Ga 1-x The bandgap of the P sublayer 2622 is 1.90 eV to 2.20 eV. 1-x The thickness of the P sublayer 2622 is 85 nm.

[0066] Embodiment 2: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the concentration of the doping source Si of the n-type doped InP sublayer 2613 is 1.0×10 18 atoms / cm 3 , Al x The concentration of the doping source Mg in the P sublayer 2621 is 7.0×10 18 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 7.0×10 18 atoms / cm 3 .

[0067] Embodiment three: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 5.0×10 19 atoms / cm 3 The concentration of the doping source Si in the n-type doped InP sublayer 2613 is 5.0×10 18 atoms / cm 3 , Al x The concentration of the doping source Mg in the P sublayer 2621 is 1.0×10 19 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 1.0×10 19 atoms / cm 3 .

[0068] Embodiment 4: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 5.5×10 19 atoms / cm 3 The concentration of the doping source Si in the n-type doped InP sublayer 2613 is 5.5×10 18 atoms / cm 3 , Al x The concentration of the doping source Mg in the P sublayer 2621 is 5.0×10 19 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 5.0×10 19 atoms / cm 3 .

[0069] Embodiment five: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 1.0×10 20 atoms / cm 3 The concentration of the doping source Si in the n-type doped InP sublayer 2613 is 1.0×10 19 atoms / cm 3 , Al x The concentration of the doping source Mg in the P sublayer 2621 is 1.0×10 20 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 1.0×10 20 atoms / cm 3 .

[0070] Embodiment six: This embodiment provides an LED epitaxial wafer. The difference from the LED epitaxial wafer provided in the first embodiment is that in this embodiment, Al x The thickness of the P sublayer 2621 is 85 nm, and Ga 1-x The thickness of the P sublayer 2622 is 90 nm.

[0071] Embodiment seven: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the sixth embodiment, in this embodiment, the concentration of the doping source Si of the n-type doped InP sublayer 2613 is 1.0×10 18 atoms / cm 3 , Al xThe concentration of the doping source Mg in the P sublayer 2621 is 7.0×10 18 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 7.0×10 18 atoms / cm 3 .

[0072] Embodiment eight: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the sixth embodiment, in this embodiment, the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 5.0×10 19 atoms / cm 3 The concentration of the doping source Si in the n-type doped InP sublayer 2613 is 5.0×10 18 atoms / cm 3 , Al x The concentration of the doping source Mg in the P sublayer 2621 is 1.0×10 19 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 1.0×10 19 atoms / cm 3 .

[0073] Embodiment nine: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the sixth embodiment, in this embodiment, the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 5.5×10 19 atoms / cm 3 The concentration of the doping source Si in the n-type doped InP sublayer 2613 is 5.5×10 18 atoms / cm 3 , Al x The concentration of the doping source Mg in the P sublayer 2621 is 5.0×10 19 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 5.0×10 19 atoms / cm 3 .

[0074] Embodiment ten: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the sixth embodiment, in this embodiment, the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 1.0×10 20 atoms / cm 3The concentration of the doping source Si in the n-type doped InP sublayer 2613 is 1.0×10 19 atoms / cm 3 , Al x The concentration of the doping source Mg in the P sublayer 2621 is 1.0×10 20 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 1.0×10 20 atoms / cm 3 .

[0075] Embodiment eleven: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 1.0×10 20 atoms / cm 3 , the thickness of the p-type doped InP sublayer 2611 is 50 nm, the thickness of the undoped InP sublayer 2612 is 50 nm, and the concentration of the doping source Si of the n-type doped InP sublayer 2613 is 1.0×10 19 atoms / cm 3 The thickness of the n-type doped InP sublayer 2613 is 45 nm, and the Al x The concentration of the doping source Mg in the P sublayer 2621 is 1.0×10 20 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 1.0×10 20 atoms / cm 3 .

[0076] Embodiment 12: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the eleventh embodiment, in this embodiment, the thickness of the p-type doped InP sublayer 2611 is 35nm, the thickness of the undoped InP sublayer 2612 is 35nm, the thickness of the n-type doped InP sublayer 2613 is 30nm, and the thickness of the Al x The concentration of the doping source Mg in the P sublayer 2621 is 1.0×10 20 atoms / cm 3 , Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 1.0×10 20 atoms / cm 3 .

[0077] Embodiment 13: This embodiment provides an LED epitaxial wafer. The difference from the LED epitaxial wafer provided in the eleventh embodiment is that in this embodiment, Al x The thickness of the P sublayer 2621 is 85 nm, and Ga 1-x The thickness of the P sublayer 2622 is 90 nm.

[0078] Embodiment 14: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the eleventh embodiment, in this embodiment, the thickness of the p-type doped InP sublayer 2611 is 35nm, the thickness of the undoped InP sublayer 2612 is 35nm, the thickness of the n-type doped InP sublayer 2613 is 30nm, and the thickness of the Al x The thickness of the P sublayer 2621 is 85 nm, and Ga 1-x The thickness of the P sublayer 2622 is 90 nm.

[0079] Embodiment 15: This embodiment provides an LED epitaxial wafer. The difference from the LED epitaxial wafer provided in the eleventh embodiment is that in this embodiment, the thickness of the p-type doped InP sublayer 2611 is 40nm, the thickness of the undoped InP sublayer 2612 is 40nm, the thickness of the n-type doped InP sublayer 2613 is 35nm, and the thickness of the Al x The thickness of the P sublayer 2621 is 90 nm, and Ga 1-x The thickness of the P sublayer 2622 is 95 nm.

[0080] Embodiment 16: This embodiment provides an LED epitaxial wafer. The difference from the LED epitaxial wafer provided in the eleventh embodiment is that in this embodiment, the thickness of the p-type doped InP sublayer 2611 is 40nm, the thickness of the undoped InP sublayer 2612 is 40nm, the thickness of the n-type doped InP sublayer 2613 is 35nm, and the thickness of the Al x The thickness of the P sublayer 2621 is 70 nm, and Ga 1-x The thickness of the P sublayer 2622 is 75 nm.

[0081] Comparative Example 1: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the value range of x is 0.45, and the concentration of the doping source Mg of the p-type doped InP sublayer 2611 is 5.0×10 19 atoms / cm 3 , the thickness of the p-type doped InP sublayer 2611 is 50 nm, the thickness of the undoped InP sublayer 2612 is 50 nm, and the concentration of the doping source Si of the n-type doped InP sublayer 2613 is 1.0×10 19atoms / cm 3 The thickness of the n-type doped InP sublayer 2613 is 45 nm, and the Al x The concentration of the doping source Mg in the P sublayer 2621 is 1.0×10 19 atoms / cm 3 , Al x The bandgap of the P sublayer 2621 is 2.10 eV, and the Al x The thickness of the P sublayer 2621 is 85 nm, and Ga 1-x The concentration of the doping source Mg in the P sublayer 2622 is 5.0×10 19 atoms / cm 3 , Ga 1-x The bandgap of the P sublayer 2622 is 1.93 eV, and Ga 1-x The thickness of the P sublayer 2622 is 90 nm.

[0082] Comparative Example 2: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the value range of x is 1.0, and the p-type window layer 260 includes two tunnel junction structures 261 and an Al2O3 layer sandwiched between the two tunnel junction structures 261. x The tunnel junction structure 261 includes a p-type doped InP sublayer 2611, an undoped InP sublayer 2612, an n-type doped InP sublayer 2613, and an Al x The bandgap of the P sublayer 2621 is 2.45 eV, and the Al x The thickness of the P sublayer 2621 is 3500 nm.

[0083] Comparative Example 3: This embodiment provides an LED epitaxial wafer. Different from the LED epitaxial wafer provided in the first embodiment, in this embodiment, the p-type window layer 260 is a p-type window layer whose main component is GaP, and the thickness of the p-type window layer 260 is 3000 nm.

[0084] The LED epitaxial wafers provided in Examples 1 to 16 and Comparative Examples 1 to 3 were tested under the same conditions to obtain the results of the luminous intensity obtained in each example, and the degree of improvement of the luminous intensity of Examples 1 to 16 and Comparative Examples 1 to 2 was obtained by taking the luminous intensity obtained in Comparative Example 3 as a reference. The specific data are shown in Table 1: Table 1

[0085] It can be seen from Table 1 that under the same test conditions, since the p-type window layer 260 in the LED epitaxial wafer provided in Examples 1 to 11 and Examples 13 to 16 of the present invention is arranged as two tunnel junction structures 261 and superlattice units 262 periodically distributed along the stacking direction and sandwiched between the two tunnel junction structures 261, compared with the p-type window layer in Comparative Example 3 whose main component is GaP, the thickness can be made thinner while achieving the same performance or higher performance.

[0086] It can be seen from the twelfth embodiment that when the p-type doped InP sublayer 2611, the n-type doped InP sublayer 2613, and the Al x P sublayer 2621, Ga 1-x When the doping concentration of the P sublayer 2622 is too high, compared with the p-type window layer in comparative example 3 whose main component is GaP, although the thickness of the p-type window layer 260 can be made thinner, the performance is reduced. This may be due to the excessively high doping concentration leading to a decrease in process stability and material quality, such as impurity diffusion and increased interface roughness.

[0087] It can be seen from Comparative Example 1 that when the value of x is less than 0.5, even if the p-type doped InP sublayer 2611, the n-type doped InP sublayer 2613, and the Al x P sublayer 2621, Ga 1-x When the doping concentration of the P sublayer 2622 is at a preferred value, compared with the p-type window layer whose main component is GaP in Comparative Example 3, although the thickness of the p-type window layer 260 can be made thinner, the performance degradation is relatively large. This may be because the lattice mismatch of the superlattice structure formed by the superlattice unit 262 is relatively large, resulting in poor growth quality of the superlattice structure and affecting device performance. It can be seen from Comparative Example 2 that when the value of x is 1.0, a superlattice structure cannot be formed. At this time, the thickness of the p-type window layer 260 needs to be set thicker, and the corresponding performance degradation is also relatively large.

[0088] It can be seen from the tenth and eleventh embodiments that when the thickness of the tunnel junction structure 261 is large, the performance is greatly degraded. This may be because the increase in the thickness of the tunnel junction causes the degradation of material quality and increases the resistance of the structure, thereby reducing the overall electro-optical conversion efficiency.

[0089] In summary, the present application arranges the p-type window layer 260 into two tunnel junction structures 261 and a superlattice unit 262 periodically distributed along the stacking direction sandwiched between the two tunnel junction structures 261, wherein the tunnel junction structure 261 includes a p-type doped InP sublayer 2611, an undoped InP sublayer 2612, and an n-type doped InP sublayer 2613 stacked in sequence, and the superlattice unit 262 includes an Al2O3 stacked in sequence. xP sublayer 2621 and Ga 1-x P sublayer 2622, the value range of x is 0.5≤x<1, and the tunnel junction structure 261 can improve the carrier injection efficiency through the tunnel effect, so that more carriers can pass through the p-type window layer 260 into the interior of the device, and the superlattice structure formed by the superlattice unit 262 can further promote the expansion and distribution of carriers in the p-type window layer 260 through its special band structure and carrier transport characteristics. This expansion and distribution helps to reduce the accumulation of carriers in the p-type window layer 260, reduce resistance, and thus improve current expansion capability. At the same time, the p-type window layer whose main component is GaP usually requires a thicker thickness to ensure sufficient current expansion capability and photoelectric conversion efficiency, which will increase the resistance and cost of the device. The present application introduces a tunnel junction structure 261 that can improve the carrier injection efficiency, and a superlattice structure formed by a superlattice unit 262 that can optimize the carrier transmission path and distribution state. It can achieve the same performance with a thinner p-type window layer 260, thereby achieving the purpose of thinning the thickness of the p-type window layer 260.

[0090] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0091] The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the protection scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. An LED epitaxial wafer, characterized in that: The LED epitaxial wafer comprises: substrate; An epitaxial layer is arranged on one side of the substrate, the epitaxial layer includes an n-type electron layer, an n-type electron blocking layer, an active layer, a p-type hole blocking layer, a p-type hole layer and a p-type window layer stacked in sequence, the p-type window layer includes two tunnel junction structures and a superlattice unit periodically distributed along the stacking direction and sandwiched between the two tunnel junction structures, the tunnel junction structure includes a p-type doped InP sublayer, an undoped InP sublayer, and an n-type doped InP sublayer stacked in sequence, and the superlattice unit includes an Al x P sublayer and Ga 1-x P sublayer; The value range of x is 0.5≤x<1.

2. The LED epitaxial wafer according to claim 1, characterized in that: The Al x The P sublayer and the Ga 1-x The doping sources of the P sublayer are Mg or Zn.

3. The LED epitaxial wafer according to claim 2, characterized in that: The Al x The P sublayer and the Ga 1-x The concentration of the doping source of the P sublayer is 5.0×10 18 atoms / cm 3 ~1.0×10 20 atoms / cm 3 .

4. The LED epitaxial wafer according to claim 1, characterized in that: The thickness of the superlattice unit is 50nm~100nm.

5. The LED epitaxial wafer according to claim 1, characterized in that: The doping source of the p-type doped InP sublayer is Mg, and the doping source of the n-type doped InP sublayer is Si.

6. The LED epitaxial wafer according to claim 5, characterized in that: The concentration of the doping source of the p-type doped InP sublayer is 1.0×10 19 atoms / cm 3 ~1.0×10 20 atoms / cm 3 The concentration of the doping source of the n-type doped InP sublayer is 1.0×10 17 atoms / cm 3 ~1.0×10 19 atoms / cm 3 .

7. The LED epitaxial wafer according to claim 1, characterized in that: The thickness of the p-type doped InP sublayer is 10nm-50nm, the thickness of the undoped InP sublayer is 10nm-50nm, and the thickness of the n-type doped InP sublayer is 10nm-50nm.

8. The LED epitaxial wafer according to any one of claims 1 to 7, characterized in that: The period number of the superlattice unit is 2-10.

9. An LED chip, characterized in that: It comprises the LED epitaxial wafer as claimed in any one of claims 1 to 8, and a connecting electrode formed on the LED epitaxial wafer.

10. A method for preparing an LED epitaxial wafer, characterized in that: The preparation method comprises the following steps: providing a substrate; growing an n-type electron layer on the substrate; growing an n-type electron blocking layer on the n-type electron layer; growing an active layer on the n-type electron blocking layer; growing a p-type hole blocking layer on the active layer; growing a p-type hole layer on the p-type hole blocking layer; A p-type window layer is grown on the p-type hole layer, wherein the p-type window layer includes two tunnel junction structures and a superlattice unit periodically distributed along the stacking direction and sandwiched between the two tunnel junction structures, the tunnel junction structure includes a p-type doped InP sublayer, an undoped InP sublayer, and an n-type doped InP sublayer stacked in sequence, and the superlattice unit includes an Al x P sublayer and Ga 1-x P sublayer, the value range of x is 0.5≤x<1.

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