Memory preparation method, memory, device and equipment

Abstract

The invention provides a memory preparation method, a memory, a device and equipment, and the method comprises the steps: forming a first semiconductor structure and a first active structure which are sequentially stacked on a substrate, and enabling the doping concentration of the first semiconductor structure to be the same as the doping concentration of a second active structure; ion implantation is carried out in the area, close to the first active structure, of the first semiconductor structure to form a BL structure located between the first semiconductor structure and the first active structure, and the first semiconductor structure, the BL structure and the first active structure are self-aligned in the BL area; forming a first memory based on the first active structure; reversing the first memory and removing the substrate to expose the first semiconductor structure; etching the first semiconductor structure in the BL region to form a second active structure; and forming a second memory based on the second active structure, the first source drain structure of the first memory and the second source drain structure of the second memory sharing the BL structure. The integration level of the memory can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a memory, a memory, a device and an apparatus. Background Art

[0002] Dynamic random access memory (DRAM) usually uses a transistor and a capacitor (1T1C) structure as the chip's storage unit. Through the continuous evolution of the architecture, the area of ​​DRAM storage unit is 4F. 2 (F is the feature size). However, as Moore's Law continues, the area shrinkage of traditional DRAM has reached a bottleneck. There is an urgent need for a method that can reduce the area of ​​DRAM storage cells and increase storage density. Summary of the invention

[0003] The present application provides a method for preparing a memory, a memory, a device and an apparatus, which can reduce the area of ​​a storage unit of the memory and improve the storage density and integration.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a memory, the method comprising: forming a stacked structure on a substrate, the stacked structure comprising: a first semiconductor structure and a first active structure stacked in sequence in a first direction, the doping concentration of the first semiconductor structure being the same as the doping concentration of the first active structure; performing ion implantation in a region close to the first active structure on the first semiconductor structure to form a bit line BL structure, the BL structure being located between the first semiconductor structure and the first active structure, the first semiconductor structure, the BL structure and the first active structure being self-aligned along the first direction in the BL region; forming a first memory based on the first active structure; flipping the first memory and removing the substrate to expose the first semiconductor structure; etching the first semiconductor structure in the BL region to form a second active structure; forming a second memory based on the second active structure, wherein the first source-drain structure in the first memory and the second source-drain structure in the second memory share the BL structure.

[0005] In one possible embodiment, a stacked structure is formed on a substrate, including: stacking a first material layer and a second material layer in sequence along a first direction on the substrate; etching the first material layer and the second material layer along a BL direction to form a first semiconductor structure and a second semiconductor structure; and etching the second semiconductor structure along a WL direction to form a first active structure.

[0006] In one possible implementation, ion implantation is performed in a region on the first semiconductor structure close to the first active structure to form a bit line BL structure, including: performing ion implantation on a region on the first semiconductor structure in the BL region close to the first active structure to form a third semiconductor structure in the BL region; and annealing the third semiconductor to form the BL structure.

[0007] In one possible implementation, a first memory is formed based on a first active structure, including: forming a first transistor based on the first active structure; forming a first capacitor structure on the first transistor; and a second memory is formed based on a second active structure, including: forming a second transistor based on the second active structure; and forming a second capacitor structure on the second transistor.

[0008] In one possible embodiment, a first transistor is formed based on a first active structure, including: forming a first gate structure based on the first active structure; removing the first gate structure in the BL region to form a first groove; depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of the first mask, and the first mask is located on the first active structure; removing the first mask to form a second groove; and forming a first source-drain structure in the second groove.

[0009] In a possible embodiment, the first gate structure includes a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, the height of the first gate electrode layer is lower than the height of the first gate dielectric layer; the first gate structure is removed in the BL region to form a first groove, including: forming a sacrificial layer on the first gate electrode layer located in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer located below the sacrificial layer to form a first groove.

[0010] In a possible implementation, forming a first capacitor structure on a first transistor includes: forming a first dielectric layer on a first source-drain structure; etching a first portion of the first dielectric layer to expose the first source-drain structure; and forming a first capacitor structure on the first source-drain structure.

[0011] In one possible implementation, a second transistor is formed based on the second active structure, including: forming a second gate structure based on the second active structure; removing the second gate structure in the BL region to form a third groove; depositing an insulating material on the second gate structure in the WL region and in the third groove to form a second insulating layer, wherein the upper surface of the second insulating layer is flush with the upper surface of the second mask, and the second mask is located on the second active structure; removing the second mask to form a fourth groove; and forming a second source-drain structure in the fourth groove.

[0012] In a second aspect, an embodiment of the present application provides a memory, which is manufactured using the preparation method described in the first aspect and any one of its embodiments, and includes: a BL structure; a first memory; a second memory, the second memory is arranged back to back with the first memory, and the first source-drain structure in the second memory and the second source-drain structure in the first memory share the BL structure.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a memory as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, a first semiconductor structure and a first active structure are formed on a substrate, and then ion implantation is performed in a region on the first semiconductor near the first active structure to form a BL structure located between the first semiconductor structure and the first active structure. The first semiconductor structure, the BL structure, and the second active structure are self-aligned in the BL region; then, based on the front active structure (first active structure), a first memory (front memory) is prepared; the front memory is flipped and the substrate is removed to expose the first semiconductor structure; then the first semiconductor structure is etched in the BL region to form a second active structure; finally, based on the second active structure, a second memory (back memory) is prepared. The present application ensures self-alignment of the front and back BLs by integrated molding of the BL region. Front and back integrated 4F is achieved through wafer bonding and flipping. 2 The equivalent area of ​​the memory is 2F. 2 , which is equivalent to reducing the area of ​​the memory unit of the memory and improving the storage density and integration of the memory. Moreover, the present application forms the BL structure by ion implantation, which is simple in steps and can save costs.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an implementation process of a method for preparing a memory in an embodiment of the present application;

[0019] Figure 2 A schematic top view of a memory in an embodiment of the present application;

[0020] Figures 3 to 24 This is a schematic diagram of the structure of the memory in the preparation process in the embodiment of the present application;

[0021] Fig.25 Schematic diagram of the structure of the memory in the embodiment of the present application.

[0022] The above pictures:

[0023] 10. Memory; 11. First transistor (front transistor); 111. First active structure; 112. First source-drain structure; 113. First gate structure; 1131. First gate dielectric layer; 1132. First gate electrode layer; 12. Second transistor; 121. Second active structure; 122. Second source-drain structure; 123. Second gate structure; 1231. Second gate dielectric layer; 1232. Second gate electrode layer; 13. Third insulating layer; 14. Wafer carrier; 20. Substrate; 21. First material layer; 22. Second material layer; 23. First mask; 24. Active structure ; 241: first semiconductor structure; 242: second semiconductor structure; 25, first shallow trench isolation structure; 26, third mask; 27, third semiconductor structure; 28, BL structure; 29, second shallow trench isolation structure; 30, isolation layer; 31, sacrificial layer; 32, first groove; 33, first oxide layer; 34, first insulating layer; 35, second groove; 36, first dielectric layer; 37, first capacitor structure; 38, second mask; 39, third shallow trench isolation structure; 40, second oxide layer; 41, second insulating layer; 42, second dielectric layer; 43, second capacitor structure. DETAILED DESCRIPTION

[0024] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0025] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size. With the continuous development of transistor technology, a flip-chip stacked transistor came into being. The active area of ​​the upper and lower layers of the same source transistors is formed by etching, and the flip-chip stacked transistor is made on the front and back of the wafer by flipping the wafer, which can overcome the shortcomings of the existing solution.

[0026] In DRAM, ferroelectric random access memory (FeRAM) or other memory, a storage unit may include a transistor and a capacitor structure, wherein the transistor is disposed on a substrate, the capacitor structure is located at an end of the transistor away from the substrate, and the transistor and the capacitor structure are electrically connected.

[0027] Take DRAM as an example. The basic structure of DRAM is 1T1C. Currently, there are three main types of DRAM. The first type of DRAM has an area of ​​8F. 2 , which is achieved by placing transistors and capacitors horizontally; the second type of DRAM has an area of ​​6F 2 By tilting the placement of transistors and capacitors, the arrangement density can be increased, thereby achieving a smaller integration area; the area of ​​the third DRAM is 4F 2 By placing transistors and capacitor structures vertically, the vertical volume is fully utilized to achieve smaller DRAM area scaling.

[0028] As integrated circuits continue to shrink in size, there is an urgent need for a method that can reduce the area of ​​a memory cell and increase storage density.

[0029] Based on this, an embodiment of the present application provides a method for preparing a memory, which can reduce the area of ​​a storage unit of the memory and improve the storage density and integration.

[0030] In some embodiments, the memory may include a plurality of memory cells, each of which may include a flip-stack transistor and a capacitance structure (capacitor), wherein the capacitance structure is electrically connected to the flip-stack transistor.

[0031] In some embodiments, the flip-stacked transistor may include a gate structure, a source structure, and a drain structure. The capacitor structure and the flip-stacked transistor may be electrically connected by the source structure of the flip-stacked transistor and the capacitor structure, or by the drain structure of the flip-stacked transistor and the capacitor structure. The flip-stacked transistor controls the writing, modification, or reading of information in the capacitor structure. That is, the flip-stacked transistor acts as a selection device (or a switching device) to control the writing, modification, or reading of information in the capacitor structure.

[0032] In some embodiments, the capacitor structure may include a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode. Exemplarily, the first electrode may be electrically connected to the drain structure of the flip-chip stack transistor, and the second electrode may be grounded.

[0033] In some embodiments, the memory cell may further include a plurality of word line (WL) structures and a plurality of bit line (BL) structures, wherein the WL structure may be connected to the gate structure of the flip-stack transistor to control the on and off of the flip-stack transistor. The BL structure may be connected to the source structure or the drain structure of the flip-stack transistor to write data into the capacitor structure connected to the flip-stack transistor when the flip-stack transistor is turned on.

[0034] In some embodiments, a flip-chip stacked transistor may include at least two transistors. Taking a first transistor and a second transistor as an example, the first transistor and the second transistor are arranged back to back, and the second active structure of the first transistor and the first active structure of the second transistor are formed by the same process. Therefore, it can be understood that the first transistor and the second transistor share an active structure.

[0035] In the embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor are transistors of the same type, such as vertical channel transistors (VCT), which may also be referred to as vertical gate-all-around transistors.

[0036] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a memory in an embodiment of the present application. Figure 1 As shown, the method for preparing the memory in the embodiment of the present application may include:

[0037] Step S110: forming a stacking structure on a substrate.

[0038] The stacked structure includes: a first semiconductor structure and a second active structure stacked in sequence in a first direction, the first semiconductor structure and the second active structure are self-aligned along the first direction in the WL region. The first direction is the growth direction of the substrate, that is, the direction of growth from the bottom to the top.

[0039] In some embodiments, the implementation process of step S110 can be divided into the following three steps: step one: stacking a first material layer and a second material layer in sequence along a first direction on a substrate; step two: etching the first material layer and the second material layer in the WL region to form a first semiconductor structure and a second semiconductor structure; step three: etching the second semiconductor structure in the BL region to form a first active structure.

[0040] In step 1, the first material layer and the second material layer are doped the same.

[0041] By way of example, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate.

[0042] It can be understood that the first material layer and the second material layer are doped in the same way. In this way, the first material layer and the second material layer with the same doping can be subsequently etched to serve as an active structure shared by the front transistor (first transistor) and the back transistor (second transistor) in the flip-chip stacked transistor.

[0043] Since the memory cell of the memory includes a WL region and a BL region, after the first material layer and the second material layer are stacked sequentially on the substrate, the WL region and the BL region can be etched to form an active structure. First, based on step 2, the first material layer and the second material layer can be etched in the WL region to form a first semiconductor structure and a second semiconductor structure.

[0044] In some embodiments, the implementation process of step 2 may be: forming a first mask on the second material layer, the first mask being used to locate the WL region; etching the first material layer and the second material layer based on the first mask to form the first semiconductor structure and the second semiconductor structure. That is, after forming the mask by photolithography, etching is performed along the BL direction to form the first semiconductor structure and the second semiconductor structure.

[0045] It can be understood that a first mask can be formed on the second material layer first, and the first mask is used to locate the WL region. Therefore, the first mask covers a portion of the second material layer in the WL region and covers the entire second material layer in the BL region. In this way, the second material layer and the first material layer are etched based on the first mask to form a second semiconductor structure and a first semiconductor structure. The second semiconductor structure includes a first active structure in the WL region and a second material layer in the BL region. The first semiconductor structure includes a second active structure in the WL region and a first material layer in the BL region.

[0046] For example, the etching process may be at least one of dry etching, wet etching, reactive ion etching, etc.

[0047] After forming the first semiconductor structure and the second semiconductor structure, the second semiconductor structure can be etched in the BL region based on step 3 to form a first active structure. That is, etching is performed along the BL direction and the etching stops on the first material layer to form the first active structure.

[0048] In some embodiments, the implementation process of step three may be: forming a third mask on the first mask, the third mask being used for the BL region; etching the first mask and the second semiconductor structure based on the third mask to form a first active structure.

[0049] It can be understood that the BL region can be positioned by a third mask, and the third mask can be formed on the first mask. The third mask covers a portion of the first mask in the BL region and covers the entire first mask in the WL region. In this way, when etching downward based on the third mask, the second material layer in the BL region can be etched to form a first active structure. When etching downward based on the third mask, the first material layer can be used as an etch stop layer, that is, based on the third mask, the first mask and the second semiconductor structure are etched downward to form a first active structure, and the structure in the WL region is not affected.

[0050] In some embodiments, after etching the WL region to form the first semiconductor structure and the second semiconductor structure, an oxide material may be deposited on the substrate to form a first shallow trench isolation (STI) structure.

[0051] It is understandable that an oxide material may be deposited on the substrate and thinned so that the upper surface of the shallow trench isolation structure is flush with the upper surface of the first mask. The oxide material forming the shallow trench isolation structure may be exemplarily any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc. The thinning process may be exemplarily a process such as chemical-mechanical planarization (CMP).

[0052] Step S120: performing ion implantation in a region on the first semiconductor structure close to the first active structure to form a BL structure.

[0053] The BL structure is located between the first semiconductor structure and the first active structure. The first semiconductor structure, the BL structure and the first active structure are self-aligned along a first direction in the BL region. The doping concentration of the BL structure is different from that of the first semiconductor structure.

[0054] In some embodiments, the implementation process of step S120 may be: performing ion implantation on a region of the first semiconductor structure in the BL region close to the first active structure to form a third semiconductor structure in the BL region; and performing annealing treatment on the third semiconductor structure to form a BL structure.

[0055] It can be understood that the third mask formed above covers the entire first mask in the WL region, that is, the third mask covers the entire WL region, so ion implantation can be performed on the region near the first active structure on the first semiconductor structure in the BL region based on the third mask formed above to form a third semiconductor structure. The third semiconductor structure is then annealed, and due to the increase in temperature during annealing, ions diffuse and move to the active structure in the same horizontal direction as the third semiconductor, thereby forming a BL structure, wherein the BL structure is discontinuous in the WL region and continuous in the BL region.

[0056] In some embodiments, the doping concentration of the third semiconductor may be higher than the doping concentration of the first semiconductor structure, so that a BL structure with a higher doping concentration may be formed. As a channel for data transmission, the doping concentration of the BL structure mainly affects the efficiency and noise performance of data transmission. A higher doping concentration can improve the conductivity of the BL structure, reduce resistance, and thus speed up data transmission.

[0057] In some implementations, after the BL structure is formed, the third mask may be removed.

[0058] In some embodiments, after forming the BL active structure, an oxide material may be deposited on the BL structure to form a second shallow trench isolation structure.

[0059] It is understandable that after forming the first shallow trench isolation structure and the second shallow trench isolation structure, the first shallow trench isolation structure and the second shallow trench isolation structure can be thinned to a preset height to expose the gate region of the front transistor so as to subsequently prepare the gate structure of the front transistor.

[0060] Step S130: forming a first memory based on the first active structure.

[0061] In some embodiments, the implementation process of step S130 may include the following two steps: forming a first transistor based on the first active structure; and forming a first capacitor structure on the first transistor.

[0062] In some embodiments, based on the first active structure, the implementation process of forming the first transistor can be: based on the first active structure, forming a first gate structure; removing the first gate structure in the BL region to form a first groove; depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, and the upper surface of the first insulating layer is flush with the upper surface of the first mask; removing the first mask to form a second groove; forming a first source-drain structure in the second groove.

[0063] It can be understood that after thinning the first shallow trench isolation structure and the second shallow trench isolation structure to a preset height, the gate region of the front transistor is exposed, that is, a first gate groove is formed between the first active structure, so that an insulating material can be deposited at the first gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate electrode layer and the first gate dielectric layer surrounding the first gate electrode layer together constitute a first gate structure. The height of the first gate dielectric layer can be higher than the height of the first gate electrode layer.

[0064] For example, the first gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0065] By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0066] Since the WL structure in the WL region is connected to the gate structure of the transistor, the first gate structure in the WL region is necessary, while the first gate structure in the BL region may not exist, and thus the first gate structure in the BL region may be selectively removed.

[0067] In some embodiments, the first gate structure is removed in the BL region to form a first groove by: forming a sacrificial layer on the first gate electrode layer in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer; and anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer below the sacrificial layer to form a first groove.

[0068] It can be understood that a sacrificial layer attached to the bottom of the first gate electrode layer, the sidewall of the first gate dielectric layer, and the sidewall of the first mask can be deposited on the first gate electrode layer in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer, and then the bottom of the sacrificial layer and the first gate electrode layer below the sacrificial layer are anisotropically etched to obtain a first groove. Since the anisotropic etching is etched downward from the bottom of the sacrificial layer, and a portion of the first gate electrode layer still exists below the sidewall of the sacrificial layer, this portion of the first gate electrode layer is retained.

[0069] The insulating material may be, for example, oxide, nitride, etc. When depositing the sacrificial layer, a very thin film may be deposited on the surface of the substrate by atomic layer deposition (ALD).

[0070] In some embodiments, after the first recess is formed, the sacrificial layer may be removed.

[0071] It can be understood that after forming the first groove, an insulating material can be deposited on the first gate structure in the WL region and in the first groove to form a first insulating layer, and the upper surface of the first insulating layer is flush with the upper surface of the first mask. The first mask can then be removed to form a second groove, and a first source-drain structure of the front transistor is formed in the second groove. Among them, the first insulating layer is used to isolate the first source-drain structure of the front transistor. In the case where the transistor formed in the embodiment of the present application is a VCT, the source structure and drain structure of the VCT are approximately symmetrical. Therefore, for ease of explanation, the first source-drain structure mentioned in the embodiment of the present application is a short name, specifically referring to the first source structure and / or the first drain structure. In addition, the same is true for the second source-drain structure that appears later.

[0072] For example, ion implantation can be performed in the second groove to deposit metal material, and then annealing can be performed to form silicide, and the silicide can be used as the first source-drain structure. This is only an exemplary description, and can be determined as needed in actual operation. When the silicide is used as the first source structure, the BL structure can be used as the first drain structure. When the silicide is used as the first drain structure, the BL structure can be used as the first source structure.

[0073] In some embodiments, an insulating material may be deposited on the first gate structure in the WL region to form an isolation layer so that only the BL region is processed. In this way, after removing the sacrificial layer, the isolation layer above the WL region may be removed so that a first insulating layer is formed on both the WL region and the BL region.

[0074] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the first groove in the BL region to form a first oxide layer. Then, a first insulating layer is formed on the first oxide layer in the BL region and the first gate structure in the WL region. The first oxide layer may also be formed by ALD deposition, for example.

[0075] After the first source-drain structure is formed, a capacitor structure of a front-side memory may be formed on the front-side transistor.

[0076] In some embodiments, the implementation process of forming the first capacitor structure on the first transistor may be: forming a first dielectric layer on the first source-drain structure; etching a first portion of the first dielectric layer to expose the first source-drain structure; and forming the first capacitor structure on the first source-drain structure.

[0077] It can be understood that an insulating dielectric can be deposited on the first source-drain structure to form a first dielectric layer, and then a portion of the first dielectric layer is etched to expose the first source-drain structure below, and a layer of metal material is first deposited on the first source-drain structure, and then a dielectric material is deposited, and then another layer of metal material is deposited, so that a first capacitor structure including a first electrode and a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode can be formed, and thus the front memory can be prepared. Among them, the first dielectric layer located between the first capacitor structures can serve as an isolation structure between the first capacitor structures.

[0078] Step S140: flipping the first memory and removing the substrate to expose the first semiconductor structure.

[0079] In some embodiments, the implementation process of step S140 may be: flipping the first memory and removing the substrate; thinning the first shallow trench isolation structure to a preset height to expose the first semiconductor structure, and the thinned first shallow trench isolation structure is used to isolate the first transistor from the second transistor.

[0080] It can be understood that after the first capacitor structure is formed, the first capacitor structure can be bonded to the carrier wafer, and then the first capacitor structure can be flipped over and the substrate can be removed to expose the first semiconductor structure, thereby facilitating the subsequent preparation of the back side memory.

[0081] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first capacitor structure to form a third insulating layer, and the third insulating layer may be bonded to the carrier wafer, after which the first capacitor structure may be flipped over and the substrate may be removed.

[0082] After removing the substrate, the upper surface of the first semiconductor structure is flush with the upper surface of the first shallow trench isolation structure, so the first shallow trench isolation structure can be thinned to a preset height to expose the first semiconductor structure. The preset height can be set according to actual needs, and the embodiment of the present application does not limit this.

[0083] Step S150: etching the first semiconductor structure in the BL region to form a second active structure.

[0084] It can be understood that the first semiconductor structure formed above includes the second active structure in the WL region and the first material layer in the BL region. Therefore, after flipping the wafer, it is necessary to etch the back region and stop at the BL structure to form the second active structure, that is, to etch the first material layer along the WL direction to form the second active structure, and the second active structure includes the second active structure in the WL region and the second active structure in the BL region.

[0085] In some embodiments, after thinning the first shallow trench isolation structure, a second mask can be formed on the first material layer in the BL region and the second active structure in the WL region. The second mask is used to locate the second active structure in the BL region. Therefore, when etching downward based on the second mask, the first material layer in the BL region can be etched to form the second active structure in the BL region, while the structure in the WL region is not affected.

[0086] In some embodiments, after forming the second active structure, an oxide material may be deposited on the BL structure in the BL region to form a third shallow trench isolation structure.

[0087] It is understandable that after forming the first shallow trench isolation structure and the third shallow trench isolation structure, the first shallow trench isolation structure and the third shallow trench isolation structure can be thinned to a preset height to expose the gate region of the back transistor so as to subsequently prepare the gate structure of the back transistor.

[0088] Step S160: forming a second memory based on the second active structure.

[0089] In some embodiments, the implementation process of step S160 may include the following two steps: forming a second transistor based on the second active structure; and forming a second capacitor structure on the second transistor.

[0090] In some embodiments, based on the second active structure, the implementation process of forming the second transistor can be: based on the second active structure, forming a second gate structure; removing the second gate structure in the BL region to form a third groove; depositing an insulating material on the second gate structure in the WL region and in the second groove to form a second insulating layer, the upper surface of the second insulating layer is flush with the upper surface of the second mask, and the second mask is located on the second active structure; removing the second mask to form a fourth groove; forming a second source and drain structure in the fourth groove.

[0091] It can be understood that after thinning the first shallow trench isolation structure and the third shallow trench isolation structure to a preset height, the gate region of the back transistor is exposed, that is, a second gate groove is formed between the second active structure, so that an insulating material can be deposited at the second gate groove to form a second gate dielectric layer, and a metal material can be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute a second gate structure. The height of the second gate dielectric layer can be higher than the height of the second gate electrode layer.

[0092] In some embodiments, the second gate structure is removed in the BL region to form a third groove by: forming a sacrificial layer on the second gate electrode layer located in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer; and anisotropically etching the bottom of the sacrificial layer and the second gate electrode layer located below the sacrificial layer to form a third groove.

[0093] It can be understood that a sacrificial layer attached to the bottom of the second gate electrode layer, the sidewall of the second gate dielectric layer, and the sidewall of the second mask can be deposited on the second gate electrode layer in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer, and then the bottom of the sacrificial layer and the second gate electrode layer below the sacrificial layer are anisotropically etched to obtain a third groove. Since the anisotropic etching is etched downward from the bottom of the sacrificial layer, and a portion of the second gate electrode layer still exists below the sidewall of the sacrificial layer, this portion of the second gate electrode layer is retained.

[0094] In some embodiments, after the third recess is formed, the sacrificial layer may be removed.

[0095] After forming the third groove, an insulating material may be deposited on the second gate structure in the WL region and in the third groove to form a second insulating layer, the upper surface of the second insulating layer being flush with the upper surface of the second mask. The second mask may then be removed to form a fourth groove, and a second source-drain structure of the back transistor may be formed in the fourth groove.

[0096] In some embodiments, an insulating material may be deposited on the second gate structure in the WL region to form an isolation layer so that only the BL region is processed. In this way, after removing the sacrificial layer, the isolation layer above the WL region may be removed so that a second insulating layer is formed on both the WL region and the BL region.

[0097] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the third groove in the BL region to form a second oxide layer. Then, a second insulating layer is formed on the second oxide layer in the BL region and the second gate structure in the WL region. The second oxide layer may also be formed by ALD deposition, for example.

[0098] After the second source-drain structure is formed, a capacitor structure of a back side memory may be formed on the back side transistor.

[0099] In some embodiments, the implementation process of forming the second capacitor structure on the second transistor may be: forming a second dielectric layer on the second source-drain structure; etching a first portion of the second dielectric layer to expose the second source-drain structure; and forming a second capacitor structure on the second source-drain structure.

[0100] It can be understood that an insulating dielectric can be deposited on the second source-drain structure to form a second dielectric layer, and then a portion of the second dielectric layer is etched to expose the second source-drain structure below, and a layer of metal material is first deposited on the second source-drain structure, and then a dielectric material is deposited, and then another layer of metal material is deposited, so that a second capacitor structure including a first electrode and a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode can be formed, and thus the back side memory can be prepared. Among them, the second dielectric layer located between the second capacitor structures can serve as an isolation structure between the second capacitor structures.

[0101] In the present application, a first semiconductor structure and a second active structure are formed on a substrate, and then ion implantation is performed in a region on the first semiconductor near the second active structure to form a BL structure located between the first semiconductor structure and the first active structure. The first semiconductor structure, the BL structure and the first active structure are self-aligned in the BL region; then, based on the front active structure (first active structure), a first memory (front memory) is prepared; the front memory is flipped and the substrate is removed to expose the first semiconductor structure; then the first semiconductor structure is etched in the BL region to form a second active structure; finally, based on the second active structure, a second memory (back memory) is prepared. The present application ensures self-alignment of the front and back BLs by integrated molding of the BL region. Front and back integrated 4F is achieved through wafer bonding and flipping. 2 The equivalent area of ​​the memory is 2F. 2 , which is equivalent to reducing the area of ​​the memory unit of the memory and improving the storage density and integration of the memory. Moreover, the present application forms the BL structure by ion implantation, which is simple in steps and can save costs.

[0102] The following uses VCT as an example to illustrate the method for preparing the memory provided in the embodiment of the present application. Figure 2 This is a top view of the memory in the embodiment of the present application. It should be noted that for ease of understanding, only the BL structure, WL structure and capacitor structure are shown in the top view. The AA' direction is the cross-sectional direction of the memory along the BL structure; the BB' direction is the cross-sectional direction of the memory along the WL structure.

[0103] Figures 3 to 24 is a schematic diagram of the structure of the memory in the preparation process of the embodiment of the present application, Fig.25 Schematic diagram of the structure of the memory of the embodiment of the present application. Figures 3 to 25 (a) is a cross-sectional view of the memory along the cross-sectional direction of the BL structure (i.e., the AA' direction). Figures 3 to 25 (b) is a cross-sectional view of the memory along the cross-sectional direction of the WL structure (ie, the BB' direction).

[0104] In one example, the preparation process of the memory 10 may include the following steps:

[0105] Step 1: Form a first material layer 21 and a second material layer 22 on the original substrate 20 in sequence, and form a first mask 23 on the second material layer 22. The first mask 23 is used to define the active structure of the WL region, and obtain the following: Figure 3 The structure shown.

[0106] The first material layer and the second material layer are doped in the same manner and are used to form an active structure shared by the front transistor and the back transistor.

[0107] Step 2: Based on the first mask 23, the second material layer 22 and the first material layer 21 of the WL region are sequentially etched until the substrate 20 to form a self-aligned semiconductor structure 24, wherein the semiconductor structure 24 includes a first semiconductor structure 241 and a second semiconductor structure 242, and the following is obtained: Figure 4 The structure shown.

[0108] Step 3: Deposit an oxide material on the substrate 20 in the WL region to form a first shallow trench isolation structure 25, and perform CMP to the upper surface of the first mask 23 to obtain Figure 5 The structure shown.

[0109] Step 4: Form a third mask 26 by photolithography and etching to prepare for WL etching. The third mask 26 is used to define the active structure of the WL region to obtain Figure 6 The structure shown.

[0110] Step 5: Etching according to the WL photolithography pattern, that is, etching based on the third mask 26 to form the first active structure 111, and obtaining the following Figure 7 The structure shown.

[0111] Step 6: Perform ion implantation on the first semiconductor structure 251 based on the third mask 26 to form a third semiconductor structure 27 in the BL region, and obtain Figure 8 The structure shown.

[0112] The doping concentration of the third semiconductor structure 27 is higher than the doping concentration of the first semiconductor structure 251 .

[0113] Step 7: Annealing to promote ion diffusion and form a complete connected BL structure 28, as shown in the following figure: Fig. 9 The structure shown.

[0114] like Fig. 9 As shown in (a) in FIG. 3 , the BL structure is a continuous structure in the BL region. Fig. 9 As shown in (b), the BL structure is a discontinuous structure in the WL region. This step can ensure self-alignment in the BL direction.

[0115] Step 8: Etch the third mask 26, and deposit a second shallow trench isolation structure 29 on the BL structure in the BL region, and CMP the first shallow trench isolation structure and the second shallow trench isolation structure to a certain height, to obtain Fig.10 The structure shown.

[0116] Step 9: selectively deposit an insulating material on the surface of the first active structure 111 to form a first gate dielectric layer 1131, thereby obtaining Fig.11 The structure shown.

[0117] Step 10: Deposit metal material on the first gate dielectric layer 1131 and perform CMP to a certain height to form a first gate electrode layer 1132. Fig.12 The structure shown.

[0118] The first gate dielectric layer 1131 and the first gate electrode layer 1132 constitute a first gate structure 113 , and the height of the first gate dielectric layer 1131 is higher than the height of the first gate electrode layer 1132 .

[0119] Step 11: Form an isolation layer 30 by photolithography and etching to cover the WL region so that only the BL region can be processed later. Fig.13 The structure shown.

[0120] Step 12: Deposit a sacrificial layer 31 on the first gate electrode layer 1132 to adhere to the bottom of the first gate electrode layer 1132, the sidewall of the first gate dielectric layer 1131, and the sidewall of the first mask 23, to obtain Fig.14 The structure shown.

[0121] Step 13: Anisotropically etch the bottom of the sacrificial layer 31 and the first gate electrode layer 1132 located below the sacrificial layer 31, then remove the sacrificial layer 31 to form a first groove 32, and obtain the following: Fig.15 The structure shown.

[0122] It can be understood that the anisotropic etching is performed from the bottom of the sacrificial layer downwards, and a portion of the first gate electrode layer still exists below the sidewall of the sacrificial layer, so this portion of the first gate electrode layer is retained, see Fig.15 (a).

[0123] For example, when depositing the sacrificial layer, a very thin sacrificial layer may be deposited on the surface of the substrate by ALD deposition.

[0124] Step 14: Deposit an oxide material in the first groove 32 to form a first oxide layer 33, and obtain Fig.16 The structure shown.

[0125] Step 15: Remove the isolation layer 30 above the WL region, and deposit an insulating material (such as SiN) in the two regions to form a first insulating layer 34, so as to obtain Fig.17 The structure shown.

[0126] Step 16: Selectively etch the first mask 23 to form a second groove 35, and obtain Fig.18 The structure shown.

[0127] Step 17: forming a first source-drain structure 112 in the second groove 35, and depositing an insulating dielectric on the first source-drain structure 112 to form a first dielectric layer 36, so as to obtain Fig.19 The structure shown.

[0128] For example, ion implantation may be performed in the second groove 35 to deposit a metal material, which is then annealed to form silicide, and the silicide is used as the first source-drain structure.

[0129] Step 18: Etch a portion of the first dielectric layer 36 to expose the first source-drain structure 112, and form a first capacitor structure 37 on the first source-drain structure 112 to obtain Fig. 20 The structure shown.

[0130] The first capacitor structure may include deposition of a metal upper plate, deposition of a dielectric layer, and deposition of a metal lower plate. Fig. 20 This is a simplified representation only.

[0131] Here, the first drain structure of the first transistor is connected to the BL structure 28 , and the first source structure of the first transistor is connected to the first capacitor structure 37 .

[0132] Step 19: Deposit insulating material on the first capacitor structure 37 to form a third insulating layer 13, and bond the third insulating layer 13 to the carrier wafer 14, and then flip the wafer to obtain the following: Fig.21 The structure shown.

[0133] Step 20: Remove the substrate 20 to the first shallow trench isolation structure 25 to obtain Fig. 22 The structure shown.

[0134] Step 21: Form a second mask 38, and perform etching based on the second mask 38 to form a second active structure 121, and obtain Fig.23 The structure shown.

[0135] Step 22: Deposit an oxide material on the BL structure in the BL region and perform CMP to a certain height to form a third shallow trench isolation structure 39, as shown in FIG. Fig.24 The structure shown.

[0136] Step 23: Prepare a second transistor and a second capacitor structure 43 to obtain Fig.25 The structure shown.

[0137] It can be understood that first, an insulating material is selectively deposited on the surface of the second active structure 121 to form a second gate dielectric layer 1231, and a metal material is deposited on the second gate dielectric layer 1231 and CMPed to a certain height to form a second gate electrode layer 1232, so as to form the second gate structure 123. Then, an isolation layer is formed by photolithography and etching to cover the WL region, so as to facilitate the processing of the BL region. Afterwards, a sacrificial layer attached to the bottom of the second gate electrode layer 1242, the sidewalls of the second gate dielectric layer 1231, and the sidewalls of the second mask 38 may be deposited on the second gate electrode layer 1232, the bottom of the sacrificial layer and the second gate electrode layer 1232 located below the sacrificial layer may be anisotropically etched, and then the sacrificial layer may be removed to form a groove, and an oxide material may be deposited in the groove to form a second oxide layer 40, the isolation layer above the WL region may be removed, an insulating material (such as SiN) may be deposited in the two regions to form a second insulating layer 41, the second mask 38 may be selectively etched to form a groove, a second drain structure 122 may be formed in the groove, an insulating dielectric may be deposited on the second source-drain structure 122 to form a second dielectric layer 42, a portion of the second dielectric layer 42 may be etched to expose the second source-drain structure 122, and a second capacitor structure 43 may be formed on the second source-drain structure 122. Here, the second drain structure of the second transistor is connected to the BL structure 28, and the second source structure of the second transistor is connected to the second capacitor structure 43.

[0138] You can refer to steps 9 to 18 here.

[0139] This application ensures self-alignment of the front and back BLs through integrated molding of the BL area. Through wafer bonding and flipping, front and back integrated 4F is achieved 2 The equivalent area of ​​the memory is 2F. 2 , which is equivalent to reducing the area of ​​the memory cell of the memory and improving the storage density and integration of the memory. Moreover, the present application forms the BL structure by ion implantation, which has simple steps and can save costs.

[0140] Furthermore, this application starts from the specific process flow of self-aligned flip-chip stacked transistors and 2 The DRAM production process is combined with the BL integrated molding to ensure the self-alignment of the BL area. The front and back DRAM production is achieved through wafer bonding flipping, and its volume is equivalent to 2F. 2 , achieving further miniaturization of integrated circuit size.

[0141] Furthermore, the memory provided in the embodiment of the present application can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the structure of the above-mentioned memory, and it can be observed that the 1T1C structure in the basic structure of the memory exists on both the front and back sides. Moreover, by cutting the cross section of the substrate, it can be seen that it is initially a complete silicon substrate, and the BL structure is subsequently formed by ion implantation.

[0142] The present application embodiment provides a semiconductor device, including: a memory as described in the above embodiment. The specific definition of the memory can refer to the above memory, which will not be described in detail here.

[0143] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device is arranged on the circuit board. The semiconductor device includes the above memory. The specific definition of the memory can refer to the above memory, which is not repeated here.

[0144] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0145] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a memory, characterized in that: The method comprises: Forming a stacked structure on a substrate, the stacked structure comprising: a first semiconductor structure and a first active structure stacked in sequence in a first direction, wherein the doping concentration of the first semiconductor structure is the same as the doping concentration of the first active structure; Performing ion implantation in a region near the first active structure on the first semiconductor structure to form a bit line BL structure, wherein the BL structure is located between the first semiconductor structure and the first active structure, and the first semiconductor structure, the BL structure and the first active structure are self-aligned along the first direction in the BL region; Based on the first active structure, forming a first memory; Flipping the first memory and removing the substrate to expose the first semiconductor structure; Etching the first semiconductor structure in the BL region to form a second active structure; A second memory is formed based on the second active structure, wherein the first source-drain structure in the first memory and the second source-drain structure in the second memory share the BL structure.

2. The method according to claim 1, characterized in that: The forming of a first stacking structure on a substrate comprises: stacking a first material layer and a second material layer in sequence along the first direction on the substrate; Etching the first material layer and the second material layer in the word line WL region to form the first semiconductor structure and the second semiconductor structure; The second semiconductor structure is etched in the BL region to form the first active structure.

3. The method according to claim 1, characterized in that The step of performing ion implantation in a region on the first semiconductor structure close to the first active structure to form a bit line BL structure comprises: Performing ion implantation on a region of the first semiconductor structure in the BL region close to the first active structure to form a third semiconductor structure in the BL region; The third semiconductor is annealed to form the BL structure.

4. The method according to claim 1, characterized in that: The forming of a first memory based on the first active structure includes: Based on the first active structure, forming a first transistor; forming a first capacitor structure on the first transistor; The forming of a second memory based on the second active structure comprises: Based on the second active structure, forming a second transistor; A second capacitor structure is formed on the second transistor.

5. The method according to claim 4, characterized in that The forming of a first transistor based on the first active structure comprises: Based on the first active structure, forming a first gate structure; Removing the first gate structure in the BL region to form a first groove; Depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein an upper surface of the first insulating layer is flush with an upper surface of a first mask, and the first mask is located on the first active structure; removing the first mask to form a second groove; A first source-drain structure is formed in the second groove.

6. The method according to claim 5, characterized in that The first gate structure includes a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, wherein the height of the first gate electrode layer is lower than the height of the first gate dielectric layer; The removing the first gate structure in the BL region to form a first groove comprises: forming a sacrificial layer on the first gate electrode layer in the BL region, wherein an upper surface of the sacrificial layer is flush with an upper surface of the first gate dielectric layer; The bottom of the sacrificial layer and the first gate electrode layer located below the sacrificial layer are anisotropically etched to form the first groove.

7. The method according to claim 5 or 6, characterized in that: The forming of a first capacitor structure on the first transistor comprises: forming a first dielectric layer on the first source-drain structure; Etching a first portion of the first dielectric layer to expose the first source-drain structure; The first capacitor structure is formed on the first source-drain structure.

8. The method according to claim 4, characterized in that The forming of a second transistor based on the second active structure comprises: Based on the second active structure, forming a second gate structure; Removing the second gate structure in the BL region to form a third groove; Depositing an insulating material on the second gate structure in the WL region and in the third groove to form a second insulating layer, wherein an upper surface of the second insulating layer is flush with an upper surface of a second mask, and the second mask is located on the second active structure; removing the second mask to form a fourth groove; A second source-drain structure is formed in the fourth groove.

9. A memory, prepared using the preparation method according to any one of claims 1 to 8, characterized in that: include: BL structure; a first memory; A second memory, wherein the second memory is arranged opposite to the first memory, and a first source-drain structure in the second memory and a second source-drain structure in the first memory share the BL structure.

10. A semiconductor device, characterized in that: include: The memory as claimed in claim 9.

11. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 10, wherein the semiconductor device is arranged on the circuit board.

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