Static random access memory mismatch test structure and test method

Abstract

The invention provides a static random access memory mismatch test structure and a test method, the static random access memory mismatch test structure comprises a plurality of rows of ring oscillators with different stages, a decoder and a multiplexer, and the stages of each row of ring oscillators are sequentially increased. The ring oscillator in each row comprises a plurality of first phase inverters connected in series and a plurality of second phase inverters connected in series, the input ends of the plurality of first phase inverters are connected in series with the output ends of the plurality of second phase inverters, each first phase inverter is composed of a first PMOS tube and a first NMOS tube in the storage unit, and each second phase inverter is composed of a second PMOS tube and a second NMOS tube in the storage unit. The first phase inverter is composed of a first PMOS transistor and a first NMOS transistor in the memory cell, the second phase inverter is composed of a second PMOS transistor and a second NMOS transistor in the memory cell, so that the layout area of the static random access memory mismatch test structure is smaller than that of an existing mismatch device test structure, and the area occupied by the static random access memory mismatch test structure is saved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a static random access memory mismatch test structure and a test method. Background Art

[0002] With the continuous development of integrated circuit technology, the number of semiconductor devices integrated in a single chip continues to increase. When designing integrated circuits, it is usually necessary to use several semiconductor devices with the same electrical parameters. For example, when designing a storage unit of a static random access memory (SRAM), several MOS transistors with the same electrical parameters are required. Since static random access memory has varying degrees of process fluctuations during the manufacturing process, for example, it is easy to cause fluctuations in feature size in the lithography and etching processes, and it is easy to cause fluctuations in doping concentration in the ion implantation process. With the random fluctuations in the process, the characteristics of devices of the same design on a chip (for example, the threshold voltage, leakage current, capacitance, resistance, etc. of the device) will show some deviations, thus causing device mismatch. Device mismatch includes local mismatch (SRAM local mismatch) and global mismatch. As Figure 1 As shown, currently, the method for measuring mismatch is to use a large number of device arrays to perform DC testing on a single transistor 10, extract process fluctuations through test data, and verify the mismatch value, but this occupies a large area. Summary of the invention

[0003] The object of the present invention is to provide a static random access memory mismatch test structure and a test method to reduce the area occupied by the static random access memory mismatch test structure.

[0004] To achieve the above object, the present invention provides a static random access memory mismatch test structure, comprising: a plurality of rows of ring oscillators of different levels, the levels of the ring oscillators in each row are increased sequentially, each row of the ring oscillators comprises a plurality of first inverters connected in series and a plurality of second inverters connected in series, the input ends of the plurality of first inverters are connected in series with the output ends of the plurality of second inverters, wherein the first inverter is composed of a first PMOS tube and a first NMOS tube in a storage unit, and the second inverter is composed of a second PMOS tube and a second NMOS tube in the storage unit;

[0005] A decoder, the decoder being electrically connected to all the ring oscillators and configured to output a row selection signal to select a predetermined number of ring oscillators;

[0006] A multiplexer is used to output the output signals of the ring oscillators of the predetermined number of stages.

[0007] Optionally, in the static random access memory mismatch test structure, the ring oscillator also includes a NAND gate, a first input end of the NAND gate is used to receive an enable signal, and a second input end of the NAND gate is connected to the output ends of a plurality of the second inverters connected in series to form a loop.

[0008] Optionally, in the static random access memory mismatch test structure, the multiplexer includes multiple input terminals, and the input terminals of the multiplexer correspond one-to-one to the output terminals of the multiple rows of the ring oscillators, wherein each input terminal of the multiplexer has a third inverter, a first NOR gate and a fourth inverter, the input terminal of the fourth inverter is connected to the output terminal of the decoder, the output terminal of the fourth inverter is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is connected to the output terminal of the third inverter in the multiplexer corresponding to the ring oscillator in an adjacent row, and the output terminal of the first NOR gate is connected to the input terminal of the third inverter.

[0009] Optionally, in the static random access memory mismatch test structure, the input end of the multiplexer also has a second NOR gate and a fifth inverter, the output end of the fifth inverter is connected to the first input end of the second NOR gate, the second input end of the second NOR gate is connected to the output end of the third inverter corresponding to the ring oscillator of the first row, and the output end of the second NOR gate outputs the output signal of the ring oscillator of the predetermined level.

[0010] Optionally, in the static random access memory mismatch test structure, the output signal is an AC signal.

[0011] Optionally, in the static random access memory mismatch test structure, the number of stages of the ring oscillator is 5 to 29, and the number of stages of the ring oscillator is an odd number.

[0012] Optionally, in the static random access memory mismatch test structure, the gate of the first PMOS tube is electrically connected to the gate of the first NMOS tube, and the drain of the first PMOS tube is electrically connected to the drain of the first NMOS tube.

[0013] Optionally, in the static random access memory mismatch test structure, the drain of the second PMOS tube is electrically connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is electrically connected to the gate of the second NMOS tube.

[0014] Optionally, in the static random access memory mismatch test structure, the storage unit also includes a third NMOS tube and a fourth NMOS tube, the drain of the third NMOS tube is electrically connected to the drain of the first PMOS tube and the drain of the first NMOS tube; the drain of the fourth NMOS tube is electrically connected to the drain of the second PMOS tube and the drain of the second NMOS tube.

[0015] Based on the same inventive concept, the present invention also provides a static random access memory mismatch test method, comprising:

[0016] The static random access memory mismatch test structure as described above;

[0017] The output signal of the ring oscillator of the predetermined number is obtained, and the frequency of the ring oscillator of the predetermined number is obtained according to the output signal, so as to obtain the mismatch value of the ring oscillator of different numbers.

[0018] In the static random access memory mismatch test structure provided by the present invention, multiple rows of ring oscillators, decoders and multiplexers of different levels are included, the levels of the ring oscillators in each row are increased sequentially, and the ring oscillators in each row include multiple first inverters connected in series and multiple second inverters connected in series, the input ends of the multiple first inverters are connected in series with the output ends of the multiple second inverters, wherein the first inverter is composed of a first PMOS tube and a first NMOS tube in a storage unit, and the second inverter is composed of a second PMOS tube and a second NMOS tube in the storage unit. The invention relates to a static random access memory mismatch test structure, wherein the layout area of ​​the static random access memory mismatch test structure is smaller than that of the existing mismatch device test structure, thereby saving the area occupied by the test structure; the decoder is electrically connected to all the ring oscillators and is used to output a row selection signal to select a ring oscillator of a predetermined number of stages; the multiplexer is used to output the output signal of the ring oscillator of the predetermined number of stages, thereby obtaining the output signal of the ring oscillator of the predetermined number of stages and obtaining the frequency of the ring oscillator of the predetermined number of stages according to the output signal to obtain the mismatch values ​​of the ring oscillators of different stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the circuit principle of the existing mismatch test structure;

[0020] Figure 2 A schematic diagram of a circuit principle of a static random access memory mismatch test structure according to an embodiment of the present invention;

[0021] Figure 3 It is a structural schematic diagram of a storage unit of a static random access memory mismatch structure according to an embodiment of the present invention;

[0022] Figure 4 It is a circuit diagram of a plurality of first inverters and a plurality of second inverters of a static random access memory mismatch structure according to an embodiment of the present invention;

[0023] Figure 5 is a circuit diagram of a static random access memory mismatch structure according to an embodiment of the present invention;

[0024] The reference numerals are described as follows:

[0025] 100-ring oscillator; 101-first inverter; 102-second inverter; 103-NAND gate;

[0026] 200-decoder;

[0027] 300 - multiplexer; 310 - third inverter; 311 - first NOR gate; 312 - fourth inverter; 313 - second NOR gate; 314 - fifth inverter; 315 - sixth inverter. DETAILED DESCRIPTION

[0028] The static random access memory mismatch test structure and test method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0029] Figure 2 FIG. 1 is a schematic diagram of the circuit principle of the static random access memory mismatch test structure according to an embodiment of the present invention. Figure 2 As shown, the static random access memory mismatch test structure provided in this embodiment includes multiple rows of ring oscillators 100 of different levels, a decoder 200 and a multiplexer 300 .

[0030] like Figure 2 As shown, the number of the ring oscillators (RO) 100 in each row increases successively, and the number of the ring oscillators 100 is 5 to 29, and the number of the ring oscillators 100 is an odd number. For example, the number of the ring oscillators 100 in the first row is 5, the number of the ring oscillators 100 in the second row is 7, the number of the ring oscillators 100 in the third row is 9, the number of the ring oscillators 100 in the fourth row is 11, and so on. That is, the number of the ring oscillators 100 increases successively from the first row to the nth row, and the number of the ring oscillators 100 in each row increases successively to 2.

[0031] In this embodiment, Figure 5As shown, each row of the ring oscillator 100 includes a plurality of first inverters 101 connected in series and a plurality of second inverters 102 connected in series, wherein the input ends of the plurality of first inverters 101 are connected in series with the output ends of the plurality of second inverters 102, wherein Figure 2 As shown, the first inverter 101 is composed of the first PMOS tube PL and the first NMOS tube NL in the storage unit, and the second inverter 102 is composed of the second PMOS tube PR and the second NMOS tube NR in the storage unit. The first storage unit is a 6T storage unit, that is, the storage unit includes 6 transistors. Since the first inverter 101 is composed of the first PMOS tube PL and the first NMOS tube NL in the storage unit, and the density of the transistors in the storage unit is relatively high, the layout area of ​​the static random access memory mismatch test structure is smaller than that of the existing mismatch device test structure, thereby saving the area occupied by the mismatch test structure.

[0032] like Figure 3 As shown, the first inverter 101 and the second inverter 102 are connected in series through metal wires to form a closed loop, thereby forming a basic ring oscillator (RO) 100. Since the frequency of the ring oscillator 100 is mainly determined by the delay time of the inverter in its loop, when the number of inverters (i.e., the number of RO stages) increases, due to process deviations and parasitic effects, the frequency of the ring oscillator 100 will tend to be stable, thereby reflecting the changing trend of the device mismatch value.

[0033] like Figure 3 As shown, in this embodiment, the gate of the first PMOS tube PL is electrically connected to the gate of the first NMOS tube NL, and the drain of the first PMOS tube PL is electrically connected to the drain of the first NMOS tube NL. The drain of the second PMOS tube PR is electrically connected to the drain of the second NMOS tube NR, and the gate of the second PMOS tube PR is electrically connected to the gate of the second NMOS tube NR.

[0034] In further schemes, such as Figure 3 As shown, the storage unit further includes a third NMOS tube NPL and a fourth NMOS tube NPR, the source of the third NMOS tube NPL is electrically connected to the drain of the first PMOS tube PL and the drain of the first NMOS tube NL; the source of the fourth NMOS tube NPR is electrically connected to the drain of the second PMOS tube PR and the drain of the second NMOS tube NR. The third NMOS tube NPL and the fourth NMOS tube NPR are used as switches to control the reading and writing of the storage unit.

[0035] like Figure 5As shown, the ring oscillator 100 further includes a NAND gate 103, wherein a first input terminal of the NAND gate 103 is used to receive an enable signal, wherein the enable signal is used to enable the ring oscillator 100 to start oscillation and generate an AC signal. A second input terminal of the NAND gate 103 is connected to the output terminals of a plurality of the second inverters 102 connected in series to form a loop.

[0036] like Figure 2 As shown, the decoder 200 is electrically connected to all the ring oscillators 100 and is used to output a row selection signal to select a predetermined number of ring oscillators 100; the decoder 200 can receive an external address signal and convert it into a corresponding row selection signal, thereby controlling the enabling or disabling of each row of ring oscillators 100 through the row selection signal, and then testing the mismatch value of the ring oscillators 100 of a specified number of levels (or a specified row), thereby achieving addressing testing of the number of levels of different ring oscillators 100.

[0037] In this embodiment, the multiplexer 300 is used to output the output signal of the ring oscillator 100 of the predetermined number of stages, wherein the output signal is an AC signal. Figure 5 As shown, the multiplexer 300 includes a plurality of input terminals, and the input terminals of the multiplexer correspond to the plurality of rows of the ring oscillators 100 one by one. Each input terminal of the multiplexer 300 has a third inverter 310, a first NOR gate 311, and a fourth inverter 312, the input terminal of the fourth inverter 312 is connected to the output terminal of the decoder 200, the output terminal of the fourth inverter 312 is connected to the first input terminal of the first NOR gate 311, the second input terminal of the first NOR gate 311 is connected to the output terminal of the third inverter 310 in the multiplexer corresponding to the ring oscillator 100 in the adjacent row, and the output terminal of the first NOR gate 311 is connected to the input terminal of the third inverter 310. Furthermore, the input end of the multiplexer 300 corresponding to the ring oscillator with the largest number of stages (i.e., the ring oscillator in the last row) can be provided with a sixth inverter 315 without providing a first NOR gate, and the sixth inverter 315 is located between the third inverter 310 and the fourth inverter 312.

[0038] like Figure 5As shown, the input end of the multiplexer 300 also has a second NOR gate 313 and a fifth inverter 314, the input end of the fifth inverter 314 is connected to the output end of the ring oscillator 100 of the predetermined number, the output end of the fifth inverter 314 is connected to the first input end of the second NOR gate 313, the second input end of the second NOR gate 313 is connected to the output end of the third inverter 310 of the input end of the multiplexer corresponding to the ring oscillator 100 of the first row, and the output end (output) of the second NOR gate 313 outputs the output signal of the ring oscillator 100 of the predetermined number. In this way, by acquiring the output signal of the ring oscillator of the predetermined number, and obtaining the frequency of the ring oscillator of the predetermined number according to the output signal, the mismatch value of the ring oscillator of different numbers is obtained, and then the relationship between the mismatch value of the ring oscillator and the number of different ring oscillators can be obtained.

[0039] This embodiment also provides a static random access memory mismatch test method, including:

[0040] like Figure 2 As shown, a static random access memory mismatch test structure is provided. The static random access memory mismatch test structure is the static random access memory mismatch test structure provided in this embodiment, which will not be described in detail here.

[0041] Then, the output signal of the ring oscillator 100 of the predetermined number of stages is obtained, and the frequency of the ring oscillator 100 of the predetermined number of stages is obtained according to the output signal, so as to obtain the mismatch value of the ring oscillator 100 of different stages. By measuring the frequency of each row of ring oscillators 100, recording and analyzing the frequency data of ring oscillators 100 of different stages, it is possible to find out that the frequency tends to be stable as the number of stages increases, thereby reflecting the change of the mismatch value of the device. For example, when the RO stage is less than 9, the global mismatch and local mismatch are protected. When the RO stage is greater than 25, only the global mismatch is reflected because the local mismatch is complementary.

[0042] In summary, in the static random access memory mismatch test structure and test method provided by the embodiment of the present invention, the static random access memory mismatch test structure includes multiple rows of ring oscillators, decoders and multiplexers of different levels, the levels of the ring oscillators in each row increase sequentially, and the ring oscillators in each row include multiple first inverters connected in series and multiple second inverters connected in series, the input ends of the multiple first inverters are connected in series with the output ends of the multiple second inverters, wherein the first inverter is composed of a first PMOS tube and a first NMOS tube in the storage unit, and the second inverter is composed of a first NMOS tube in the storage unit. The present invention is characterized in that the present invention is composed of two PMOS tubes and a second NMOS tube. Thus, compared with the existing mismatch device test structure, the layout area of ​​the static random access memory mismatch test structure is smaller, thereby saving the area occupied by the test structure; the decoder is electrically connected to all the ring oscillators and is used to output a row selection signal to select a ring oscillator of a predetermined number of stages; the multiplexer is used to output the output signal of the ring oscillator of the predetermined number of stages, thus, by acquiring the output signal of the ring oscillator of the predetermined number of stages and obtaining the frequency of the ring oscillator of the predetermined number of stages according to the output signal, the mismatch values ​​of the ring oscillators of different stages are obtained.

[0043] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A static random access memory mismatch test structure, characterized in that: include: A plurality of rows of ring oscillators of different levels, wherein the levels of the ring oscillators in each row increase sequentially, and each row of the ring oscillators comprises a plurality of first inverters connected in series and a plurality of second inverters connected in series, wherein the input ends of the plurality of first inverters are connected in series with the output ends of the plurality of second inverters, wherein the first inverter is composed of a first PMOS tube and a first NMOS tube in a storage unit, and the second inverter is composed of a second PMOS tube and a second NMOS tube in the storage unit; A decoder, the decoder being electrically connected to all the ring oscillators and configured to output a row selection signal to select a predetermined number of ring oscillators; A multiplexer is used to output the output signals of the ring oscillators of the predetermined number of stages.

2. The static random access memory mismatch test structure according to claim 1, characterized in that: The ring oscillator further comprises a NAND gate, a first input terminal of the NAND gate is used to receive an enable signal, and a second input terminal of the NAND gate is connected to output terminals of a plurality of the second inverters connected in series to form a loop.

3. The static random access memory mismatch test structure as claimed in claim 2, characterized in that: The multiplexer includes a plurality of input terminals, and the input terminals of the multiplexer correspond one-to-one to the output terminals of the multiple rows of the ring oscillators, wherein each input terminal of the multiplexer has a third inverter, a first NOR gate and a fourth inverter, the input terminal of the fourth inverter is connected to the output terminal of the decoder, the output terminal of the fourth inverter is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is connected to the output terminal of the third inverter corresponding to the ring oscillator in an adjacent row, and the output terminal of the first NOR gate is connected to the input terminal of the third inverter.

4. The static random access memory mismatch test structure according to claim 3, characterized in that: The input end of the multiplexer also has a second NOR gate and a fifth inverter, the output end of the fifth inverter is connected to the first input end of the second NOR gate, the second input end of the second NOR gate is connected to the output end of the third inverter corresponding to the ring oscillator of the first row, and the output end of the second NOR gate outputs the output signal of the ring oscillator of the predetermined number of levels.

5. The static random access memory mismatch test structure according to claim 1, wherein: The output signal is an AC signal.

6. The static random access memory mismatch test structure according to claim 1, characterized in that: The number of stages of the ring oscillator is 5-29, and the number of stages of the ring oscillator is an odd number.

7. The static random access memory mismatch test structure according to claim 1, characterized in that: The gate of the first PMOS tube is electrically connected to the gate of the first NMOS tube, and the drain of the first PMOS tube is electrically connected to the drain of the first NMOS tube.

8. The static random access memory mismatch test structure according to claim 1, characterized in that: The drain of the second PMOS tube is electrically connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is electrically connected to the gate of the second NMOS tube.

9. The static random access memory mismatch test structure according to claim 1, characterized in that: The storage unit also includes a third NMOS tube and a fourth NMOS tube, the source of the third NMOS tube is electrically connected to the drain of the first PMOS tube and the drain of the first NMOS tube; the source of the fourth NMOS tube is electrically connected to the drain of the second PMOS tube and the drain of the second NMOS tube.

10. A static random access memory mismatch test method, characterized in that: include: The static random access memory mismatch test structure according to any one of claims 1 to 9; The output signal of the ring oscillator of the predetermined number is obtained, and the frequency of the ring oscillator of the predetermined number is obtained according to the output signal, so as to obtain the mismatch value of the ring oscillator of different numbers.

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