Controllable scaling convolution processing device and method based on random calculation

Abstract

The present invention relates to a controllable scaling convolution processing device and method based on random calculation. By sharing the pseudo-random number sequence generated by the random number source in the random number generation module, one round of convolution calculation uses only one linear feedback shift register, which greatly reduces the hardware cost and calculation overhead. At the same time, the random number generation module performs operations such as shifting and swapping the pseudo-random number sequence through shuffling operations, which effectively weakens the correlation between data, thereby greatly reducing the precision error caused by the correlation in the random calculation. In the convolution calculation module, a JK trigger is used to replace a binary divider to generate a control signal of a multiplexer in the convolution calculation, without relying on a large number of AND gates or XOR gates, which greatly simplifies the complexity of the convolution calculation architecture and further reduces the hardware cost, area occupancy and power consumption; finally, the data processing module completes the conversion and recovery of binary numbers.

Description

Technical Field

[0001] The present invention relates to the field of random computing technology of a new computing architecture, and in particular to a controllable scalable convolution processing device and method based on random computing. Background Art

[0002] Deep learning technology, especially convolutional neural networks (CNN), has been widely used in fields such as face recognition and voice search. However, with the increase in model complexity and data size, the computing resources and hardware consumption required by CNN have increased significantly. Among them, convolution calculations based on matrix multiplication have become the main source of resource consumption, limiting its application in resource-constrained environments such as smart watches and surveillance cameras.

[0003] Stochastic computing (SC) is an efficient computing paradigm with the characteristics of probabilistic representation and approximate computing. Stochastic computing uses the bit operations of random bit streams (SN) to approximate complex calculations such as multiplication. Its hardware cost is much lower than that of binary multipliers. It can effectively reduce the dependence on computing resources and show good fault tolerance. Due to the approximate nature of CNN, small errors in calculations have no obvious effect on its accuracy. Introducing stochastic computing into CNN can significantly improve computing efficiency and reduce costs, which is particularly important for resource-constrained application environments.

[0004] The current application of CNN in the field of stochastic computing focuses on the multiplication and accumulation operations of convolutional structures. Multiplication is usually implemented using AND gates and XNOR gates, and 0.5 times scaling addition is implemented using multiplexers (MUX). However, the correlation of random bit streams in stochastic computing will have a great impact on the calculation accuracy, and generating low-correlation random bit streams often requires a higher hardware cost than the calculation itself. In addition, a large number of accumulation operations in convolution operations will cause huge scaling errors in multiplexer additions, further leading to serious precision loss. Some current studies consider using approximate parallel counters (APCs) to implement accumulation operations, but the approximate parallel counters contain a large number of complex circuit structures such as full adders and half adders, and because the output of the approximate parallel counter is in binary (BN) format, additional binary number and random bit stream conversion is required, which makes it not advantageous in terms of hardware cost, area and power consumption. Therefore, more effective hardware design of CNN in the field of stochastic computing still faces huge challenges. Researching how to improve the accuracy of convolution calculations in practical applications and reduce computing power consumption to improve computing performance is still an important technical issue currently faced. Summary of the invention

[0005] Based on this, it is necessary to provide a controllable scalable convolution processing device based on random calculation and a controllable scalable convolution processing method based on random calculation, which can effectively improve the accuracy of convolution calculation and reduce calculation power consumption.

[0006] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On the one hand, a controllable scaling convolution processing device based on random calculation is provided, comprising:

[0008] A random number generation module is used to share a pseudo-random number sequence generated by a random number source through a shuffling operation, and convert the data to be converted in the form of binary numbers into a random bit stream represented by probability; the data to be converted includes input data and weight coefficients corresponding to the input data;

[0009] The convolution calculation module is used to generate a control signal of a multiplexer in the convolution calculation according to the random bit stream corresponding to the weight coefficient, execute the convolution operation of the convolution kernel in the CNN on the random bit stream corresponding to the input data, and obtain the random bit stream after the convolution calculation is completed; the control signal is generated by using a JK flip-flop to replace the binary divider;

[0010] The data processing module is used to convert the random bit stream after the convolution calculation into a binary number and perform recovery processing on the scaled data to obtain the convolution processing result corresponding to the input data.

[0011] On the other hand, a controllable scaling convolution processing method based on random calculation is also provided. Based on the above-mentioned controllable scaling convolution processing device based on random calculation, the controllable scaling convolution processing method based on random calculation includes the steps of:

[0012] Converting the data to be converted in binary form into a random bit stream represented by probability; the data to be converted includes input data and weight coefficients corresponding to the input data;

[0013] Generate a control signal of a multiplexer in a convolution calculation according to a random bit stream corresponding to the weight coefficient;

[0014] Execute a convolution operation of the convolution kernel in the CNN on the random bit stream corresponding to the input data according to the control signal to obtain a random bit stream after the convolution calculation is completed;

[0015] The random bit stream after the convolution calculation is converted into a binary number and the scaled data is restored to obtain the convolution processing result corresponding to the input data.

[0016] One of the above technical solutions has the following advantages and beneficial effects:

[0017] The above-mentioned controllable scalable convolution processing device and method based on random calculation, by sharing the pseudo-random number sequence generated by the random number source in the random number generation module, makes one round of convolution calculation use only one linear feedback shift register, greatly reducing the hardware cost and calculation overhead, and at the same time, the random number generation module shifts and swaps the pseudo-random number sequence through shuffling operations, effectively weakening the correlation between data, thereby greatly reducing the precision error caused by correlation in random calculation. Then, the convolution calculation module uses a JK trigger to replace the binary divider to generate the control signal of the multiplexer in the convolution calculation to perform the convolution operation of the convolution kernel in the CNN on the random bit stream corresponding to the input data, without relying on a large number of AND gates or XOR gates, greatly simplifying the complexity of the convolution calculation architecture, and further reducing the hardware cost, area occupancy and power consumption; finally, the data processing module is combined to complete the conversion and recovery of binary numbers. Compared with traditional technologies, the above design is simple and efficient, stable and reliable, has excellent performance, and is very conducive to the deployment and application of deep neural networks in resource-constrained environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 Schematic diagram of the overall structure of a controllable scaling convolution processing device based on random calculation in one embodiment;

[0021] Figure 2 A schematic diagram of the structure of a random number generation module in one embodiment;

[0022] Figure 3 Schematic diagram of the structure of a convolution calculation module in one embodiment;

[0023] Figure 4 Schematic diagram of the structure of a control signal generator in a convolution calculation module in one embodiment;

[0024] Figure 5 is a structural diagram of a data processing module in one embodiment;

[0025] Figure 6Schematic diagram of a flow chart of a controllable scalable convolution processing method based on random calculation in one embodiment. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0027] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0028] In one embodiment, see Figure 1 , a controllable scaling convolution processing device 100 based on random calculation is provided, including a random number generation module 11, a convolution calculation module 13 and a data processing module 15. The random number generation module 11 is used to share a pseudo-random number sequence generated by a random number source through a shuffling operation, and convert the data to be converted in the form of binary numbers into a random bit stream represented by probability; the data to be converted includes input data and weight coefficients corresponding to the input data. The convolution calculation module 13 is used to generate a control signal of a multiplexer in the convolution calculation according to the random bit stream corresponding to the weight coefficient, execute the convolution operation of the convolution kernel in the CNN on the random bit stream corresponding to the input data, and obtain a random bit stream after the convolution calculation is completed; the control signal is generated by using a JK trigger to replace the binary divider. The data processing module 15 is used to convert the random bit stream after the convolution calculation is completed into a binary number and perform recovery processing on the scaled data to obtain the convolution processing result corresponding to the input data.

[0029] The above-mentioned controllable scalable convolution processing device 100 based on random calculation, by sharing the pseudo-random number sequence generated by the random number source in the random number generation module 11, makes one round of convolution calculation use only one linear feedback shift register, greatly reduces the hardware cost and calculation overhead, and at the same time, the random number generation module 11 performs operations such as shifting and exchanging the pseudo-random number sequence through shuffling operations, effectively weakens the correlation between data, thereby greatly reducing the precision error caused by the correlation in random calculation. Then, the convolution calculation module 13 uses a JK trigger to replace the binary divider to generate the control signal of the multiplexer in the convolution calculation to perform the convolution operation of the convolution kernel in the CNN on the random bit stream corresponding to the input data, without relying on a large number of AND gates or XOR gates, greatly simplifying the complexity of the convolution calculation architecture, and further reducing the hardware cost, area occupancy and power consumption; finally, the data processing module 15 is combined to complete the conversion and recovery of binary numbers. Compared with traditional technologies, the above-mentioned design is simple and efficient, stable and reliable, has excellent performance, and is very conducive to the deployment and application of deep neural networks in resource-constrained environments.

[0030] It should be noted that the random number generation module 11 is used to convert data in general binary form into data in the form of a random bit stream (SN) that satisfies random calculations.

[0031] In one embodiment, the random number generation module 11 includes a linear feedback shift register, multiple shuffling units and multiple probability conversion circuits. The linear feedback shift register is used to provide a pseudo-random number sequence. Each shuffling unit shuffles the random numbers in the pseudo-random number sequence through circular shift, random exchange and flipping strategies. Each probability conversion circuit is composed of a comparator, which is used to compare the data to be converted with the shuffled random number bit by bit, and output a random bit stream represented by probability.

[0032] like Figure 2 As shown, the random number generation module 11 is composed of a linear feedback shift register (LFSR), multiple shuffle units (Shuffle Unit, SU) and multiple probability conversion circuits (PCC). Among them, in the random number generation module 11, the linear feedback shift register is used as a random number source to generate a pseudo-random number sequence. The shuffle unit shuffles the random numbers in the pseudo-random number sequence through circular shift, random exchange and flipping strategies, so that the data shares a linear feedback shift register and reduces the correlation of the data. The probability conversion circuit is composed of a comparator (<) for converting the data to be converted (i.e., the target data to be converted) x (is the input data from the input image) and the corresponding weight coefficients w) and the shuffled random number are sent to the comparator for bitwise comparison, and a random bit stream represented by probability is output. In this way, in the random number generation module 11, the pseudo-random number sequence generated by the linear feedback shift register is shared, so that one round of convolution calculation uses only one linear feedback shift register, which greatly reduces the hardware cost and calculation overhead. At the same time, by shuffling and performing operations such as shifting and swapping the pseudo-random number sequence, the correlation between the data is effectively weakened, thereby greatly reducing the precision error caused by the correlation in the random calculation.

[0033] In one embodiment, the number of bits of the cyclic shift of the shuffle unit is k , randomly swapped position scales p And the flip signal q The setting rules are:

[0034] , , (1)

[0035] in, k , p , q < n , n is the number of output data bits of the linear feedback shift register.

[0036] It can be understood that three parameters (flag quantities) need to be set in the shuffle unit, namely the number of bits of the cyclic shift k , randomly swapped position scales p And the flip signal q ,in k , p , q < n , n is the number of bits of the output data of the linear feedback shift register. In order to minimize the correlation of the data, the setting rules of the above three parameters can be shown in the following formula (1). According to formula (1), the random number output by the linear feedback shift register is first cyclically shifted in the shuffle unit. k and in p bit and p +1 bit is swapped, and then the q Flip (invert) the digits.

[0037] Specifically, a linear feedback shift register is used to generate random numbers, and then the random numbers are generated according to the preset flag quantity. k , p , q , the output of the linear feedback shift register is circularly shifted in the shuffle unit k Position, and p bit andp +1 bit is swapped, and then the q For example, to set the number of data bits n = 8 (the same applies to any other example of data bit number), the pseudo-random number sequence output by the linear feedback shift register is { r 1, r 2, r 3, r 4, r 5, r 6, r 7, r 8}, where , then in this embodiment k = 4, p = 2, q = 6, the random number sequence after shuffling is { r 5, r 7, r 6, r 8, r 1, ~ r 2, r 3, r 4}, "~" means flip. After the shuffle operation is completed, the generated random number is compared with the target data to be converted. x Connect to the corresponding probability conversion circuit for bitwise comparison and finally output the target data x The corresponding random bit stream (such as Figure 2 In Output 1 to Output 7).

[0038] In one embodiment, when multiple shuffling operations are performed using each shuffling unit, the number of bits of the cyclic shift of the shuffling unit is k Set according to the set sequence rules, the sequence rules are { n / twenty one, n +1 / 2, 2, n +2 / 2, 3, … , n -1}; when k = 1, the random swap setting in the shuffle unit is p Position and p +2 digits.

[0039] It can be understood that if multiple shuffling operations are to be performed, in order to keep the data generated before and after low correlation, the number sequence rule can be used to shuffle the data. k Set the value: { n / twenty one, n +1 / 2, 2, n +2 / 2, 3, … , n-1}. At the same time, in order to make the shuffle operation always effective, it is necessary to limit the maximum number of times it is executed in each round of operation to n -1. When k = 1, in order to avoid the conflict between the cyclic shift and random swap, the random swap is set in the first p Position and p +2 digits.

[0040] Specifically, the number of data bits is still set n = 8 as an example (the same applies to any other example of the number of data bits), if multiple shuffling is required, k The value is set according to the above sequence rule, that is, {4, 1, 5, 2, 6, 3, 7}, and the maximum number of shuffles is 7. After the shuffle operation is completed, the generated random number is compared with the target data to be converted. x Connect a probability conversion circuit to perform bit-by-bit comparison and finally output the target data x The corresponding random bit stream.

[0041] In one embodiment, the convolution calculation module 13 includes a control signal generator, a symbol processing unit, a multiplication accumulation calculation unit and a bias addition calculation unit. The control signal generator is used to generate a control signal for each multiplexer in the multiplication accumulation calculation unit according to the random bit stream corresponding to the weight coefficient, and the control signal generator is composed of a plurality of JK flip-flops, a plurality of AND gates and a plurality of OR gates. The symbol processing unit includes a plurality of XOR gates that are consistent with the data volume of the input data, and is used to complete the symbol processing of the random bit stream corresponding to the input data. The multiplication accumulation calculation unit and the bias addition calculation unit are both composed of a multiplexer, and the multiplication accumulation calculation unit is used to complete the multiplication accumulation calculation of the input data after the symbol processing according to the control signal, and the bias addition calculation unit is used to perform the bias addition calculation with a scaling factor of 0.5 using the output of the multiplication accumulation calculation unit and the bias coefficient to obtain the random bit stream after the convolution calculation is completed. The value of the bias coefficient is obtained in advance by pre-training.

[0042] It can be understood that the convolution calculation module 13 is used to perform the convolution operation of the convolution kernel in the CNN on the input image, such as Figure 3 As shown, the convolution calculation module 13 consists of a Figure 4 The control signal generator 131, a sign processing unit 133, a multiplication and accumulation calculation unit 135 and a bias addition calculation unit 137 are shown.

[0043] Among them, in the convolution calculation module 13, the control signal generator 131 is used to generate the control signal of the multiplexer in the convolution calculation, and the control signal generator 131 is composed of a number of JK flip-flops, AND gates and OR gates. The symbol processing unit 133 is used to complete the symbol processing of the input data, and is mainly composed of a plurality of XOR gates, and the number of XOR gates is consistent with the data volume of the input data. The multiplication and accumulation calculation unit 135 and the bias addition calculation unit 137 are used to complete the core convolution operation, which is mainly calculated by the multiplexer. At the same time, since the multiplexer structure has correlation insensitivity to the input data, in this embodiment, the linear feedback shift register of the input data can be directly shared, and the shuffling operation only needs to be performed in the control signal part of the multiplexer.

[0044] In this way, the JK flip-flop is used to replace the binary divider to generate the control signal, and the convolution calculation is completed through a simple XOR gate and multiplexer structure. There is no need to rely on a large number of AND gates or XNOR gates, which greatly simplifies the complexity of the operation architecture and further reduces the hardware cost, area occupancy and power consumption.

[0045] Specifically, in the control signal generator 131, the absolute value of the weight calculated in each round of convolution is input (such as , i =1,2,3,…, n ) corresponds to a random bit stream. According to the characteristics of the random bit stream, it can be regarded as a Bernoulli sequence. When the input of the JK trigger satisfies the Bernoulli sequence, its output state satisfies formula (2):

[0046] (2)

[0047] Among them, each P is the probability represented by the random bit stream, that is, the value of the weight. For the convenience of representation, the probability is written as a specific value. If the weight and Connected to a JK flip-flop, the output Q is as shown in formula (3):

[0048] (3)

[0049] By analogy, the JK flip-flop can generate all the control signals required for convolution operations without the need for additional complex operations such as binary division of weights in advance. k = 9 rounds of convolution operation, the number of data bits at this time n = 9, you need to enter , , , … , 9 random bit stream weight values ​​(it should be noted that at this time, the number of output data bits of the linear feedback shift register in the random number generation module 11 is n The setting must be greater than 9 so that the shuffle operation can be performed at least 9 times. In real applications, the output data bit number of the linear feedback shift register is usually much greater than 9), and the control signals required for all convolution calculations are calculated through 5 JK flip-flops and some AND gates and OR gates, without the need for additional complex operations such as binary division of the weights in advance.

[0050] Furthermore, in the sign processing unit 133, the sign of the weight coefficient is first separated from the input data, and a signal value is used sign Record the sign of the weight and sign The value of the input data x (like x 1, x 2, x 3, … x 9) Perform XOR operation respectively. Signal value sign The definition of is shown in formula (4):

[0051] (4)

[0052] in, For input data The corresponding weight coefficient, when the weight is non-negative sign ( w i )=0, XOR input data x The value remains unchanged; when the weight is negative sign ( w i )=1, XOR input data x The value is flipped, which is consistent with the sign of the result of the general multiplication operation. In a round of convolution calculation, the sign processing only needs to be performed once in the initial stage.

[0053] Furthermore, in the convolution calculation module 13, as Figure 3 As shown, the convolution kernel size can usually be set to 3×3, then n = 9, that is, each round of convolution performs 9 data multiplication and accumulation calculations and bias addition calculations. The main part of the convolution calculation module 13 is composed of 9 multiplexers and 9 XOR gates. The tree depth of the multiplexer is +1 = 5. The XOR gate completes the sign bit preprocessing. The control signal of the multiplexer in the last layer is 0.5 to complete the bias addition calculation. The random number source of the control signal of the different multiplexers in each layer sets different shuffling transformation rules, that is, the variable controlling the cyclic shift kSet it according to the above number series rules, such as {4, 1, 5, 2, 6}.

[0054] Furthermore, the multiplication-accumulation calculation unit 135 sends the input data and control signal after the sign processing to the multiplexer, and the multiplexer scales the data according to the relationship between the absolute values ​​of the weights and completes a multiplication-accumulation calculation. n When the value is 2, the scaling operation process is shown in formula (5):

[0055] (5)

[0056] Among them, the scaling factor is the reciprocal of the absolute value of the weight coefficient. The transformation of equation (5) is shown in equation (6):

[0057] (6)

[0058] in, is the sign( w i ) and input data x According to formula (6), the multiplexer is used to select the output according to the control signal of the weight ratio, and the coefficient value is fitted by selecting the control signal of 0 and 1 in the multiplexer to complete the operation. Among them, the scaling coefficient of the multiplexer is Similarly, when n is a normal value, the scaling factor of the multiplexer is , the operation performed by the multiplication and accumulation unit is shown in formula (7):

[0059] (7)

[0060] Further, in the bias addition calculation unit 137, the output of the above multiplication and accumulation operation and the bias coefficient ( bias ) is sent to the next multiplexer to perform a bias addition calculation with a scaling factor of 0.5, thus completing a round of convolution operation. According to the scaling factor of the multiplication and accumulation calculation unit 135, the bias coefficient needs to be unified before the bias addition operation, that is, the bias coefficient is multiplied by the scaling factor after the multiplication and accumulation operation, that is, Since the bias coefficient value is obtained in advance by pre-training, this operation can be completed before the convolution calculation, and no additional hardware consumption is generated at this stage. S is 0.5, and the bias coefficient is recorded as b , the bias coefficient has been pre-processed to unify the coefficients, and the output after the calculation is completed is shown in formula (8):

[0061] (8)

[0062] According to formula (8), after a round of convolution calculation is completed, the scaling factor generated by the multiplexer is .

[0063] More specifically, in the convolution calculation, the multiplexer control signal is transformed from the weight parameters corresponding to the input data of each round of calculation. The selection of each pair of parameters can be combined according to the principle of proximity. The calculation process is as follows, for the first layer of multiplexer structure:

[0064] (9)

[0065] The same goes for the multiplication and accumulation operations of other inputs of this layer:

[0066] (10)

[0067] (11)

[0068] (12)

[0069] (13)

[0070] For the second layer multiplexer structure:

[0071] (14)

[0072] The same goes for the multiplication and accumulation operations of other inputs of this layer:

[0073] (15)

[0074] The same is true for the third-layer multiplexer structure:

[0075] (16)

[0076] For the fourth layer of multiplexer structure, which is the last layer of multiplication and accumulation calculation, the same is true:

[0077] (17)

[0078] For the fifth layer of multiplexer structure, namely the bias addition module, the control signal of the multiplexer S Set to 0.5, the bias coefficient is b , the bias coefficient has been pre-processed to unify the coefficients, then:

[0079] (18)

[0080] According to the above calculation process, after one round of convolution calculation, the scaling factor generated by the multiplexer is ,in, n = 9.

[0081] In one embodiment, Figure 1 As shown, the data processing module 15 includes a counter 151 and a multiplier 153. The counter 151 is used to count the number of 1s in the random bit stream after the convolution calculation is completed, and convert the random bit stream after the convolution calculation into a binary number according to the probability of the counting result. The multiplier 153 is used to restore the scaled data of the binary number converted by the counter 151 according to the scaling factor of the convolution calculation, so as to obtain the convolution processing result corresponding to the input data.

[0082] It can be understood that the data processing module 15 is used to convert the random bit stream after the convolution calculation into a binary number and perform recovery processing on the scaled data, such as Figure 5 As shown, the data processing module 15 is composed of a counter 151 (CNT), an optional multiplier 153 (MUL) and an optional regularization operation (Reg) unit.

[0083] In the data processing module 15, the counter 151 is used to count the 1s in the bit stream output by the convolution calculation, and convert the result from the random bit stream into a binary number according to the probability of the count result. The multiplier 153 is used to complete the recovery processing of the scaled data, according to the scaling factor of the convolution calculation. At this stage, it is only necessary to compare the result with the inverse of the scaling factor By multiplying, that is, performing a binary multiplication, the original size of the data can be restored. In this way, the scaling coefficient range in the convolution calculation is controllable through a simple regularization configuration during training, which minimizes the accuracy error caused by the scaling effect of the multiplexer, and after the relevant calculation is completed, the scaled data is restored using the multiplier 153, thereby eliminating the impact of scaling.

[0084] In one embodiment, Figure 1 As shown, the data processing module 15 also includes a regularization operation unit 155, which is used to limit the Reg function within a set limit range during CNN training and maintain the data format of the random bit stream after the convolution calculation is completed for random calculation; the limit range is [-1, 1].

[0085] Further, in practical applications, it is usually not desirable to convert the data into a binary format after the convolution calculation is completed, but to retain the format of the random bit stream for performing other random calculations. In this case, the data processing module 15 does not use the multiplier 153 to restore the data, but uses a regularization operation (Reg) unit for processing.

[0086] Specifically, when training CNN, it is usually necessary to regularize the model to reduce the degree of overfitting. The weights generated by regularization generally conform to the normal distribution, and most of them are concentrated near 0. Figure 5 As shown in Figure 1, a range-limiting operation can be added to the Reg function during CNN training to keep its range in [-1, 1], thereby achieving the purpose of artificially controlling the scaling factor value and making it much smaller than the scaling factor generated by the multiplexer during general calculations, that is, , retaining the effective information in the convolution process to the greatest extent and reducing the impact of scaling factors on calculation accuracy. Therefore, when the module processes data, the data format of the random bit stream can be maintained for subsequent random calculations, and the data can be restored through the counter 151 and the multiplier 153 after the relevant operations are completed.

[0087] The above-mentioned controllable scalable convolution processing device based on random computing has a simple and efficient design, is stable and reliable, has excellent performance, and is very beneficial to the deployment and application of deep neural networks in resource-constrained environments.

[0088] In one embodiment, a controllable scaling convolution processing method based on random calculation is also provided, based on the above-mentioned controllable scaling convolution processing device 100 based on random calculation, such as Figure 6 As shown, the controllable scaling convolution processing method based on random calculation may include the steps of:

[0089] S12, converting the data to be converted in binary form into a random bit stream represented by probability; the data to be converted includes input data and weight coefficients corresponding to the input data;

[0090] S14, generating a control signal of a multiplexer in a convolution calculation according to a random bit stream corresponding to the weight coefficient;

[0091] S16, executing a convolution operation of the convolution kernel in the CNN on the random bit stream corresponding to the input data according to the control signal, to obtain a random bit stream after the convolution calculation is completed;

[0092] S18, converting the random bit stream after the convolution calculation into a binary number and performing a recovery process on the scaled data to obtain a convolution processing result corresponding to the input data.

[0093] The above-mentioned controllable scaling convolution processing method based on random calculation, by sharing the pseudo-random number sequence generated by the random number source in the random number generation module 11, makes one round of convolution calculation use only one linear feedback shift register, greatly reduces the hardware cost and calculation overhead, and at the same time, the random number generation module 11 performs operations such as shifting and exchanging the pseudo-random number sequence through shuffling operations, effectively weakens the correlation between data, thereby greatly reducing the precision error caused by the correlation in random calculation. Then, the convolution calculation module 13 uses a JK trigger to replace the binary divider to generate the control signal of the multiplexer in the convolution calculation to perform the convolution operation of the convolution kernel in the CNN on the random bit stream corresponding to the input data, without relying on a large number of AND gates or XOR gates, greatly simplifying the complexity of the convolution calculation architecture, and further reducing the hardware cost, area occupancy and power consumption; finally, the data processing module 15 is combined to complete the conversion and recovery of binary numbers. Compared with traditional technologies, the above-mentioned design is simple and efficient, stable and reliable, has excellent performance, and is very conducive to the deployment and application of deep neural networks in resource-constrained environments.

[0094] In one embodiment, during CNN training, the Reg function is limited within a set limit range through a regularization operation unit and the data format of the random bit stream after the convolution calculation is completed is maintained for random calculation; the limit range is [-1, 1].

[0095] It can be understood that the explanation of the above-mentioned components can be understood by referring to the corresponding features of the above-mentioned controllable scalable convolution processing device 100 based on random calculation, and will not be repeated in this embodiment.

[0096] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

[0098] In addition, the terms "one" and "multiple" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "one" or "multiple" may explicitly or implicitly include at least one of the features. In the description of the present invention, "multiple" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0099] In the present invention, unless otherwise clearly defined and specified, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a communication connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Claims

1. A controllable scaling convolution processing device based on random computing, characterized in that: include: A random number generation module, used for sharing a pseudo-random number sequence generated by a random number source through a shuffling operation, and converting the data to be converted in the form of binary numbers into a random bit stream represented by probability; The data to be converted includes input data and weight coefficients corresponding to the input data; A convolution calculation module, used to generate a control signal of a multiplexer in a convolution calculation according to a random bit stream corresponding to the weight coefficient, execute a convolution operation of a convolution kernel in a CNN on a random bit stream corresponding to the input data, and obtain a random bit stream after the convolution calculation is completed; the control signal is generated by using a JK flip-flop instead of a binary divider; A data processing module, used to convert the random bit stream after the convolution calculation into a binary number and perform recovery processing on the scaled data to obtain the convolution processing result corresponding to the input data; wherein the convolution calculation module includes a control signal generator, a symbol processing unit, a multiplication and accumulation calculation unit, and a bias addition calculation unit; The control signal generator is used to generate control signals for each multiplexer in the multiplication and accumulation calculation unit according to the random bit stream corresponding to the weight coefficient, and the control signal generator is composed of a plurality of JK flip-flops, a plurality of AND gates, and a plurality of OR gates; The symbol processing unit includes a plurality of XOR gates that are consistent with the data volume of the input data, and is used to complete the symbol processing of the random bit stream corresponding to the input data; The multiplication-accumulation calculation unit and the bias addition calculation unit are both composed of a multiplexer. The multiplication-accumulation calculation unit is used to complete the multiplication-accumulation calculation of the input data after sign processing according to the control signal. The bias addition calculation unit is used to use the output of the multiplication-accumulation calculation unit and the bias coefficient to perform a bias addition calculation with a scaling factor of 0.5 to obtain a random bit stream after the convolution calculation is completed; the value of the bias coefficient is obtained in advance by pre-training.

2. The controllable scaling convolution processing device based on random calculation according to claim 1, characterized in that: The random number generation module includes a linear feedback shift register, multiple shuffling units and multiple probability conversion circuits. The linear feedback shift register is used to provide the pseudo-random number sequence. Each of the shuffling units shuffles the random numbers in the pseudo-random number sequence through circular shift, random exchange and flipping strategies. Each of the probability conversion circuits is composed of a comparator, which is used to compare the data to be converted with the shuffled random numbers bit by bit and output the random bit stream represented by probability.

3. The controllable scaling convolution processing device based on random calculation according to claim 2, characterized in that: The number of bits of the cyclic shift of the shuffle unit k , randomly swapped position scales p And the flip signal q The setting rules are: in, k , p , q < n , n is the number of output data bits of the linear feedback shift register.

4. The controllable scaling convolution processing device based on random calculation according to claim 3 is characterized in that: When multiple shuffling operations are performed using each of the shuffling units, the number of bits of the cyclic shift of the shuffling unit k Set according to the set sequence rule, the sequence rule is { n / twenty one, n +1 / 2, 2, n +2 / 2, 3, … , n -1}; when k = 1, the random exchange in the shuffle unit is set in the first p Position and p +2 digits.

5. The controllable scaling convolution processing device based on random calculation according to any one of claims 1 to 4, characterized in that: The data processing module includes a counter and a multiplier. The counter is used to count the number of 1s in the random bit stream after the convolution calculation is completed, and convert the random bit stream after the convolution calculation into a binary number according to the probability of the counting result. The multiplier is used to restore the scaled data of the binary number converted by the counter according to the scaling factor of the convolution calculation to obtain the convolution processing result corresponding to the input data.

6. The controllable scaling convolution processing device based on random calculation according to claim 5, characterized in that: The data processing module also includes a regularization operation unit, which is used to limit the Reg function within a set limit range during CNN training and maintain the data format of the random bit stream after the convolution calculation is completed for random calculation; the limit range is [-1, 1].

7. A controllable scaling convolution processing method based on random computing, characterized in that: Based on the controllable scaling convolution processing device based on random calculation according to any one of claims 1 to 6, the controllable scaling convolution processing method based on random calculation comprises the steps of: Converting the data to be converted in binary form into a random bit stream represented by probability; the data to be converted includes input data and weight coefficients corresponding to the input data; Generate a control signal of a multiplexer in a convolution calculation according to a random bit stream corresponding to the weight coefficient; Execute a convolution operation of a convolution kernel in a CNN on a random bit stream corresponding to the input data according to the control signal to obtain a random bit stream after the convolution calculation is completed; The random bit stream after the convolution calculation is completed is converted into a binary number and the scaled data is restored to obtain the convolution processing result corresponding to the input data.

8. The controllable scaling convolution processing method based on random calculation according to claim 7 is characterized in that: During CNN training, the Reg function is limited within a set limit range through a regularization operation unit and the data format of the random bit stream after the convolution calculation is completed is maintained for random calculation; the limit range is [-1, 1].

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