Testing device and method for memory chip

Abstract

The invention discloses a testing device and method for a memory chip. The memory chip and the logic chip are attached face to face to form a stacked memory. The test device at least comprises: a plurality of probe test pads formed on the surface of the memory chip and used for receiving an external clock signal and a plurality of test signals, the plurality of test signals being sampled and read at a rising edge and a falling edge of the external clock signal; and a test command address generation unit for decoding the plurality of sampled test signals to generate a test command and a test address. The number of the plurality of test signals is smaller than the number of the plurality of external operation signals input by the memory chip in the normal mode.

Description

Technical Field

[0001] The invention relates to a testing device and method for a memory chip. Background Art

[0002] like Figure 1A and 1B As shown, the stacked semiconductor device includes heterogeneous chips, for example, a memory device formed by stacking a logic chip 10 and a memory chip 20 can be obtained by wafer-on-wafer (WoW) technology. That is, the surfaces of the logic chip 10 and the memory chip 20 are bonded in a face-to-face manner. As a means of interconnecting signals between the logic chip 10 and the memory chip 20, face-to-face bonding can be used, in which metal terminals 12 and 22 provided on the surfaces of the two chips can be directly bonded. For example, the surface of the logic chip 10 has a plurality of metal terminals 12, and the surface of the memory chip 20 also has a plurality of metal terminals 22 corresponding in position. The plurality of metal terminals 12 of the logic chip 10 are respectively connected to the internal wires 14 of the logic chip 10, and similarly, the plurality of metal terminals 22 of the memory chip 20 are also respectively connected to the internal wires 24 of the memory chip 20. Thus, the logic chip 10 and the memory chip 20 can connect their internal circuits 14 and 24 through the metal terminals 22. These signals include clock signals, command signals, addresses, input data, and output data, for example.

[0003] In addition, in the case of memory devices, before wafer stacking and bonding, a probe test is performed on the memory wafer to determine whether the dies in the wafer are qualified. Figure 2 As shown above, in addition to the above-mentioned multiple metal terminals 22, the surface of the memory chip 20 also has multiple probe test pads 26, wherein the configuration positions of the metal terminals 22 and the probe test pads 26 are only for illustration. The probe test pads 26 allow the probe to fall on the memory device for testing. In addition, these signals are the same in normal operation and probe testing. Generally speaking, the number of probe pads 26 is greater than the number of metal terminals 22, and the area of ​​the two is about 60μm 2 With 1μm 2 Therefore, if the number of the probe pads 26 is large, the area of ​​the memory chip 20 will be greatly increased.

[0004] The number of probe pads 26 required for testing depends on how many signals there are to control the memory operation. On the other hand, for the memory chip 20, the operation time of the probe test will be slower than the normal operation time of the memory device, because the main test item focuses on the integrity of the memory device, rather than the speed performance.

[0005] Therefore, how to reduce the number of probe test pads without affecting the probe test is a topic that needs to be considered. Summary of the invention

[0006] According to one embodiment of the present invention, a test device for a memory chip is provided. The memory chip and the logic chip are bonded face to face to form a stacked memory. The test device at least includes: a plurality of probe test pads formed on the surface of the memory chip for receiving an external clock signal and a plurality of test signals, wherein the plurality of test signals are sampled and read at the rising edge and the falling edge of the external clock signal; and a test command address generating unit for decoding the sampled plurality of test signals to generate a test command and a test address. The number of the plurality of test signals is less than the number of the plurality of external operation signals input to the memory chip in normal mode.

[0007] According to one embodiment of the present invention, in the test device of the above-mentioned memory chip, the test command address generating unit also includes: a test command decoder, which decodes the multiple test signals based on the sampled signals relative to the rising edge of the external clock signal to generate the test command; and a test address decoder, which decodes the multiple test signals based on the sampled signals relative to the rising edge of the external clock signal to generate the test address.

[0008] According to an embodiment of the present invention, in the test device of the memory chip, the test command address generating unit further includes: a command address selector, which is used to receive the test command and the test address for testing, and receive the command and address for normal operation. When the command address selector receives a test enable signal to enable testing, the command address selector outputs the test command and the test address. When the command address selector receives the test enable signal to inhibit testing, the command address selector outputs the command and the address for normal operation.

[0009] According to an embodiment of the present invention, in the memory chip test device, the plurality of test signals include an external chip selection signal and a plurality of external command address signals.

[0010] According to an embodiment of the present invention, in the test device of the memory chip, the test command address generating unit further includes: first, second, third, fourth and fifth latches. The first latch receives the plurality of external command address signals, latches the plurality of external command address signals at the rising edge of the external clock signal, and the second latch latches the output of the first latch at the falling edge of the external clock signal, and outputs a plurality of internal rising edge command address signals. The third latch receives the plurality of external command address signals, latches the plurality of external command address signals at the falling edge of the external clock signal, and outputs a plurality of internal falling edge command address signals. The fourth latch receives the external chip select signal, latches the external chip select signal at the rising edge of the external clock signal, and the fifth latch latches the output of the fourth latch at the falling edge of the external clock signal, and outputs an internal chip select signal. The plurality of internal rising edge command address signals, the plurality of internal falling edge command address signals and the internal chip select signal are transmitted to the test command decoder. The plurality of internal rising edge command address signals and the plurality of internal falling edge command address signals are transmitted to the test address decoder.

[0011] According to an embodiment of the present invention, in the above-mentioned memory chip testing device, the first, the second, the third, the fourth and the fifth latches are edge-triggered flip-flops.

[0012] According to an embodiment of the present invention, in the above memory chip test device, the time point when the multiple test signals are sampled and read differs from the time point when the test command and the test address are generated by at least one cycle of the external clock signal.

[0013] According to an embodiment of the present invention, in the above-mentioned memory chip test device, a plurality of first metal terminals are configured on the surface of the memory chip, and a plurality of second metal terminals are configured on the surface of the logic chip, and the configuration positions of the plurality of first metal terminals correspond to the configuration positions of the plurality of second metal terminals, and the plurality of first metal terminals and the second metal terminals are face-to-face bonded to bond the logic chip and the memory chip. In the normal operation mode, the external clock signal and the external operation signal are respectively transmitted to the memory chip via the plurality of first metal terminals.

[0014] According to an embodiment of the present invention, in the above memory chip testing device, an area of ​​each of the plurality of probe test pads is larger than an area of ​​each of the plurality of first metal terminals.

[0015] According to an embodiment of the present invention, in the above-mentioned memory chip testing device, the memory chip is a DRAM memory chip.

[0016] According to another embodiment of the present invention, a method for testing a memory chip is provided. A method for testing a memory chip, wherein the memory chip and a logic chip are bonded face to face to form a stacked memory, and the method at least comprises: receiving an external clock signal and multiple test signals by probing multiple probe test pads on the surface of the memory chip; sampling and reading the multiple test signals at the rising edge and the falling edge of the external clock signal; and decoding the sampled multiple test signals to generate a test command and a test address. The number of the multiple test signals is less than the number of the multiple external operation signals input to the memory chip in normal mode.

[0017] According to one embodiment of the present invention, the testing method of the above-mentioned memory chip also includes: decoding the multiple test signals based on the sampled ones relative to the rising edge of the external clock signal to generate the test command; and decoding the multiple test signals based on the sampled ones relative to the rising edge of the external clock signal to generate the test address.

[0018] According to one embodiment of the present invention, the testing method of the above-mentioned memory chip also includes: receiving the test command and the test address for testing, and receiving the command and address for normal operation; when the command address selector receives a test enable signal to enable the test, outputting the test command and the test address; and when the command address selector receives the test enable signal to inhibit the test, the command address selector outputs the command and the address for normal operation.

[0019] According to an embodiment of the present invention, in the above-mentioned memory chip testing method, the plurality of test signals include an external chip selection signal and a plurality of external command address signals. According to one embodiment of the present invention, the test method of the above-mentioned memory chip also includes: receiving the multiple external command address signals, latching the multiple external command address signals at the rising edge of the external clock signal, and latching the latched multiple external command address signals at the falling edge of the external clock signal to output multiple internal rising edge command address signals; receiving the multiple external command address signals, latching the multiple external command address signals at the falling edge of the external clock signal to output multiple internal falling edge command address signals; receiving the external chip select signal, latching the external chip select signal at the rising edge of the external clock signal, and latching the latched external chip select signal at the falling edge of the external clock signal, and outputting the internal chip select signal; decoding based on the multiple internal rising edge command address signals, the multiple internal falling edge command address signals and the internal chip select signal to output the test command; and decoding based on the multiple internal rising edge command address signals and the multiple internal falling edge command address signals to output the test address.

[0020] According to an embodiment of the present invention, in the above-mentioned memory chip testing method, the time point when the multiple test signals are sampled and read differs from the time point when the test command and the test address are generated by at least one cycle of the external clock signal.

[0021] According to an embodiment of the present invention, in the above-mentioned memory chip testing method, the memory chip is a DRAM memory chip.

[0022] Based on the above, according to the embodiments of the present invention, the number of probe pads used in the test operation can be reduced, and thus the size of the memory chip can be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A and Figure 1B It is a schematic diagram of the stacking method of a stacked memory device.

[0024] Figure 2 yes Figure 1A and Figure 1B Schematic diagram of the probe pad distribution of the memory chip.

[0025] Figure 3 The timing diagram of the memory chip under normal operation is shown as an example.

[0026] Figure 4 A timing diagram of a memory chip when performing a test operation according to an embodiment of the present invention is illustrated.

[0027] Figure 5 is a schematic diagram of a circuit architecture of a testing method according to an embodiment of the present invention.

[0028] Figure 6 A schematic diagram of a memory chip circuit that can be used with a test circuit according to an embodiment of the present invention is shown.

[0029] Figure 7 4 is a timing diagram of a test method for a memory chip according to an embodiment of the present invention.

[0030] Figure 8 is a timing diagram of the normal operation of the memory chip according to an embodiment of the present invention.

[0031]

Explanation of symbols

[0032] 10: Logic chip

[0033] 12, 12_1, 12_2, 12_3, 12_4, 22: Metal terminals

[0034] 14, 24: Internal lines

[0035] 20: Memory chip

[0036] 26, 26-1, 26-2, 26-3j: Probe pads

[0037] 30-1, 30-2, 30-3j: Probe input buffer

[0038] 40: Test command decoder

[0039] 42: Test address decoder

[0040] 50_1, 50_2, 50_3, 50_4: Terminal input buffer

[0041] 60: Command decoder

[0042] 62: Address decoder

[0043] 70: Command address selector

[0044] CS_n_r, CS_n_r0: internal chip select signal

[0045] CK: internal clock signal

[0046] RAS_n: column address strobe signal

[0047] CAS_n: row address select signal

[0048] WE_n: Write enable signal

[0049] CA<7:0>: Command address signal

[0050] A<11:0>: Address signal

[0051] EX_CS_n: External chip select signal

[0052] EX_CK: external clock signal

[0053] EX_CA <j>: External command address signal

[0054] EX_RAS_n: External column address strobe signal

[0055] EX_CAS_n: External address selection signal

[0056] EX_WE_n: External write enable signal

[0057] EX_A<11:0>: External address

[0058] CA_r <0> ~CA_r <7> 、CA_r0 <j>: Internal rising edge command address signal

[0059] CA_f <0> ~CA_f <7> : Internal falling edge command address signal

[0060] FF_1~FF_5: Latch

[0061] CK_r: internal rising edge clock signal

[0062] CK_f: internal falling edge clock signal

[0063] ACT_test, PRE_test, WRITE_test, READ_test, REF_test: test commands

[0064] ACT_norm, PRE_norm, WRITE_norm, READ_norm, REF_norm: Normal operation commands

[0065] ACT, PRE, WRITE, READ, REF: Output commands

[0066] XAD__test<11:0>, YAD_test<8:0>: test address

[0067] XAD__norm<11:0>, YAD_norm<8:0>: Normal operation address

[0068] XAD<11:0>, YAD<8:0>: output address

[0069] T1, T2, T3, T0r, T0f, T1r, T1f, T2r, T2f, Tr0, Tf0, Tr1, Tf1, Tr2, Tf2: time point

[0070] Ts: set time

[0071] Th: hold time DETAILED DESCRIPTION

[0072] Figure 3 The timing diagram of the memory chip under normal operation is shown below. Figure 4 The timing diagram of the memory chip when performing the test operation according to the embodiment of the present invention is illustrated. Figure 3 and Figure 4 The concept of the test operation of the present invention is briefly described. Through the test operation of the present invention, the number of probe test pads on the memory chip can be reduced. Here, as an example, the memory chip can be composed of a dynamic random access memory (DRAM), and of course it can also be composed of other types of memory.

[0073] like Figure 3 As shown, when the memory chip is in normal operation, for example, at the rising edge of the clock signal CK at time point T1, the chip select signal CS_n is pulled low, and the input command signal RAS_n (column address strobe signal), CAS_n (row address strobe signal), WE_n (write enable signal) and address signal A<11:0> are sampled (read). These clock signal CK, chip select signal CS_n, command signals RAS_n, CAS_n and WE_n and address signal A<11:0> are, for example, obtained by Figure 2 The illustrated metal terminals 22 are input into the memory chip 20 .

[0074] Here, the input command signals RAS_n, CAS_n and WE_n and the address signal A<11:0> must remain valid from the setup time Ts to the hold time Th relative to the rising edge of the clock signal CK. In addition, when the chip select signal CS_n becomes a low level at the rising edge of the clock signal CK (such as Figure 3 The time points T1, T3, etc. in the memory are defined by the RAS_n, CAS_n and WE_n and the address signal A<11:0>. The decoder can define each internal command and internal address (for controlling the memory cell array). Table 1 lists the various commands defined by RAS_n, CAS_n, WE_n and A<11:0>. As shown in Table 1, these commands include: no operation command (no operation) NOP, active command (active) ACT, precharge command (precharge) PRE, write command (write) WRITE, read command (read) READ, refresh command (refresh) REF, etc.

[0075] Table 1

[0076] CMD CK CS_n RAS_n CAS_n WE_n A<11:0> NOP Rising edge H DC DC DC DC ACT Rising edge L L H H XA<11:0> PRE Rising edge L L H L DC WRITE Rising edge L H L L OF<8:0> READ Rising edge L H L H OF<8:0> REF Rising edge L L L H DC

[0077] DC: Ignore the conditions

[0078] When performing probe testing on memory chips in the prior art, the same method as normal operation is basically adopted. However, the method of performing probe testing in this embodiment is different from the normal operation method. According to an embodiment of the present invention, when performing probe testing on a memory chip, various internal commands defined by signals such as RAS_n, CAS_n, WE_n, and A<11:0> are not used. Instead, signal CA<7:0> is used as an external input to define various internal commands of the memory chip. Signal CA<7:0> requires 8 probe pads, which is only an example here. Signal CA <j>The number j of (j=0-j-1) can be adjusted according to actual needs. In addition, the embodiment of the present invention further uses the rising and falling edges of the clock signal CK to sample the input signal to cooperate with the chip selection signal CS_n and the signal CA<7:0> to define various internal commands of the memory chip.

[0079] Figure 4 The timing diagram of the memory chip when performing the test operation according to the embodiment of the present invention is illustrated. Figure 4 As shown, under the test operation of the memory chip, for example, at the rising edge of the clock signal CK at the time point T0r and the falling edge at the time point T0f, the chip selection signal CS_n is pulled low, and the input external signal CA<7:0> is sampled (read), namely cmad_r and cmad_f, where cmad_r represents the command and address input at the rising edge of the clock signal CK, and cmad_f represents the command and address input at the falling edge of the clock signal CK. Here, the input signal CA<7:0> must remain valid between the setting time Ts and the holding time Th relative to the rising edge of the clock signal CK and between the setting time Ts and the holding time Th relative to the falling edge of the clock signal CK. These clock signal CK, chip selection signal CS_n, and signal CA<7:0> are, for example, obtained by Figure 2 Probe pads 26 are illustrated as inputs into the memory chip 20 .

[0080] In addition, the signals cmad_r and cmad_f input through CA<7:0> can define each internal command and internal address (test command and address) through the test decoder. That is, when the clock signal CK is at the rising edge, the chip select signal CS_n is at a low level, and at the rising edge (such as time point T0r) and falling edge (such as time point T0f) of the same clock signal CK, cmad_r and cmad_f are input through the signal CA<7:0>. Thus, each command and address of the public test memory chip is defined by the combination of the command and address in cmad_r and cmad_f.

[0081] Table 2 lists various commands defined by signal CA<7:0>. As shown in Table 2, these commands include: no operation command (NOP), active command (ACT), precharge command (PRE), write command (WRITE), read command (READ), refresh command (REF), etc.

[0082] Table 2

[0083]

[0084]

[0085] In the above-described example, compared to the existing test method, 2 probe pads are required for inputting the clock signal CK and the chip selection signal CS_n, 3 probe pads are required for inputting the signals RAS_n, CAS_n and WE_n, and 12 probe pads are required for inputting the address signal A<11:0>. On the contrary, the embodiment of the present invention only requires 8 probe pads for inputting the signal CA<7:0>. Therefore, in addition to the probe pads for inputting the clock signal CK and the chip selection signal CS_n, only 8 probe pads are required for inputting the signal CA<7:0>. Therefore, the number of probe pads for testing can be greatly reduced.

[0086] Next reference Figure 5 A schematic diagram of a circuit structure for implementing the testing method of the present invention is shown in FIG. Figure 7 1 is a timing diagram of a test method for a memory chip according to an embodiment of the present invention. Figure 5 and Figure 7 To illustrate the test method and architecture of the embodiment of the present invention. To distinguish, "EX_" is added before each signal to indicate a signal input from the outside of the memory chip 20.

[0087] like Figure 5 As shown, in Figure 2 The memory chip 20 is provided with probe test pads 26-1, 26-2 and 26-3. <j>(In this example, j=0-7) Therefore, in this example, 10 probe test pads are provided on the memory chip 20 for the probes to contact with to input external signals, which include the external clock signal EX_CK, the external chip select signal EX_CS_n and the external command address signal EX_CA <j>In addition, the memory chip 20 is provided with probe test pads 26-1, 26-2, 26-3. <j>Corresponding probe input buffers 30-1, 30-2, 30-3 <j>A test command decoder 40 and a test address decoder 42 are also provided in the memory chip 20 for testing. Figure 5 and Figure 6 The probe input buffers 30-1, 30-2, 30-3 in <j>, the latches FF_1 to FF_5 , the test command decoder 40 , the test address decoder 42 , and the command address selector 70 may be collectively referred to as a test command address generating unit.

[0088] When the memory chip 20 is in the test mode, the test enable signal becomes high level to enable the test-related components in the memory chip 20, such as the probe input buffers 30-1, 30-2, 30-3. <j>, a test command decoder 40 and a test address decoder 42. When testing, the probe of the test device will contact the probe test pads 26-1, 26-2, 26-3 on the memory chip 20. <j>Contact to input the above external clock signal EX_CK, external chip select signal EX_CS_n and external command address signal EX_CA <j>To the memory chip 20.

[0089] After that, the external pulse signal EX_CK, the external chip select signal EX_CS_n and the external command address signal EX_CA <j>The pads 26_1, 26_2, and 26_3 are tested by the probes. <j>, transmitted to the probe input buffers 30_1, 30_2, 30_3 corresponding to each other <j>.

[0090] Then, the pin test pad 26_1 for the external clock signal EX_CK outputs the internal rising edge clock signal CK_r and the internal falling edge clock signal CK_f. Figure 7 As shown, the internal rising edge clock signal CK_r is generated based on the rising edge of the external clock signal EX_CK, and the basic waveform and timing are the same. The internal falling edge clock signal CK_f is generated based on the falling edge of the external clock signal EX_CK, and the basic waveform is the same but the time is offset by half a cycle.

[0091] In addition, the external chip select signal EX_CS_n input from the probe pad 26_2 is buffered in the probe input buffer 30_2. Thereafter, it is latched in the latch FF_4 based on the internal rising edge clock signal CK_r. The latch FF_4 outputs the internal chip select signal CS_n_r0. Thereafter, it is latched in the latch FF_5 based on the internal falling edge clock signal CK_f. The latch FF_5 outputs the internal chip select signal CS_n_r. Thereafter, the internal chip select signal CS_n_r0 generated by the external chip select signal EX_CS_n based on the internal rising edge clock signal CK_r and the internal chip select signal CS_n_r generated based on the internal falling edge clock signal CK_f are transmitted to the test command decoder 40.

[0092] like Figure 7 As shown, relative to the time point Tr0 (the rising edge of the external clock signal EX_CK), the external chip select signal EX_CS_n becomes a low level. Thereafter, the external chip select signal EX_CS_n becomes a low level. The external chip select signal EX_CS_n generates the internal chip select signal CS_n_r0 based on the rising edge of the external clock signal EX_CK, and its effective period is from the time point Tr0 to the time point Tr1. In addition, the external chip select signal EX_CS_n generates the internal chip select signal CS_n_r based on the falling edge of the external clock signal EX_CK (time point Tf0), and its effective period is from the time point Tf0 to the time point Tf1.

[0093] In addition, if Figure 5 As shown, the external command address signal EX_CA <j>Via probe pad 26_3 <j>Input to the memory chip 20 and buffered in the corresponding probe input buffer 30_3 <j>Here, taking EX_CA<7:0> as an example, 8 slave probe pads 26_3 are required. <j>and 8 probe input buffers 30_3 <j>, this number can be changed according to the actual design requirements. External command address signal EX_CA <j>Then, it is latched in latch FF_1 based on the internal rising edge clock signal CK_r. Latch FF_1 outputs internal command address signal CA_r0 <j>The output signal CA_r0 of latch FF_1 <j>Then, the internal falling edge clock signal CK_f is latched in the latch FF_2. After that, the latch FF_2 outputs the internal rising edge command address signal CA_r <j>Similarly, the external address signal CA <j>Then, it is latched in latch FF_3 based on the internal falling edge clock signal CK_f. Latch FF_3 outputs the internal falling edge command address signal CA_f <j>After that, the internal rising edge command address signal CA_r is generated. <j>and the internal falling edge command address signal CA_f <j>The signal is further transmitted to the test command decoder 40 and the test address decoder 42 .

[0094] Each of the latches FF_1 to FF_5 can be implemented by a trigger. For example, an edge-triggered trigger can be used to implement each of the latches FF_1 to FF_5. Each of the latches FF_1 to FF_5 can be designed to latch the input signal at the rising edge or the falling edge of the external clock signal EX_CK.

[0095] Next, the test command decoder 40 receives the internal rising edge command address signal CA_r <0> ~CA_r <7> , Internal falling edge command address signal CA_f <0> ~CA_f <7> And the internal chip selection signal CS_n_r, and decode the input data values ​​to generate the test commands ACT_test, PRE_test, WRITE_test, READ_test, REF_test required for testing the memory chip 20. Also, as an example of decoding, you can refer to the comparison table listed in Table 2.

[0096] The test address decoder 42 receives the internal rising edge command address signal CA_r <0> ~CA_r <7> The internal falling edge command address signal CA_f <0> ~CA_f <7> , and decodes the input data value to generate test addresses XAD_test<11:0> and YAD_test<8:0>, i.e., row and column addresses of the memory cell array of the memory chip 20, which are assumed to be addressed by 12 bits. Also, as an example of decoding, the comparison table listed in Table 2 can be referred to.

[0097] Afterwards, the test commands ACT_test, PRE_test, WRITE_test, READ_test, and REF_test output by the test command decoder 40 are transmitted to Figure 6 Similarly, the test addresses XAD_test<11:0> and YAD_test<8:0> output by the test address decoder 42 are transmitted to the command address selector 70 shown in FIG. Figure 6 A command address selector 70 is shown.

[0098] like Figure 7 As shown, as mentioned above, the test method of the embodiment of the present invention samples and reads the external chip selection signal EX_CS_n at the rising edge and falling edge of the external clock signal EX_CK. At the time point Tr0 (the rising edge of the 0th cycle of the external clock signal EX_CK), the external chip selection signal EX_CS_n becomes low level. At the rising edge (time point Tr0) and falling edge (time point Tf0) of the 0th cycle of the external clock signal EX_CK, the external command address signal EX_C is sampled and read. <j>Sampling and reading are performed, that is, data A (at time Tr0 when the internal chip select signal CS_n_r0 becomes low) and data B (at time Tf0 when the internal chip select signal CS_n_r becomes low) are input into the memory chip 10. Then, the internal command address signal CA_r0 is sent during the valid period (Tr0 to Tr1) of the internal chip select signal CS_n_r0. <j>.

[0099] After that, under the activation of the internal rising edge clock signal CK_r (the rising edge of time point Tr0), the external command address signal EX_CA <j>Read data A, sample and read the internal command address signal CA_r0 <j>As mentioned above, under the action of latches FF1-FF2, the sampled internal command address signal CA_r0 is <j>Delay half a cycle to generate the internal rising edge command address signal CA_r at time point Tf0 <j>In addition, under the activation of the internal falling edge clock signal CK_f (falling edge at time point Tf0), the internal falling edge command address signal CA_f is generated at time point Tf0 through the above latch FF_3. <j>.

[0100] Afterwards, at time point Tr1, the internal rising edge address signal CA_r is sent out. <j>The internal falling edge command address signal CA_f <j>The encoded test command cmd_test and test addresses XAD_test<11:0> and YAD_test<8:0>. That is, as mentioned above, the internal rising edge command address signal CA_r <j>The internal falling edge command address signal CA_f <j>The encoded test command and test address are transmitted to the test command decoder 40 and the test address decoder 42 respectively.

[0101] Next, at time point Tr1, based on the test command cmd_test and the test addresses XAD_test<11:0> and YAD_test<8:0>, command signals (such as ACT, PRE, WRITE, READ, REF) and address signals (such as XAD<11:0> and YAD<8:0>) are generated. That is, as described above, the actual command and address obtained by decoding are transmitted to the memory cell array of the memory chip 20 through the test command decoder 40 and the test address decoder 42 for testing.

[0102] Regarding the normal operation of the memory chip 20 of the present invention, it can be any prior art architecture without affecting the implementation of the testing method of the present invention. Figure 6 A circuit diagram illustrating normal operation of a memory chip is shown.

[0103] like Figure 6 As shown, a plurality of metal terminals 12_1, 12_2, 12_3, 12_4 are disposed on the surface of the memory chip 20. The external clock signal EX_CK, the external address signal EX_A<11:0>, the external command signal (EX_RAS_n, EX_CAS_n, EX_WE_n) and the external chip selection signal EX_CS_n are respectively input to the corresponding terminal input buffers 50_1, 50_2, 50_3, 50_4 of the memory chip 20 via the metal terminals 12_1, 12_2, 12_3, 12_4. Here, the above-mentioned external command signal (EX_RAS_n, EX_CAS_n, EX_WE_n), the external chip selection signal EX_CS_n and the external address signal EX_A<11:0> can be regarded as the external operation signals of the memory chip 20 in the normal operation mode. In addition, in the normal operation, the logic chip 10 is stacked to the memory chip 20, so each external signal and address signal is transmitted from the logic chip 10.

[0104] According to an embodiment of the present invention, the test signal (such as the external chip selection signal EX_CS_n, EX_C <j>) is less than the number of external operation signals (such as external chip selection signal EX_CS_n, external command signal EX_RAS_n, EX_CAS_n, EX_WE_n and external address signal EX_A<11:0>) input to the memory chip 20 in the normal mode. <j>The number of the metal terminals 12_1 , 12_2 , 12_3 , and 12_4 used for normal operation will be less than that of the metal terminals 12_1 , 12_2 , 12_3 , and 12_4 used for normal operation.

[0105] Afterwards, the terminal input buffers 50_1, 50_3, 50_4 transmit the internal clock signal CK, the internal command signal (RAS_n, CAS_n, WE_n) and the internal chip select signal CS_n to the command decoder 60, thereby decoding the normal operation command, such as ACT_norm, PRE_norm, WRITE_norm, WE_norm, READ_norm, REF_norm. Similarly, the terminal input buffers 50_3, 50_4 transmit the internal clock signal CK and the internal address A<11:0> to the address decoder 62, thereby decoding the normal operation address XAS_norm<11:0>, YAD_norm<8:0>. Afterwards, the normal operation command ACT_norm, PRE_norm, WRITE_norm, READ_norm, REF_norm and the normal operation address XAD_norm<11:0>, YAD_norm<8:0> are transmitted to the command address selector 70.

[0106] When the test enable signal is at a high level, that is, the memory chip 20 is in a tested state, the command address selector 70 selects each test command ACT_test, PRE_test, WRITE_test, READ_test, REF_test and the test address XAD_test<11:0> and YAD_test<8:0> as the output command ACT, PRE, WRITE, READ, REF, and the output address XAD<11:0> and YAD<8:0>, and transmits them to the memory cell array in the memory chip 20 for testing. In addition, when the test enable signal is at a low level, that is, the memory chip 20 is in a normal operation state, the command address selector 70 selects each normal operation command ACT_norm, PRE_norm, WRITE_norm, READ_norm, REF_norm and the test address XAD_norm<11:0> and YAD_norm<8:0> as the output command ACT, PRE, WRITE, READ, REF, and the output address XAD<11:0> and YAD<11:0>, and transmits it to the memory cell array in the memory chip 20 for operation.

[0107] In the normal operation mode described above, if Figure 8 As shown in the timing diagram, at time point T0, the external command signals EX_RAS_n, EX_CAS_n, EX_WE_n and the external address EX_A<11:0> are sent out. After the external chip select signal EX_CS_n is sent out, the internal chip select signal CS_n is delayed by half a cycle and becomes low level. When the internal chip select signal CS_n becomes low level and remains low level until time point T1 (i.e., valid period), the internal commands RAS_n, CAS_n, WE_n and the internal address A<11:0> are sent out during this valid period. Afterwards, in the same time interval T0-T1, the commands ACT, PRE, WRITE, READ, REF and the addresses XAD<11:0> and YAD<8:0> are sent out.

[0108] In addition, compared with the normal operation mode of the memory chip 20, in the Figure 7 In the test state shown in the figure, when the external command address signal EX_CA is <j>After the read operation is performed, the test command cmd_test and the test addresses XAD_test<11:0> and YAD_test<8:0> generated subsequently are sent out after a delay of about one cycle (time point Tr1). However, when testing the memory chip 20, the effectiveness of the memory chip 20 is mainly tested, and the speed is not required like normal operation. Therefore, there is no impact if the test command cmd_test and the test addresses XAD_test<11:0> and YAD_test<8:0> are sent out after a delay of at least one cycle. On the contrary, the method of the present invention can effectively reduce the probe test pads 26_1, 26_2, and 26_3. <j>The number of memory chips 20 can be further reduced in size.

[0109] In summary, according to the embodiments of the present invention, when testing a memory chip, sampling and reading the input signal based on the rising and falling edges of the clock signal can effectively reduce the number of probe test pads, thereby further reducing the area of ​​the memory chip.< / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A memory chip test device, wherein the memory chip and a logic chip are face-to-face bonded to form a stacked memory, the test device comprising at least: A plurality of probe test pads are formed on the surface of the memory chip to receive an external clock signal and a plurality of test signals, wherein the plurality of test signals are sampled and read at the rising edge and the falling edge of the external clock signal; as well as A test command address generating unit is configured to decode the sampled test signals to generate a test command and a test address. The number of the plurality of test signals is smaller than the number of the plurality of external operation signals input to the memory chip in a normal mode.

2. The memory chip test device according to claim 1, wherein the test command address generating unit further comprises: A test command decoder, decoding the plurality of test signals sampled based on the rising edge of the external clock signal to generate the test command; as well as The test address decoder decodes the plurality of sampled test signals relative to the rising edge of the external clock signal to generate the test address.

3. The memory chip testing device according to claim 2, wherein the test command address generating unit further comprises: A command address selector, used to receive the test command and the test address for testing, and to receive the command and address for normal operation, When the command address selector receives a test enable signal to enable the test, the command address selector outputs the test command and the test address. When the command address selector receives the test enable signal to inhibit testing, the command address selector outputs the command and the address for normal operation. 4 . The memory chip testing device as claimed in claim 2 , wherein the plurality of test signals include an external chip selection signal and a plurality of external command address signals.

5. The memory chip testing device according to claim 4, wherein the test command address generating unit further comprises: The first, second, third, fourth and fifth latches, The first latch receives the plurality of external command address signals and latches the plurality of external command address signals at the rising edge of the external clock signal, and the second latch latches the output of the first latch at the falling edge of the external clock signal and outputs a plurality of internal rising edge command address signals. The third latch receives the plurality of external command address signals, latches the plurality of external command address signals at the falling edge of the external clock signal, and outputs a plurality of internal falling edge command address signals. The fourth latch receives the external chip selection signal and latches the external chip selection signal at the rising edge of the external clock signal, and the fifth latch latches the output of the fourth latch at the falling edge of the external clock signal and outputs an internal chip selection signal. wherein the plurality of internal rising edge command address signals, the plurality of internal falling edge command address signals and the internal chip selection signal are transmitted to the test command decoder, The plurality of internal rising edge command address signals and the plurality of internal falling edge command address signals are transmitted to the test address decoder. 6 . The memory chip testing device as claimed in claim 5 , wherein the first, the second, the third, the fourth and the fifth latches are edge-triggered flip-flops.

7. The memory chip testing device according to claim 1, wherein the time point at which the plurality of test signals are sampled and read differs from the time point at which the test command and the test address are generated by at least one cycle of the external clock signal.

8. The memory chip test device according to claim 1, wherein a plurality of first metal terminals are arranged on the surface of the memory chip, and a plurality of second metal terminals are arranged on the surface of the logic chip, and the arrangement positions of the plurality of first metal terminals correspond to the arrangement positions of the plurality of second metal terminals, and the logic chip and the memory chip are joined together by the plurality of first metal terminals and the second metal terminals being joined face to face with each other, In a normal operation mode, the external clock signal and the external operation signal are respectively transmitted to the memory chip via the plurality of first metal terminals. 9 . The memory chip testing device as claimed in claim 8 , wherein an area of ​​each of the plurality of probe test pads is larger than an area of ​​each of the plurality of first metal terminals.

10. The memory chip testing device as claimed in claim 1, wherein the memory chip is a DRAM memory chip.

11. A method for testing a memory chip, wherein the memory chip and a logic chip are bonded face to face to form a stacked memory, the method comprising at least: Receiving an external clock signal and a plurality of test signals by probing a plurality of test pads on a surface of the memory chip; At the rising edge and the falling edge of the external clock signal, respectively sampling and reading the multiple test signals; as well as Decoding the sampled test signals to generate test commands and test addresses, The number of the plurality of test signals is smaller than the number of the plurality of external operation signals input to the memory chip in a normal mode.

12. The memory chip testing method according to claim 11, further comprising: relative to the rising edge of the external clock signal, decoding the plurality of test signals based on the sampling to generate the test command; as well as Relative to the rising edge of the external clock signal, the plurality of test signals sampled are decoded to generate the test address.

13. The memory chip testing method according to claim 12, further comprising: Receiving the test command and the test address for testing, and receiving the command and address for normal operation; When the command address selector receives a test enable signal to enable the test, the command address selector outputs the test command and the test address; as well as When the command address selector receives the test enable signal to inhibit testing, the command address selector outputs the command and the address for normal operation. 14 . The memory chip testing method as claimed in claim 12 , wherein the plurality of test signals include an external chip selection signal and a plurality of external command address signals.

15. The memory chip testing method according to claim 14, further comprising: receiving the plurality of external command address signals, latching the plurality of external command address signals at the rising edge of the external clock signal, latching the plurality of latched external command address signals at the falling edge of the external clock signal and outputting a plurality of internal rising edge command address signals; receiving the plurality of external command address signals, latching the plurality of external command address signals at the falling edge of the external clock signal to output a plurality of internal falling edge command address signals; receiving the external chip selection signal, latching the external chip selection signal at the rising edge of the external clock signal, latching the latched external chip selection signal at the falling edge of the external clock signal, and outputting an internal chip selection signal; Decoding based on the multiple internal rising edge command address signals, the multiple internal falling edge command address signals and the internal chip selection signal to output the test command; as well as Decoding is performed based on the multiple internal rising edge command address signals and the multiple internal falling edge command address signals to output the test address. 16 . The memory chip testing method according to claim 11 , wherein the time point when the plurality of test signals are sampled and read differs from the time point when the test command and the test address are generated by at least one cycle of the external clock signal.

17. The memory chip testing method according to claim 11, wherein the memory chip is a DRAM memory chip.

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