Frequency control type wide-range variable quiescent current source and CT-sigma delta modulator

Abstract

The invention discloses a frequency control type wide-range variable quiescent current source and a CT-sigma delta modulator, the frequency control type wide-range variable quiescent current source comprises a frequency control type bias generation circuit and a current mirror circuit, the frequency control type bias generation circuit comprises at least one capacitor bias diode circuit, and the current mirror circuit comprises at least one capacitor bias diode circuit. The bias circuit is used for generating bias voltage. The current mirror circuit is used for copying current flowing through a diode load in the capacitor bias diode circuit according to the bias voltage, and the current linearly changes along with the clock frequency. The frequency control type wide-range variable quiescent current source is simple in circuit, the scaling range of the generated variable quiescent current is large, control is easy and convenient, linear scaling of the CT-sigma delta modulator system power consumption along with the sampling frequency is achieved, and the high energy efficiency of the system under different sampling frequencies is guaranteed.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog circuits, and in particular relates to a frequency-controlled wide-range variable static current source and a CT-ΣΔ modulator. Background Art

[0002] IoT applications require a large number of sensor chips, and these chips are required to achieve high energy efficiency under different input signal bandwidths. Therefore, it is hoped that a variable current that scales with the signal bandwidth can be provided for analog modules. It is known that dynamic circuits can achieve a large range of current scaling with clock frequency, but they cannot be applied to static circuits. A single traditional static current source can only provide a single fixed static current. A current source array composed of a control word can provide a variable static current, but the current scaling range is small and the control is complex, and it is impossible to provide a variable static current in a wide range. How to provide a variable bias current that scales with the signal bandwidth for static circuits has become a challenge. Summary of the invention

[0003] Purpose of the invention: The technical problem to be solved by the present invention is to provide a frequency-controlled wide-range variable static current source and a CT-ΣΔ modulator in view of the deficiencies in the prior art.

[0004] In order to solve the above technical problems, in the first aspect, a frequency-controlled wide-range variable static current source is disclosed, including a frequency-controlled bias generating circuit and a current mirror circuit, wherein the frequency-controlled bias generating circuit includes at least one capacitor bias diode circuit for generating a bias voltage; the current mirror circuit is used to replicate the current flowing through the diode load in the capacitor bias diode circuit according to the bias voltage, and the current changes linearly with the clock frequency.

[0005] Furthermore, the capacitor biased diode circuit includes a capacitor, a diode load, a first switch and a third switch, the diode load includes a first transistor and a second switch, the two ends of the second switch are respectively connected to the gate and drain of the first transistor; one end of the first switch is connected to the gate of the first transistor, and when the first switch is closed, the gate-source voltage of the first transistor is 0, and the drain of the first transistor is also connected to one end of the capacitor; one end of the third switch is connected to the pre-charge voltage, and the other end is connected to one end of the capacitor, and the other end of the capacitor is grounded.

[0006] Furthermore, the current mirror circuit includes a fourth switch and a second transistor, and a connection point between the third switch and the capacitor is connected to one end of the fourth switch; and the other end of the fourth switch is connected to the gate of the second transistor.

[0007] Further, when the frequency-controlled bias generating circuit includes a capacitor bias diode circuit, the clock control timing sequence includes a pre-charging stage RST, a discharging stage CBD and a mirror stage CTRL, and when RST is at a high level in the pre-charging stage, the first switch and the third switch are closed, the second switch and the fourth switch are opened, the capacitor is pre-charged, and the first transistor is turned off;

[0008] In the pre-charging stage, when RST is at a low level, the first switch and the third switch are disconnected. In the discharging stage, CBD is at a high level, the second switch is closed, and the capacitor is discharged through the first transistor connected by the diode. The residual voltage V D When the residual voltage V D After reaching the preset bias voltage value, CBD is at a low level in the discharge phase, the second switch is disconnected, and the discharge ends; then, CTRL is at a high level in the mirror phase, the fourth switch is closed, and the residual voltage V D The second transistor is biased to generate a current I D , that is, the second transistor copies the current I flowing through the first transistor D .

[0009] Further, when the frequency-controlled bias generating circuit includes two identical capacitor bias diode circuits: a first capacitor bias diode circuit and a second capacitor bias diode circuit, the clock control timing includes a first pre-charging stage RST1, a first discharging stage CBD1, a first mirror stage CTRL1, a second pre-charging stage RST2, a second discharging stage CBD2, and a second mirror stage CTRL2. First, in the first pre-charging stage RST1 is at a high level, the first switch and the third switch of the first capacitor bias diode circuit are closed, the capacitor is pre-charged, and the first transistor is turned off; subsequently, in the first pre-charging stage RST1 is pulled low, in the first discharging stage CBD1 is pulled high, the first switch and the third switch are disconnected, the second switch is closed, the capacitor and the first transistor connected to the diode together form a discharge path, and the residual voltage V on the capacitor D Starts to change when V D After reaching the preset bias voltage value, CBD1 is pulled low in the first discharge stage, and the discharge ends. D The value is maintained, and then the first mirror stage CTRL1 is pulled high, and the fourth switch is closed, so that the residual voltage V D The second transistor is biased to generate a current I D ;

[0010] At the same time, in the high level phase of CTRL1 in the first mirror stage, the second capacitor biased diode circuit repeats the above operation, that is, in the second pre-charging stage, RST2 is high level, the first switch and the third switch of the second capacitor biased diode circuit are closed, the capacitor is pre-charged, and the first transistor is cut off; subsequently, in the second pre-charging stage, RST2 is pulled low, in the second discharging stage, CBD2 is pulled high, the first switch and the third switch are disconnected, the second switch is closed, and the capacitor and the first transistor connected to the diode together form a discharge path, and the residual voltage V on the capacitor D Starts to change when V D After reaching the preset bias voltage value, the second discharge stage CBD2 is pulled low, the discharge ends, and the residual voltage V D The value is maintained, and then the second mirror stage CTRL2 is pulled high, and the fourth switch is closed, so that the residual voltage V D The second transistor is biased to generate a current I D .

[0011] The frequency-controlled bias generation circuit includes two identical capacitor bias diode circuits, so that the frequency-controlled wide-range variable static current source operates in a ping-pong mode. In practice, due to non-ideal factors in the circuit, the residual charge on Cs will leak and cause V D drift, so it is necessary to D To ensure that the current I D The size is constant, that is, keep I D The static characteristics under a certain frequency, so the ping-pong working mode can be adopted.

[0012] Furthermore, the discharge duration of the first discharge stage CBD1 is inversely proportional to the clock frequency.

[0013] Furthermore, the current mirror circuit also includes a third transistor, and the second transistor and the third transistor form a common source and common gate structure, and the current stability thereof is further improved by adding a cascode transistor.

[0014] Furthermore, the first transistor and the second transistor are both PMOS transistors.

[0015] Furthermore, the first transistor and the second transistor are both NMOS transistors.

[0016] In the second aspect, a CT-ΣΔ (Continuous-Time Sigma-Delta) modulator is disclosed. The modulator is built based on a GmC open-loop integrator, and the bias current of Gm is provided by the frequency-controlled wide-range variable static current source. The bias current changes linearly with the sampling frequency of the modulator.

[0017] Beneficial effects: The present invention proposes a frequency-controlled current source (FCCS) that uses a simple circuit to generate a variable static current with a large scaling range and easy control. Specifically:

[0018] 1) Since the FCCS circuit is very simple, the implementation of variable quiescent current is also simple and intuitive.

[0019] 2) Since the current I can be controlled by adjusting the discharge time D size, so the current scaling control is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0021] Figure 1 CBD circuit (left) and V D Simulation curves over time.

[0022] Figure 2 FCCS circuit topology and timing diagram.

[0023] Figure 3 Circuit topology and timing diagram of FCCS in ping-pong working mode.

[0024] Figure 4 I D Simulation curve with changing clock frequency fs.

[0025] Figure 5 cascode FCCS circuit topology and timing diagram.

[0026] Figure 6 Circuit topology and timing diagram of cascode FCCS in ping-pong working mode.

[0027] Figure 7 GmC-based continuous-time delta sigma modulator system architecture and timing.

[0028] Figure 8 The power consumption curve obtained from the test varies with fs.

[0029] Fig. 9 The curve of FoM changing with fs obtained from the test. DETAILED DESCRIPTION

[0030] The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0031] The CBD (Capacitively-Biased Diode) circuit consists of a diode, a capacitor, and a switch. Figure 1 (Left) As shown, it is used in the sensor circuit to generate a DC voltage V D The working principle of this circuit is: the capacitor Cs is first precharged to an initial potential, and then discharged through the diode. After a short build-up time, the residual voltage V on Cs D It satisfies a logarithmic relationship with the discharge time t and has nothing to do with the initial potential, such as Figure 1 (right) As shown. At the same time, the current I flowing through the diode D ∝V T Cs / t, where V T is the thermal voltage (V T =kT / q), T represents the current temperature, k represents the Boltzmann constant, and q represents the charge constant.

[0032] The first embodiment of the present application discloses a frequency-controlled wide-range variable static current source, comprising a frequency-controlled bias generating circuit and a current mirror circuit, wherein the frequency-controlled bias generating circuit comprises at least one capacitor biasing diode circuit for generating a bias voltage V D The current mirror circuit is used to adjust the bias voltage V D Replicate the current I flowing through the diode load in the capacitor biased diode circuit D , the current I D Changes linearly with the clock frequency fs.

[0033] The capacitor biased diode circuit includes a capacitor Cs, a diode load, a first switch S1 and a third switch S3. The diode load includes a first transistor M D and a second switch S2, wherein both ends of the second switch S2 are connected to the first transistor M D One end of the first switch S1 is connected to the first transistor M D When the first switch S1 is closed, the first transistor M D The gate-source voltage of the first transistor M is 0. D The drain of the third switch S3 is also connected to one end of the capacitor Cs; one end of the third switch S3 is connected to the pre-charge voltage, and the other end is connected to one end of the capacitor Cs, and the other end of the capacitor Cs is grounded.

[0034] The current mirror circuit includes a fourth switch S4 and a second transistor Mc. The connection point between the third switch S3 and the capacitor Cs is connected to one end of the fourth switch S4. The other end of the fourth switch S4 is connected to the gate of the second transistor Mc.

[0035] When the frequency-controlled bias generating circuit includes a capacitor bias diode circuit, the clock control timing sequence includes a pre-charging stage RST, a discharging stage CBD and a mirror stage CTRL. When RST is at a high level in the pre-charging stage, the first switch S1 and the third switch S3 are closed, the second switch S2 and the fourth switch S4 are opened, the capacitor Cs is pre-charged, and the first transistor M D Cut-off;

[0036] In the pre-charging stage, when RST is at a low level, the first switch S1 and the third switch S3 are disconnected. In the discharging stage, CBD is at a high level, the second switch S2 is closed, and the capacitor Cs is connected to the first transistor M through the diode. D Discharge is performed, and the residual voltage V on the capacitor Cs D When the residual voltage V on the capacitor Cs starts to change D After reaching the preset bias voltage value, the discharge phase CBD is at a low level, the second switch S2 is disconnected, and the discharge ends; then, the mirror phase CTRL is at a high level, the fourth switch S4 is closed, and the residual voltage V D The second transistor Mc is biased to generate a current I D .

[0037] When the frequency-controlled bias generating circuit includes two identical capacitor bias diode circuits: a first capacitor bias diode circuit and a second capacitor bias diode circuit, the clock control timing sequence includes a first pre-charging stage RST1, a first discharging stage CBD1, a first mirror stage CTRL1, a second pre-charging stage RST2, a second discharging stage CBD2, and a second mirror stage CTRL2. First, in the first pre-charging stage RST1 is at a high level, the first switch S1 and the third switch S3 of the first capacitor bias diode circuit are closed, the capacitor Cs is pre-charged, and the first transistor M D Subsequently, in the first pre-charging stage, RST1 is pulled low, in the first discharging stage, CBD1 is pulled high, the first switch S1 and the third switch S3 are disconnected, the second switch S2 is closed, and the capacitor Cs and the diode are connected to the first transistor M D Together they form a discharge path, and the residual voltage V on the capacitor Cs D Starts to change when V D After reaching the preset bias voltage value, CBD1 is pulled low in the first discharge stage, and the discharge ends. D The value is maintained, and then the first mirror stage CTRL1 is pulled high, and the fourth switch S4 is closed, so that the residual voltage V D The second transistor Mc is biased to generate a current I D ;

[0038] At the same time, in the high level phase of the first mirror stage CTRL1, the second capacitor bias diode circuit repeats the above operation, that is, in the second pre-charging stage RST2 is high level, and the first switch S of the second capacitor bias diode circuit 1’ and the third switch S 3’ Closed, capacitor Cs' is pre-charged, the first transistor M D’ Then, in the second pre-charge phase, RST2 is pulled low, and in the second discharge phase, CBD2 is pulled high, and the first switch S 1’ and the third switch S 3’ Disconnect, the second switch S 2’ Closed, capacitor Cs' and diode connected first transistor M D’ Together they form a discharge path, and the residual voltage V on the capacitor Cs' D’ Starts to change when V D’ After reaching the preset bias voltage value, the second discharge stage CBD2 is pulled low, the discharge ends, and the residual voltage V D’ The value is maintained, and then the second mirror stage CTRL2 is pulled high, and the fourth switch S 4’ Close, so that the residual voltage V D’ The second transistor Mc' is biased to generate a current I D .

[0039] The discharge durations of the first discharge phase CBD1 and the second discharge phase CBD2 are equal and are both inversely proportional to the clock frequency fs.

[0040] The current mirror circuit further includes a third transistor M CC , the second transistor Mc and the third transistor M CC Form a common source and common gate structure.

[0041] In an optional implementation, the first transistor M D The second transistor Mc is a PMOS transistor.

[0042] In another optional implementation, the first transistor M D The second transistor Mc is an NMOS transistor.

[0043] Figure 2 There are two forms of FCCS circuit topology diagrams. The first transistor M on the left D The first switch S1 and the second transistor Mc are both PMOS tubes. The other end of the first switch S1 is connected to the power supply voltage V DD , the first transistor M D The source stage is connected to the power supply voltage V DD , so that when the first switch S1 is closed, the first transistor M D The gate-source voltage is 0; one end of the third switch S3 is connected to the precharge voltage VSS , the source of the second transistor Mc is connected to the input voltage V DD ; The first transistor M on the right D The first switch S1 and the second transistor Mc are both NMOS tubes. The other end of the first switch S1 is connected to the ground voltage V SS , the first transistor M D The source voltage V SS , so that when the first switch S1 is closed, the first transistor M D The gate-source voltage is 0; one end of the third switch S3 is connected to the precharge voltage V DD , the source of the second transistor Mc is grounded. The clock control timing includes a pre-charging stage RST, a discharging stage CBD and a mirror stage CTRL. In the pre-charging stage, when RST is at a high level, the first switch S1 and the third switch S3 are closed, and the capacitor Cs is pre-charged; in the pre-charging stage, when RST is at a low level, and in the discharging stage, when CBD is at a high level, the first switch S1 and the third switch S3 are disconnected, the second switch S2 is closed, and the capacitor Cs is connected to the first transistor M through a diode. D The tube is discharged, and the discharge time is controlled by the sampling frequency to 1 / fs, thereby obtaining the residual voltage V D , that is, the bias voltage, when the residual voltage V on the capacitor D After reaching the preset bias voltage value, CBD is at a low level in the discharge phase, the second switch S2 is disconnected, and the discharge ends; subsequently, CTRL is at a high level in the mirror phase, the fourth switch S4 is closed, and the second transistor Mc tube acts as a current mirror tube to copy the current I D . Because I D ∝V T Cs / t(V T = kT / q), so I D Proportional to the clock frequency fs, the FCCS circuit can obtain a linearly changing variable current I by controlling the clock frequency fs. D .

[0044] In fact, due to non-ideal factors in the circuit, the residual charge on Cs will leak and cause V D drift, so it is necessary to D To refresh, and to keep I D The static characteristics of the FCCS circuit can work in the ping-pong mode, that is, the frequency-controlled bias generating circuit includes a first capacitor bias diode circuit and a second capacitor bias diode circuit, such as Figure 3 As shown, by adding a group of identical CBD circuits, ping-pong timing control can be adopted.

[0045] from Figure 4 It can be seen that as the clock frequency fs changes, the current I DA wide range of linear scaling is achieved.

[0046] The FCCS circuit can also be realized by adding a cascode transistor M CC , further improve its current stability, such as Figure 5 shown.

[0047] Similarly, the cascode FCCS circuit can also work in ping-pong mode, such as Figure 6 shown.

[0048] The second embodiment of the present application discloses a CT-ΣΔ modulator, which is built based on a GmC open-loop integrator. The bias current of Gm is provided by the frequency-controlled wide-range variable static current source, and the bias current changes linearly with the sampling frequency fs of the modulator.

[0049] like Figure 7 As shown, the modulator is built based on the GmC open-loop integrator, and the bias current of Gm is provided by the FCCS working in the ping-pong working mode.

[0050] Thanks to the scalable current provided by FCCS, the test results show that the system power consumption of the modulator achieves linear scaling with the sampling frequency fs ( Figure 8 ), ensuring high energy efficiency of the system at different fs ( Fig. 9 Energy efficiency is measured by the FoM (Figure of merit) value, FoM = SNDR + 10log (Bandwidth / Power)).

[0051] The present invention provides a frequency-controlled wide-range variable static current source and a CT-ΣΔ modulator. There are many methods and ways to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A frequency-controlled wide-range variable static current source, characterized in that: It includes a frequency-controlled bias generating circuit and a current mirror circuit, wherein the frequency-controlled bias generating circuit includes at least one capacitor bias diode circuit for generating a bias voltage; The current mirror circuit is used to replicate the current flowing through the diode load in the capacitor biased diode circuit according to the bias voltage, and the current changes linearly with the clock frequency.

2. A frequency-controlled wide-range variable static current source according to claim 1, characterized in that: The capacitor biased diode circuit includes a capacitor, a diode load, a first switch and a third switch. The diode load includes a first transistor and a second switch. The two ends of the second switch are respectively connected to the gate and the drain of the first transistor; one end of the first switch is connected to the gate of the first transistor. When the first switch is closed, the gate-source voltage of the first transistor is 0, and the drain of the first transistor is also connected to one end of the capacitor; one end of the third switch is connected to the pre-charge voltage, and the other end is connected to one end of the capacitor, and the other end of the capacitor is grounded.

3. A frequency-controlled wide-range variable static current source according to claim 2, characterized in that: The current mirror circuit includes a fourth switch and a second transistor. The connection point between the third switch and the capacitor is connected to one end of the fourth switch; and the other end of the fourth switch is connected to the gate of the second transistor.

4. A frequency-controlled wide-range variable static current source according to claim 3, characterized in that: When the frequency-controlled bias generating circuit includes a capacitor biasing diode circuit, the clock control timing sequence includes a pre-charging stage RST, a discharging stage CBD and a mirroring stage CTRL. When RST is at a high level in the pre-charging stage, the first switch and the third switch are closed, the second switch and the fourth switch are opened, the capacitor is pre-charged, and the first transistor is turned off. In the pre-charging stage, when RST is at a low level, the first switch and the third switch are disconnected. In the discharging stage, CBD is at a high level, the second switch is closed, and the capacitor is discharged through the first transistor connected by the diode. The residual voltage V D When the residual voltage V D After reaching the preset bias voltage value, CBD is at a low level in the discharge phase, the second switch is disconnected, and the discharge ends; Then, in the mirror phase, CTRL is high and the fourth switch is closed, so that the residual voltage V D The second transistor is biased to generate a current I D .

5. A frequency-controlled wide-range variable static current source according to claim 3, characterized in that: When the frequency-controlled bias generating circuit includes two identical capacitor bias diode circuits: a first capacitor bias diode circuit and a second capacitor bias diode circuit, the clock control timing sequence includes a first pre-charging stage RST1, a first discharging stage CBD1, a first mirror stage CTRL1, a second pre-charging stage RST2, a second discharging stage CBD2, and a second mirror stage CTRL2. First, in the first pre-charging stage RST1 is at a high level, the first switch and the third switch of the first capacitor bias diode circuit are closed, the capacitor is pre-charged, and the first transistor is turned off; subsequently, in the first pre-charging stage RST1 is pulled low, in the first discharging stage CBD1 is pulled high, the first switch and the third switch are disconnected, the second switch is closed, the capacitor and the first transistor connected to the diode together form a discharge path, and the residual voltage V on the capacitor D Starts to change when V D After reaching the preset bias voltage value, CBD1 is pulled low in the first discharge stage, and the discharge ends. D The value is maintained, and then the first mirror stage CTRL1 is pulled high, and the fourth switch is closed, so that the residual voltage V D The second transistor is biased to generate a current I D ; At the same time, in the high level phase of the first mirror stage CTRL1, the second capacitor biased diode circuit repeats the above sequence.

6. A frequency-controlled wide-range variable static current source according to claim 4 or 5, characterized in that: The discharge duration of the first discharge phase CBD1 is inversely proportional to the clock frequency.

7. A frequency-controlled wide-range variable static current source according to claim 6, characterized in that: The current mirror circuit further includes a third transistor, and the second transistor and the third transistor form a common source and common gate structure.

8. A frequency-controlled wide-range variable static current source according to claim 6, characterized in that: The first transistor and the second transistor are both PMOS transistors.

9. A frequency-controlled wide-range variable static current source according to claim 6, characterized in that: The first transistor and the second transistor are both NMOS transistors.

10. A CT-ΣΔ modulator, characterized in that: The modulator is constructed based on a GmC open-loop integrator, and the bias current of Gm is provided by a frequency-controlled wide-range variable static current source as described in any one of claims 1-9.

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