Preparation method of low-indium heterojunction battery

Abstract

The invention discloses a preparation method of a low-indium heterojunction battery, and the method comprises the following steps: providing a substrate, and forming double-sided pyramid suede surfaces on the upper surface and the back surface of the substrate; respectively forming a first intrinsic passivation layer and a second intrinsic passivation layer on the upper surface and the back surface of the substrate; forming an N-type doped silicon layer or an N-type doped silicon oxide layer on the upper surface of the first intrinsic passivation layer, and forming a P-type doped silicon layer or a P-type doped silicon oxide layer on the back surface of the second intrinsic passivation layer; tCO composite films are formed on the upper surface doped silicon layer and the back surface doped silicon layer; performing hydrogen plasma treatment on the plated TCO composite film; and a front metal patterned electrode and a back metal patterned electrode are respectively formed on the second sub TCO films on the upper surface and the back surface. By adopting the composite structure of the low-pressure deposition indium base and the high-pressure deposition indium-free film, the total indium usage amount of the heterojunction cell is effectively reduced while the photoelectric characteristic is ensured not to be lost, and the cell cost is greatly saved.

Description

Technical Field

[0001] The present invention relates to the technical field of heterojunction batteries, and in particular to a method for preparing a low-indium heterojunction battery. Background Art

[0002] The existing heterojunction cell includes an N-type monocrystalline silicon wafer, and a pyramid velvet surface, an intrinsic passivation layer, an N-type doped silicon layer, a transparent conductive layer (TCO), and a metal grid line are sequentially arranged on the upper surface of the silicon wafer. A pyramid velvet surface, an intrinsic passivation layer, a P-type doped silicon layer, a transparent conductive layer (TCO), and a metal grid line are sequentially arranged on the back of the silicon wafer.

[0003] Among them, In2O3-based transparent conductive oxides with good photoelectric properties are often used as transparent conductive layers and anti-reflection layers to provide current transmission and improve photoelectric conversion efficiency. However, indium resources are scarce and expensive. The cost of indium-based TCO films accounts for about 15% or even more of the non-silicon cost of HJT. Although indium-free TCO films have lower costs, their photoelectric properties are often lost compared to indium-based TCO films. Therefore, finding alternative materials or methods to reduce the indium content has become the focus of current research. Summary of the invention

[0004] In view of the above problems, the present invention provides a method for preparing a low-indium heterojunction battery, which ensures that the photoelectric characteristics are not lost while effectively reducing the overall indium usage of the heterojunction battery, thereby greatly saving the battery cost.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a method for preparing a low-indium heterojunction battery, the method comprising the following steps:

[0006] Providing a substrate, and using an alkaline solution and an additive to form a double-sided pyramid velvet surface on the upper surface and the back surface of the substrate;

[0007] forming a first intrinsic passivation layer and a second intrinsic passivation layer on the upper surface and the back surface of the substrate respectively;

[0008] forming an N-type doped silicon layer or an N-type doped silicon oxide layer on the upper surface of the first intrinsic passivation layer, and forming a P-type doped silicon layer or a P-type doped silicon oxide layer on the back surface of the second intrinsic passivation layer;

[0009] A TCO composite film is formed on the upper surface and the back doped silicon layer by a PVD or RPD method, wherein the TCO composite film is divided into a first sub-TCO film and a second sub-TCO film, and is deposited in separate chambers;

[0010] The plated TCO composite film is subjected to hydrogen plasma treatment;

[0011] A front metal patterned electrode and a back metal patterned electrode are respectively formed on the upper surface and the back surface of the second sub-TCO film by screen printing or copper electroplating.

[0012] According to the method for preparing a low-indium heterojunction battery according to claim 1, it is characterized in that the first passivation layer and the second passivation layer are intrinsic amorphous silicon, and the thickness range is 3nm-10nm.

[0013] Furthermore, the thickness of the N-type doped silicon layer or the N-type doped silicon oxide layer is 5nm-25nm, and the thickness of the P-type doped silicon layer or the P-type doped silicon oxide layer is 10nm-35nm.

[0014] Furthermore, the first sub-TCO film is an indium oxide system TCO film deposited at low pressure, which is in contact with the doped silicon layer. The first sub-TCO film is deposited in a first deposition chamber, the deposition gas pressure is between 0.2Pa and 0.8Pa, the oxygen-argon flow ratio is between 2.0% and 5.0%, the hydrogen-argon flow ratio is between 0% and 3.5%, and the deposition thickness is 40nm-60nm.

[0015] Furthermore, the first sub-TCO film is subjected to vacuum annealing treatment, and the chamber pressure is 5×10-2 Pa-5×10-3 Pa. The annealing temperature is 180° C., and the annealing time is 30 min.

[0016] Furthermore, the second sub-TCO film is a TCO film of a tin oxide or zinc oxide system deposited under high pressure, which contacts the metal gate line. The second sub-TCO film is deposited in a second deposition chamber, the deposition gas pressure is between 0.9Pa and 1.2Pa, the oxygen-argon flow ratio is between 2.0% and 5.0%, and the deposition thickness is 40nm-60nm.

[0017] Furthermore, the optimal deposition temperatures of the first sub-TCO film and the second sub-TCO film are both 90° C.-250° C.

[0018] Furthermore, the total thickness of the composite TCO film is 90 nm-110 nm, and the thickness of the first sub-TCO film is greater than or equal to that of the second sub-TCO film.

[0019] Furthermore, the hydrogen plasma treatment of the plated TCO composite film adopts the PECVD method to perform plasma treatment, introducing hydrogen to make it glow discharge. The radio frequency power is 200W-1500W, the plasma treatment temperature is 80℃-160℃, and the treatment time is 5min-15min.

[0020] It can be seen from the above description of the present invention that, compared with the prior art, the present invention has the following advantages:

[0021] The TCO composite film in the low-indium heterojunction battery of the present invention adopts a composite structure of low-pressure deposition of indium-based and high-pressure deposition of indium-free thin film. The first sub-TCO film and the second sub-TCO film are thin films of different material systems, and the appropriate preparation deposition pressures are different. When the first sub-TCO film is prepared at a higher gas pressure, the surface roughness is too high, the grain size is reduced, and oxygen is more easily adsorbed in the grains on the surface of the film, which reduces the carrier concentration and mobility, resulting in an increase in resistivity. The second sub-TCO film is prepared under higher gas pressure conditions, the film has a larger grain size, fewer grain boundaries and defects, higher transmittance, and better photoelectric performance, which significantly reduces the indium content in the TCO film. While avoiding almost no loss of the photoelectric properties of the TCO film layer, it greatly reduces the cost and alleviates the problem of tight indium resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0023] Figure 1 The present invention is a process flow chart of a method for preparing a low-indium heterojunction battery;

[0024] Figure 2 This is a schematic diagram of the cross-sectional structure of a low-indium heterojunction battery prepared in the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0026] refer to Figure 1 , a method for preparing a low-indium heterojunction battery, the method comprising the following steps:

[0027] Providing a substrate, and using an alkaline solution and an additive to form a double-sided pyramid velvet surface on the upper surface and the back surface of the substrate;

[0028] forming a first intrinsic passivation layer and a second intrinsic passivation layer on the upper surface and the back surface of the substrate respectively;

[0029] forming an N-type doped silicon layer or an N-type doped silicon oxide layer on the upper surface of the first intrinsic passivation layer, and forming a P-type doped silicon layer or a P-type doped silicon oxide layer on the back surface of the second intrinsic passivation layer;

[0030] A TCO composite film is formed on the upper surface and the back doped silicon layer by a PVD or RPD method, wherein the TCO composite film is divided into a first sub-TCO film and a second sub-TCO film, and is deposited in separate chambers;

[0031] The plated TCO composite film is subjected to hydrogen plasma treatment;

[0032] A front metal patterned electrode and a back metal patterned electrode are respectively formed on the upper surface and the back surface of the second sub-TCO film by screen printing or copper electroplating.

[0033] like Figure 2 As shown, the low-indium heterojunction battery prepared by the present invention includes an N-type single crystal silicon wafer 1, an intrinsic amorphous silicon film 2, a doped amorphous silicon film 3, a first sub-TCO film 4, a second sub-TCO film 5 and a metal gate line 6 arranged in sequence on the upper surface and the back side of the N-type single crystal silicon wafer 1.

[0034] Example 1

[0035] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0036] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0037] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0038] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0039] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0040] The TCO composite film is deposited by magnetron sputtering PVD equipment in separate chambers to deposit ITO and SnOX. The first deposition chamber deposits the first sub-TCO film, the deposition pressure is maintained within 0.35Pa-0.45Pa, the target speed is 5r / min, the oxygen-argon flow ratio is 3.0%, and the deposition thickness is 50nm. The second deposition chamber deposits the second sub-TCO film, the deposition pressure is maintained at 0.9Pa-1.0Pa, the oxygen-argon flow ratio is 2.5%, and the deposition thickness is 50nm.

[0041] Silver gate electrodes are printed on the surface of the TCO composite film.

[0042] Example 2

[0043] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0044] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0045] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0046] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0047] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0048] The TCO composite film is deposited by magnetron sputtering PVD equipment in separate chambers to deposit ITO and SnOX. The first deposition chamber deposits the first sub-TCO film, the deposition pressure is maintained within 0.35Pa-0.45Pa, the target speed is 5r / min, the oxygen-argon flow ratio is 3.0%, and the deposition thickness is 50nm. The first sub-TCO film is vacuum annealed at 180°C for 30 minutes. The second deposition chamber deposits the second sub-TCO film, the deposition pressure is maintained at 0.9Pa-1.0Pa, the oxygen-argon flow ratio is 2.5%, and the deposition thickness is 50nm.

[0049] Silver gate electrodes are printed on the surface of the TCO composite film.

[0050] Example 3

[0051] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0052] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0053] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0054] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0055] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0056] The TCO composite film is deposited with ITO and SnOX in separate chambers using a magnetron sputtering PVD device. The first deposition chamber deposits the first sub-TCO film, the deposition pressure is maintained within 0.35Pa-0.45Pa, the target speed is 5r / min, the oxygen-argon flow ratio is 3.0%, and the deposition thickness is 50nm. The second deposition chamber deposits the second sub-TCO film, the deposition pressure is maintained at 0.9Pa-1.0Pa, the oxygen-argon flow ratio is 2.5%, and the deposition thickness is 50nm. The TCO composite film is treated with hydrogen plasma using PECVD equipment, the treatment temperature is 160°C, the treatment time is 15min, and the RF power is 300W.

[0057] Silver gate electrodes are printed on the surface of the TCO composite film.

[0058] Example 4

[0059] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0060] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0061] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0062] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0063] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0064] The TCO composite film is deposited with ITO and SnOX in separate chambers using a magnetron sputtering PVD device. The first sub-TCO film is deposited in the first deposition chamber, the deposition pressure is maintained within 0.35Pa-0.45Pa, the target rotation speed is 5r / min, the oxygen-argon flow ratio is 3.0%, and the deposition thickness is 50nm. The first sub-TCO film is vacuum annealed at 180°C for 30 minutes. The second sub-TCO film is deposited in the second deposition chamber, the deposition pressure is maintained at 0.9Pa-1.0Pa, the oxygen-argon flow ratio is 2.5%, and the deposition thickness is 50nm. The TCO composite film is treated with hydrogen plasma using PECVD equipment, the treatment temperature is 160°C, the treatment time is 15 minutes, and the RF power is 300W.

[0065] Silver gate electrodes are printed on the surface of the TCO composite film.

[0066] Example 5

[0067] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0068] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0069] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0070] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0071] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0072] The TCO composite film is deposited by magnetron sputtering PVD equipment in separate chambers to deposit ITO and SnOX. The first deposition chamber deposits the first sub-TCO film, the deposition pressure is maintained within 0.35Pa-0.45Pa, the target speed is 5r / min, the oxygen-argon flow ratio is 3.0%, and the deposition thickness is 50nm. The second deposition chamber deposits the second sub-TCO film, the deposition pressure is maintained at 0.35Pa-0.45Pa, the oxygen-argon flow ratio is 2.5%, and the deposition thickness is 50nm.

[0073] Silver gate electrodes are printed on the surface of the TCO composite film.

[0074] Example 6

[0075] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0076] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0077] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0078] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0079] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0080] The TCO composite film is deposited with ITO and SnOX in separate chambers using a magnetron sputtering PVD device. The first sub-TCO film is deposited in the first deposition chamber, the deposition pressure is maintained within 0.35Pa-0.45Pa, the target rotation speed is 5r / min, the oxygen-argon flow ratio is 3.0%, and the deposition thickness is 50nm. The first sub-TCO film is vacuum annealed at 180°C for 30 minutes. The second sub-TCO film is deposited in the second deposition chamber, the deposition pressure is maintained at 0.35Pa-0.45Pa, the oxygen-argon flow ratio is 2.5%, and the deposition thickness is 50nm. The TCO composite film is treated with hydrogen plasma using PECVD equipment, the treatment temperature is 160°C, the treatment time is 15 minutes, and the RF power is 300W.

[0081] Silver gate electrodes are printed on the surface of the TCO composite film.

[0082] Example 7

[0083] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0084] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0085] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0086] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0087] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0088] The TCO composite film is deposited with ITO and SnOX in separate chambers using a magnetron sputtering PVD device. The first deposition chamber deposits the first sub-TCO film, the deposition pressure is maintained within 0.35Pa-0.45Pa, the target rotation speed is 5r / min, the oxygen-argon flow ratio is 3.0%, and the deposition thickness is 50nm. The second deposition chamber deposits the second sub-TCO film, the deposition pressure is maintained at 0.9Pa-1.0Pa, the oxygen-argon flow ratio is 2.5%, and the deposition thickness is 50nm. The TCO composite film is vacuum annealed at 180°C for 30 minutes. After annealing, the TCO composite film is treated with hydrogen plasma using PECVD equipment, the treatment temperature is 160°C, the treatment time is 15 minutes, and the RF power is 300W.

[0089] Silver gate electrodes are printed on the surface of the TCO composite film.

[0090] Comparative Example 1

[0091] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0092] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0093] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0094] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0095] ITO was deposited on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer by magnetron sputtering PVD. The deposition pressure was kept within 0.35Pa-0.45Pa, the target speed was 5r / min, the oxygen-argon flow ratio was 3.0%, and the deposition thickness was 100nm.

[0096] Silver gate electrodes were printed on the surface of the TCO film.

[0097] Comparative Example 2

[0098] A method for preparing a low-indium heterojunction battery comprises selecting an N-type single crystal silicon wafer, performing pre-doping, cleaning and texturing on the wafer, and using the wafer as a crystalline silicon substrate.

[0099] The intrinsic amorphous silicon film is deposited on the upper surface and the back side of the substrate respectively by using the PECVD method;

[0100] Depositing an N-type microcrystalline silicon doping layer on the top surface of the intrinsic amorphous silicon film on the upper surface of the substrate by using a PECVD method;

[0101] Depositing a P-type microcrystalline silicon doping layer on the bottom surface of the intrinsic amorphous silicon film on the back side of the substrate by using a PECVD method;

[0102] A TCO composite film is prepared on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer respectively;

[0103] ITO was deposited on the top surface of the N-type microcrystalline doped layer and the bottom surface of the P-type microcrystalline silicon doped layer by magnetron sputtering PVD. The deposition pressure was kept within 0.35Pa-0.45Pa, the target speed was 5r / min, the oxygen-argon flow ratio was 3.0%, the deposition thickness was 100nm, and the TCO film was vacuum annealed at 180°C for 30 minutes. After annealing, the TCO composite film was treated with hydrogen plasma using PECVD equipment at a treatment temperature of 160°C, a treatment time of 15 minutes, and a radio frequency power of 300W.

[0104] Silver gate electrodes were printed on the surface of the TCO film.

[0105] The performance of the low-indium TCO composite film and the low-indium heterojunction battery in the examples and comparative examples was tested. The specific test results are shown in the following table, where the electrical parameters in Table 2 were normalized and compared with Comparative Example 1.

[0106] Table 1 Film performance test

[0107] sample <![CDATA[Carrier concentration / cm^ -3 > <![CDATA[Mobility cm 2 / (V·s)]]> Transmittance / % Example 1 8.48E+19 38.0 90.59 Example 2 8.28E+19 33.0 91.24 Example 3 1.07E+20 32.1 91.11 Example 4 1.42E+20 32.2 91.03 Example 5 9.91E+19 34.7 88.24 Example 6 9.77E+19 32.5 88.99 Example 7 1.33E+20 31.6 90.55 Comparative Example 1 3.43E+20 30.9 88.43 Comparative Example 2 3.28E+20 31.9 89.01

[0108] Table 2 Battery sample performance test

[0109] sample Isc / mA Voc / mV FF / % Eta / % Example 1 1.004 1.004 1.000 0.986 Example 2 1.006 1.006 1.000 0.989 Example 3 1.006 1.006 1.000 0.993 Example 4 1.009 1.009 1.000 0.998 Example 5 0.997 0.997 0.999 0.974 Example 6 0.997 0.997 1.000 0.976 Example 6 1.006 1.006 1.000 0.993 Comparative Example 1 1.000 1.000 1.000 1.000 Comparative Example 2 1.005 1.005 1.000 1.002

[0110] From the above embodiments and comparative examples, it can be seen that after the first sub-TCO film is deposited, vacuum annealing is used. Compared with an oxidizing atmosphere (such as air), the internal stress of the first sub-TCO film is released to the greatest extent, which can improve the crystallinity of the film, reduce internal defects, and help to improve the oxidation degree of doped atoms in the film, thereby improving the transmittance of the composite film in the visible light range. The first sub-TCO film and the second sub-TCO film have different optimal annealing atmospheres and temperatures. Vacuum annealing the first sub-TCO film alone is better than vacuum annealing the entire composite film in improving the performance of the composite film. After the second sub-TCO film is treated with hydrogen plasma, it is beneficial to form doubly charged oxygen vacancies (VO 2+ ). The generation of doubly charged oxygen vacancies releases two electrons, thereby increasing the overall carrier concentration. On the other hand, hydrogen plasma treatment is equivalent to physical texturing, which can improve the surface roughness of the film, increase the transmittance, and play a positive role in improving the optoelectronic performance.

[0111] The TCO composite film in the low-indium heterojunction battery of the present invention adopts a composite structure of low-pressure deposition of indium-based and high-pressure deposition of indium-free thin film. The first sub-TCO film and the second sub-TCO film are thin films of different material systems, and the appropriate preparation deposition pressures are different. When the first sub-TCO film is prepared at a higher gas pressure, the surface roughness is too high, the grain size is reduced, and oxygen is more easily adsorbed in the grains on the surface of the film, which reduces the carrier concentration and mobility, resulting in an increase in resistivity. The second sub-TCO film is prepared under higher gas pressure conditions, the film has a larger grain size, fewer grain boundaries and defects, higher transmittance, and better photoelectric performance, which significantly reduces the indium content in the TCO film. While avoiding almost no loss of the photoelectric properties of the TCO film layer, it greatly reduces the cost and alleviates the problem of tight indium resources.

[0112] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a low-indium heterojunction battery, characterized in that: The method comprises the following steps: Providing a substrate, and using an alkaline solution and an additive to form a double-sided pyramid velvet surface on the upper surface and the back surface of the substrate; forming a first intrinsic passivation layer and a second intrinsic passivation layer on the upper surface and the back surface of the substrate respectively; forming an N-type doped silicon layer or an N-type doped silicon oxide layer on the upper surface of the first intrinsic passivation layer, and forming a P-type doped silicon layer or a P-type doped silicon oxide layer on the back surface of the second intrinsic passivation layer; A TCO composite film is formed on the upper surface and the back doped silicon layer by a PVD or RPD method, wherein the TCO composite film is divided into a first sub-TCO film and a second sub-TCO film, and is deposited in separate chambers; The plated TCO composite film is subjected to hydrogen plasma treatment; A front metal patterned electrode and a back metal patterned electrode are respectively formed on the upper surface and the back surface of the second sub-TCO film by screen printing or copper electroplating.

2. The method for preparing a low-indium heterojunction battery according to claim 1, characterized in that: The first passivation layer and the second passivation layer are made of intrinsic amorphous silicon, and both have a thickness ranging from 3nm to 10nm.

3. The method for preparing a low-indium heterojunction battery according to claim 1, characterized in that: The thickness of the N-type doped silicon layer or the N-type doped silicon oxide layer is 5nm-25nm, and the thickness of the P-type doped silicon layer or the P-type doped silicon oxide layer is 10nm-35nm.

4. The method for preparing a low-indium heterojunction battery according to claim 1, characterized in that: The first sub-TCO film is an indium oxide system TCO film deposited at low pressure, which is in contact with the doped silicon layer. The first sub-TCO film is deposited in the first deposition chamber, the deposition gas pressure is between 0.2Pa and 0.8Pa, the oxygen-argon flow ratio is between 2.0% and 5.0%, the hydrogen-argon flow ratio is between 0% and 3.5%, and the deposition thickness is 40nm-60nm.

5. The method for preparing a low-indium heterojunction battery according to claim 4, characterized in that: The first sub-TCO film was subjected to vacuum annealing treatment with a chamber pressure of 5×10 -2 Pa-5×10 -3 Pa. The annealing temperature is 180°C and the annealing time is 30 min.

6. The method for preparing a low-indium heterojunction battery according to claim 1, characterized in that: The second sub-TCO film is a TCO film of tin oxide or zinc oxide system deposited under high pressure, which is in contact with the metal gate line. The second sub-TCO film is deposited in the second deposition chamber, the deposition gas pressure is between 0.9Pa and 1.2Pa, the oxygen-argon flow ratio is between 2.0% and 5.0%, and the deposition thickness is 40nm-60nm.

7. The method for preparing a low-indium heterojunction battery according to claim 1, characterized in that: The optimal deposition temperatures of the first sub-TCO film and the second sub-TCO film are both 90° C.-250° C.

8. The method for preparing a low-indium heterojunction battery according to claim 1, characterized in that: The total thickness of the composite TCO film is 90nm-110nm, and the thickness of the first sub-TCO film is greater than or equal to the thickness of the second sub-TCO film.

9. The method for preparing a low-indium heterojunction battery according to claim 1, characterized in that: The hydrogen plasma treatment of the plated TCO composite film adopts the PECVD method to perform plasma treatment, and hydrogen is introduced to make it glow discharge. The radio frequency power is 200W-1500W, the plasma treatment temperature is 80℃-160℃, and the treatment time is 5min-15min.

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