BUCK converter overcurrent protection circuit and method for ripple V2COT control

Abstract

The invention discloses a BUCK converter over-current protection circuit based on ripple V2COT control. The BUCK converter over-current protection circuit comprises a current sampling circuit, a comparator and a frequency reduction circuit which are connected in sequence. The current sampling circuit generates a sampling voltage, the current sampling circuit further comprises a reference voltage generating circuit which outputs a reference voltage and inputs the voltage and the reference voltage into a comparator for comparison to obtain an overcurrent signal, and the overcurrent signal is input into the frequency reduction circuit to generate a frequency reduction signal. Through combinational logic of a gate circuit, a frequency reduction signal is output. The ripple injection circuit is connected to the grid electrode of the MOS tube, and the output waveform of the ripple injection circuit is adjusted by controlling the on and off of the MOS tube, so that the working frequency of the system is reduced. The problem that the circuit recovery time is long after the overcurrent is eliminated is solved, the faster the circuit recovery is, the smaller the risk of element damage is, the higher the system reliability is correspondingly, and the development requirements of high reliability and safety of contemporary electronic products are met.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management chips, and in particular to a power management chip for ripple V 2 A COT controlled BUCK converter overcurrent protection circuit and method. Background Art

[0002] With the rapid development of applications such as mobile devices, smart homes and automotive electronics, people have put forward higher and higher requirements on the performance indicators of various electronic products. Buck converters are widely used in various new electronic devices because of their small area, low cost, high conversion efficiency and a variety of selectable control modes, which can meet the index requirements of different products under different conditions. In this context, power management chips are developing towards high efficiency, miniaturization, high reliability and safety. As an important component of power management chips, the research significance of overcurrent protection circuits has become increasingly prominent.

[0003] In order to ensure the safety and stable operation of electronic equipment, designing efficient overcurrent protection circuits has become an urgent task for researchers and engineers, and quickly entering the protection state and quickly resuming normal operation are important design indicators of overcurrent protection circuits. The method used by the traditional constant on-time controlled BUCK converter is "hiccup mode overcurrent protection", which uses the soft start signal to periodically shut down the output. The advantage of this method is that it effectively reduces the power consumption under continuous overcurrent conditions and prevents the system from damaging components due to overcurrent. However, the disadvantage is that after the overcurrent is eliminated, it takes a long time for the circuit to return to normal operation. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a ripple V 2 COT controlled BUCK converter overcurrent protection circuit and method. Aiming at the problem of long recovery time of traditional "hiccup mode overcurrent protection", the present invention proposes a circuit and method that can adapt to the ripple V 2 The overcurrent protection circuit and method of the COT-controlled BUCK converter adopts an overcurrent signal delay circuit composed of a D trigger, a Schmitt trigger, a gate circuit, an RC circuit and a diode.

[0005] Through the combinational logic of the gate circuit, the frequency reduction signal is output. Then it is connected to the gate of the MOS tube, and the output waveform of the ripple injection circuit is adjusted by controlling the on and off of the MOS tube, thereby reducing the operating frequency of the system. The problem of long circuit recovery time after overcurrent elimination is solved. The faster the circuit recovers, the smaller the risk of component damage, and the higher the system reliability, which conforms to the development requirements of high reliability and safety of contemporary electronic products.

[0006] Technical solution: A method for ripple V 2The COT-controlled BUCK converter overcurrent protection circuit comprises a current sampling circuit, a comparator CMP3 and a frequency reduction circuit connected in sequence; the current sampling circuit generates a sampling voltage V through an Mn sampling tube. sen The current sampling circuit also includes a reference voltage generating circuit outputting a reference voltage V th_oc , and the voltage V sen and reference voltage V th_oc The overcurrent signal OCP is input to the comparator CMP3 for comparison, and the overcurrent signal OCP is input to the frequency reduction circuit to generate the frequency reduction signal V COMPLOCK .

[0007] Furthermore, the frequency reduction circuit includes: a D trigger, a Schmitt trigger, a gate circuit, an RC circuit and a diode;

[0008] The D trigger includes a D1 trigger and a D2 trigger;

[0009] The Schmitt triggers include Schmitt trigger G1, Schmitt trigger G2, and Schmitt trigger G3;

[0010] The RC circuit includes a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, and a capacitor C3;

[0011] The gate circuit includes INV1, INV2, INV3, and INV4;

[0012] The diodes include a diode VD1 and a diode VD2;

[0013] The overcurrent signal OCP generated by the comparator CMP3 is connected to the input end of the Schmitt trigger G1 through the resistor R3. One end of the capacitor C1 is connected to the resistor R3 as the input end of the Schmitt trigger G1, and the other end is grounded. The output end of the Schmitt trigger G1 is connected to the CP end of the D1 trigger, and the D ends of the D1 and D2 triggers are connected to the internal power supply voltage VCC. The output end of the D1 trigger The input end of INV1 is connected to the output end of INV1, and the resistor R4 and the negative end of the diode VD1 are connected to output signal CP1; the positive end of the diode VD1 is connected to the resistor R4, the capacitor C2, and the input end of the Schmitt trigger G2, and the Schmitt trigger G2 outputs a reset signal RM1, which is connected to the reset end of the D1 trigger as the reset signal of the D1 trigger; the CP1 signal is connected to the input end of INV2, and the output signal CP2 is connected to the CP end of the D2 trigger as the clock signal of the D2 trigger; the output end of the D2 trigger The output terminal of INV3 is connected to the negative terminal of the resistor R5 and the diode VD2, and the output signal OC is connected; the positive terminal of the diode VD2 is connected to the resistor R5, the capacitor C3, and the input terminal of the Schmitt trigger G3; the Schmitt trigger G3 outputs a reset signal RM2, which is connected to the reset terminal of the D2 trigger as the reset signal of the D2 trigger; the OC signal is connected to the second input terminal of the OR gate and the first input terminal of the NOR gate; the conduction signal T on Connect to the first input of the OR gate, and the output signal is CTRL; the overcurrent signal OCP is connected to the second input of the NOR gate, and the CP1 signal is connected to the third input of the NOR gate, and the frequency reduction signal V is output through INV4. COMPLOCK .

[0014] The present invention also discloses an overcurrent protection method, comprising the following steps:

[0015] Step 1: Build a V-based 2 COT controlled BUCK converter architecture;

[0016] Step 2: Amplify the feedback voltage V through the error amplifier FB and reference voltage V REF The difference between the control signal Vea and the ripple injection signal V is obtained. Then Vea passes through the ripple injection circuit to obtain the ripple injection signal V COMP , use this signal to compare with the feedback voltage; after passing through the constant on-time circuit, a square wave signal is finally obtained to control the on and off of the switch tube to adjust the output voltage, so that the output voltage is stabilized at the set value;

[0017] Step 3: Design the overcurrent protection circuit and collect the sampling voltage V sen and reference voltage V th_oc ;

[0018] Step 4: When the sampling voltage V sen >Reference voltage V th_oc When the OCP output is high, the inductor current is limited to I LIMIT ; The frequency reduction circuit generates a frequency reduction signal V COMPLOCK , so that the freewheeling tube continues to conduct, and the inductor current continues to decrease;

[0019] Step 5, design a frequency reduction circuit, including: a D trigger, a Schmitt trigger, a gate circuit, an RC circuit and a diode; the D trigger includes a D1 trigger and a D2 trigger; the Schmitt trigger includes a Schmitt trigger G1, a Schmitt trigger G2, and a Schmitt trigger G3; the RC circuit includes a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, and a capacitor C3; the gate circuit includes INV1, INV2, INV3, and INV4; the diode includes a diode VD1 and a diode VD2;

[0020] The overcurrent signal OCP generated by the comparator CMP3 is connected to the input end of the Schmitt trigger G1 through the resistor R3. One end of the capacitor C1 is connected to the resistor R3 as the input end of the Schmitt trigger G1, and the other end is grounded. The output end of the Schmitt trigger G1 is connected to the CP end of the D1 trigger, and the D ends of the D1 and D2 triggers are connected to the internal power supply voltage VCC. The output end of the D1 trigger The input end of INV1 is connected to the output end of INV1, and the resistor R4 and the negative end of the diode VD1 are connected to output signal CP1; the positive end of the diode VD1 is connected to the resistor R4, the capacitor C2, and the input end of the Schmitt trigger G2, and the Schmitt trigger G2 outputs a reset signal RM1, which is connected to the reset end of the D1 trigger as the reset signal of the D1 trigger; the CP1 signal is connected to the input end of INV2, and the output signal CP2 is connected to the CP end of the D2 trigger as the clock signal of the D2 trigger; the output end of the D2 trigger The output terminal of INV3 is connected to the negative terminal of the resistor R5 and the diode VD2, and the output signal OC is connected; the positive terminal of the diode VD2 is connected to the resistor R5, the capacitor C3, and the input terminal of the Schmitt trigger G3; the Schmitt trigger G3 outputs a reset signal RM2, which is connected to the reset terminal of the D2 trigger as the reset signal of the D2 trigger; the OC signal is connected to the second input terminal of the OR gate and the first input terminal of the NOR gate; the conduction signal T on Connect to the first input of the OR gate, and the output signal is CTRL; the overcurrent signal OCP is connected to the second input of the NOR gate, and the CP1 signal is connected to the third input of the NOR gate, and the frequency reduction signal V is output through INV4. COMPLOCK ; V COMPLOCK The signal is connected to the gate terminal of the Mk tube to control the on and off of the Mk tube;

[0021] Step 6: When the circuit is overcurrent, the OCP signal outputs a high level and generates a clock signal CP through the Schmitt trigger; the rising edge of the CP signal causes Flips to low level, CP1 is high level, the diode is cut off, and capacitor C2 is charged through resistor R4; when the capacitor is charged to the forward threshold voltage of the Schmitt trigger, the reset signal RM1 of the D1 trigger is valid at low level, Flip to high level, CP1 generates a falling edge, and CP2 gets a rising edge; using

[0022] —CP2 rising edge generates a precise delayed OC signal. The delay time between the OC signal and the OCP signal is equal to the low level pulse width of Q1.

[0023] Step 7: When the system is working normally, the overcurrent signal OCP is at a low level, and OC is also at a low level. The conduction of the switch tube is mainly determined by T on Signal decision; when the system overcurrent occurs, in order to prevent the output voltage from dropping too low and causing the chip to shut down; the OC signal and T on The signal outputs the control signal CTRL through the OR gate, and the two jointly control the conduction of the switch tube, the overcurrent signal OCP, the delay signal OC and the clock signal CP1, and outputs V through the NOR gate and the inverter. COMPLOCK signal, as long as one of the input signals is high, the output signal V COMPLOCK is high level; when V COMPLOCK When the signal is high, the Mk tube is turned on, and the drain potential is pulled down, making V COMP <V FB , conduction signal T on Output low level; if OC is also low level at this time, the CTRL signal is low level, The off time of the switch tube is extended, the switching frequency is reduced, and a new cycle begins after the inductor current drops to a normal range.

[0024] Further, step 1 is specifically as follows: the architecture includes a switch tube MN1, a freewheeling tube MN2, an inductor L, a resistor voltage divider network, and an output capacitor C out , load resistance R L And the system control loop; the system control loop is divided into a voltage inner loop and a voltage outer loop; the feedback voltage is input to the loop comparator as the voltage inner loop to obtain a fast transient response; the EA amplifier constitutes the voltage outer loop to ensure V out The DC accuracy follows V REF .

[0025] Further, step 3 is specifically as follows: the overcurrent protection circuit includes a sampling circuit, a comparator, and a frequency reduction circuit; when the gate drive signal of the freewheeling tube is at a high level, the Mn tube is turned on, and the current sampling circuit starts to work; the current sampling circuit generates a sampling voltage V through the Mn sampling tube sen The sampling circuit also includes a reference voltage generating circuit output signal V th_oc , the sampling voltage Vsen and reference voltage V th_oc The input is sent to CMP3 for comparison to obtain the over-current signal OCP.

[0026] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0027] (1) The present invention outputs a frequency reduction signal through the combination logic of the gate circuit. Then it is connected to the gate of the MOS tube, and the output waveform of the ripple injection circuit is adjusted by controlling the on and off of the MOS tube, thereby reducing the operating frequency of the system. The problem of long circuit recovery time after overcurrent elimination is solved. The faster the circuit recovers, the smaller the risk of component damage, and the higher the system reliability is, which complies with the development requirements of high reliability and safety of contemporary electronic products. When an overcurrent occurs in the circuit, a frequency reduction circuit is used to adjust the output waveform of the feedback loop control signal, reduce the system operating frequency, and reduce the output current.

[0028] (2) The present invention realizes that a single circuit has the dual functions of ripple injection and overcurrent protection, thereby improving the response speed of the system. After the fault is eliminated, the circuit recovery time is short.

[0029] (3) The frequency reduction circuit of the present invention will only be turned on when there is overcurrent and will not affect the normal operation of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The overall architecture of the circuit;

[0031] Figure 2 This is the block diagram of the overcurrent protection circuit;

[0032] Figure 3 It is a frequency reduction circuit;

[0033] Figure 4 This is the simulation of the electrical frequency reduction function; among them, (a) the key output waveform of the frequency reduction circuit; (b) the VCOMP output waveform without the frequency reduction circuit; (c) the VCOMP output waveform with the frequency reduction circuit added.

[0034] Figure 5 The working waveforms of the converter under different loads; (a) light load mode (DCM); (b) heavy load mode (CCM); (c) overcurrent mode; (d) local amplified waveform in the overcurrent recovery stage. DETAILED DESCRIPTION

[0035] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0036] The main purpose of the present invention is to provide a method for V 2 A circuit that quickly recovers a COT-controlled buck converter after overcurrent is eliminated.

[0037] It aims to solve the problem of long circuit recovery time after the overcurrent condition disappears.

[0038] To achieve the above purpose, the present invention provides an overcurrent protection circuit. The overcurrent protection circuit of the present invention mainly includes a current sampling circuit, a comparator, and a frequency reduction circuit, so that after the overcurrent is eliminated, the circuit can quickly return to a normal working state. The specific steps are as follows:

[0039] (1) A V 2 COT controlled BUCK converter architecture, such as Figure 1 The architecture mainly consists of switch tube MN1, freewheeling tube MN2, inductor L, resistor voltage divider network, output capacitor C out , load resistance R L The system control loop is divided into a voltage inner loop and a voltage outer loop. The feedback voltage is input to the loop comparator as the voltage inner loop to obtain a fast transient response. The EA amplifier constitutes the voltage outer loop to ensure that V out The DC accuracy can well follow V REF .

[0040] (2) The feedback voltage V is amplified by the error amplifier FB and reference voltage V REF The difference between the control signal Vea and the ripple injection signal V is obtained. Then Vea passes through the ripple injection circuit to obtain the ripple injection signal V COMP , use this signal to compare with the feedback voltage. After the constant on-time circuit, we finally get a square wave signal to control the on and off of the switch tube to adjust the output voltage, so that the output voltage is stable at our set value.

[0041] (3) The overcurrent protection circuit designed this time, such as Figure 2 As shown. The circuit consists of a current sampling circuit, a comparator, and a frequency reduction circuit. When the gate drive signal of the freewheeling tube is high, the Mn tube is turned on and the current sampling circuit starts to work. The current sampling circuit generates a sampling voltage V through the Mn sampling tube. sen The sampling circuit also includes a reference voltage generating circuit outputting a signal V th_oc , the sampling voltage V sen and reference voltage V th_oc The input is sent to CMP3 for comparison to obtain the over-current signal OCP.

[0042] (4) When V sen >V th_oc When the OCP output is high, the inductor current is limited to I LIMIT The frequency reduction circuit generates a frequency reduction signal V COMPLOCK , so that the freewheeling tube continues to conduct and the inductor current continues to decrease.

[0043] (5) The frequency reduction circuit of the present invention is as follows: Figure 3 As shown. The overcurrent signal delay circuit consists of a D trigger, a Schmitt trigger, a gate circuit, an RC circuit and a diode. The circuit consists of two parts with the same structure. First, the overcurrent signal OCP generated by CMP3 is connected to the input of the G1 Schmitt trigger through the resistor R3. The output of the G1 Schmitt trigger is connected to the CP of the D1 trigger. The D terminals of the D1 and D2 triggers are connected to the internal power supply voltage VCC. The output of the D1 trigger The output terminal of INV1 is connected to the negative terminal of the resistor R4 and the diode VD1, and the output signal CP1 is connected. The positive terminal of the diode VD1 is connected to the resistor R4, the capacitor C2, and the input terminal of the Schmitt trigger G2. The Schmitt trigger G2 outputs the reset signal RM1, which is connected to the reset terminal of the D1 trigger as the reset signal of the D1 trigger. The CP1 signal is connected to the input terminal of INV2, and the output signal CP2 is connected to the CP terminal of the D2 trigger as the clock signal of the D2 trigger. The output terminal of the D2 trigger The output terminal of INV3 is connected to the negative terminal of resistor R5 and diode VD2, and the output signal OC is output. The positive terminal of diode VD2 is connected to resistor R5, capacitor C3, and the input terminal of Schmitt trigger G3. The reset signal output by Schmitt trigger G3 is RM2, which is connected to the reset terminal of D2 trigger as the reset signal of D2 trigger. The OC signal is connected to the second input terminal of OR gate and the first input terminal of NOR gate. The conduction signal T on Connect to the first input of the OR gate, and the output signal is CTRL. The overcurrent signal OCP is connected to the second input of the NOR gate, and the CP1 signal is connected to the third input of the NOR gate, and through INV4, the frequency reduction signal V is output. COMPLOCK .like Figure 1 As shown, V COMPLOCK The signal is connected to the gate terminal of the Mk tube to control the on and off of the Mk tube.

[0044] When the circuit is overcurrent, the OCP signal outputs a high level and generates a clock signal CP through the Schmitt trigger. The rising edge of the CP signal Flips to low level, CP1 is high level, the diode is cut off, and capacitor C2 is charged through resistor R4. When the capacitor is charged to the forward threshold voltage of the Schmitt trigger, the reset signal RM1 of the D1 trigger is low level effective. Flip to high level, CP1 generates a falling edge, and CP2 gets a rising edge. Using the rising edge of CP2, a precise delayed OC signal is generated. The delay time of the OC signal and the OCP signal is equal to The low level pulse width.

[0045] When the system is working normally, the overcurrent signal OCP is low level, OC is also low level, and the conduction of the switch tube is mainly determined by T on When the system is overcurrent, the output voltage will not drop too low, causing the chip to shut down. on The signal outputs the control signal CTRL through the OR gate, and the two jointly control the conduction of the switch tube, the overcurrent signal OCP, the delay signal OC and the clock signal CP1, and outputs V through the NOR gate and the inverter. COMPLOCK signal, as long as one of the input signals is high, the output signal V COMPLOCK is high level. Figure 1 As shown, when V COMPLOCK When the signal is high, the Mk tube is turned on, and the drain potential is pulled down, making V COMP <V FB , conduction signal T on Output low level. If OC is also low level at this time, the CTRL signal is low level. The switch off time is extended, the switching frequency is reduced, and a new cycle starts after the inductor current drops to a normal range.

[0046] Figure 4 The simulation results of the frequency reduction function are given. Figure 4 It can be seen from (a) that when the freewheeling diode is turned on and the inductor current is 3.9A, OCP = 1, and the circuit turns on the overcurrent protection function. During the rising edge of the OCP signal and the falling edge of the OC signal, V COMPLOCK Basically remain in the high level state, so that V COMP is low level. Figure 4 It can be seen from (b) and (c) that before adding the frequency reduction circuit, V COMP The output waveform is a sawtooth wave, which becomes a triangle wave after adding the frequency reduction circuit, making V COMP Continuously lower than the feedback voltage V FB , realizing the frequency reduction function.

[0047] First, the effectiveness of the present invention is verified. The experimental environment is Cadence6.1.8, based on the ripple V 2 The COT control mode proposes an overcurrent protection method. Figure 5 The overcurrent protection output waveform of the circuit is given when the current limit threshold is 3.9A. First, Figure 5 (a) is the operating waveform of the converter under light load conditions. It can be seen from the figure that the peak inductor current is 1.9A and there is no overcurrent phenomenon. As the load increases to heavy load, the converter switches to CCM. Figure 5 In (b), the output waveform is stable and the switching frequency is 333kHz. Figure 5 In (c), the circuit has an overcurrent and the switching frequency drops to 91kHz. Figure 5It can be seen from the partially enlarged waveform in (d) that after the overcurrent disappears, the output voltage rises to 1.2V after 18μs, and the circuit recovery time is short, which verifies the effectiveness of the present invention in solving the long overcurrent recovery time problem.

Claims

1. A ripple V 2 The COT controlled BUCK converter overcurrent protection circuit is characterized by: It includes a current sampling circuit, a comparator CMP3 and a frequency reduction circuit connected in sequence; the current sampling circuit generates a sampling voltage V through the Mn sampling tube sen The current sampling circuit also includes a reference voltage generating circuit outputting a reference voltage V th_oc , and the voltage V sen and reference voltage V th_oc The overcurrent signal OCP is input to the comparator CMP3 for comparison, and the overcurrent signal OCP is input to the frequency reduction circuit to generate the frequency reduction signal V COMPLOCK .

2. A method for ripple V according to claim 1. 2 The COT controlled BUCK converter overcurrent protection circuit is characterized by: The frequency reduction circuit includes: a D trigger, a Schmitt trigger, a gate circuit, an RC circuit and a diode; The D trigger includes a D1 trigger and a D2 trigger; The Schmitt triggers include Schmitt trigger G1, Schmitt trigger G2, and Schmitt trigger G3; The RC circuit includes a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, and a capacitor C3; The gate circuit includes INV1, INV2, INV3, and INV4; The diodes include a diode VD1 and a diode VD2; The overcurrent signal OCP generated by the comparator CMP3 is connected to the input end of the Schmitt trigger G1 through the resistor R3. One end of the capacitor C1 is connected to the resistor R3 as the input end of the Schmitt trigger G1, and the other end is grounded. The output end of the Schmitt trigger G1 is connected to the CP end of the D1 trigger, and the D ends of the D1 and D2 triggers are connected to the internal power supply. voltage VCC; the output terminal Q1 of the D1 trigger is connected to the input terminal of INV1, the output terminal of INV1 is connected to the resistor R4 and the negative terminal of the diode VD1, and the output signal CP1 is output; the positive terminal of the diode VD1 is connected to the resistor R4, the capacitor C2, and the input terminal of the Schmitt trigger G2, and the Schmitt trigger G2 outputs the reset signal RM1, which is connected to the reset terminal of the D1 trigger as the reset signal of the D1 trigger; the CP1 signal is connected to the input terminal of INV2, and the output signal CP2 is connected to the input terminal of the D1 trigger. The CP terminal of the D2 trigger is used as the clock signal of the D2 trigger; the output terminal Q2 of the D2 trigger is connected to the input terminal of INV3, the output terminal of INV3 is connected to the resistor R5 and the negative terminal of the diode VD2, and the output signal OC is output; the positive terminal of the diode VD2 is connected to the resistor R5, the capacitor C3, and the input terminal of the Schmitt trigger G3; the Schmitt trigger G3 outputs a reset signal RM2, which is connected to the reset terminal of the D2 trigger as the reset signal of the D2 trigger; the OC signal is connected to the second input terminal of the OR gate and the first input terminal of the NOR gate; the conduction signal T on Connect to the first input of the OR gate, and the output signal is CTRL; the overcurrent signal OCP is connected to the second input of the NOR gate, and the CP1 signal is connected to the third input of the NOR gate, and the frequency reduction signal V is output through INV4. COMPLOCK .

3. An overcurrent protection method based on the circuit of claim 1, characterized in that: The steps include: Step 1: Build a V-based 2 COT controlled BUCK converter architecture; Step 2: Amplify the feedback voltage V through the error amplifier FB and reference voltage V REF The difference between the control signal Vea and the ripple injection signal V is obtained. Then Vea passes through the ripple injection circuit to obtain the ripple injection signal V COMP , use this signal to compare with the feedback voltage; after passing through the constant on-time circuit, a square wave signal is finally obtained to control the on and off of the switch tube to adjust the output voltage, so that the output voltage is stabilized at the set value; Step 3: Design the overcurrent protection circuit and collect the sampling voltage V sen and reference voltage V th_oc ; Step 4: When the sampling voltage V sen >Reference voltage V th_oc When the OCP output is high, the inductor current is limited to I LIMIT ; The frequency reduction circuit generates a frequency reduction signal V COMPLOCK , so that the freewheeling tube continues to conduct, and the inductor current continues to decrease; Step 5, design a frequency reduction circuit, including: a D trigger, a Schmitt trigger, a gate circuit, an RC circuit and a diode; the D trigger includes a D1 trigger and a D2 trigger; the Schmitt trigger includes a Schmitt trigger G1, a Schmitt trigger G2, and a Schmitt trigger G3; the RC circuit includes a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, and a capacitor C3; the gate circuit includes INV1, INV2, INV3, and INV4; the diode includes a diode VD1 and a diode VD2; The overcurrent signal OCP generated by the comparator CMP3 is connected to the input end of the Schmitt trigger G1 through the resistor R3. One end of the capacitor C1 is connected to the resistor R3 as the input end of the Schmitt trigger G1, and the other end is grounded. The output end of the Schmitt trigger G1 is connected to the CP end of the D1 trigger, and the D ends of the D1 and D2 triggers are connected to the internal power supply. voltage VCC; the output terminal Q1 of the D1 trigger is connected to the input terminal of INV1, the output terminal of INV1 is connected to the resistor R4 and the negative terminal of the diode VD1, and the output signal CP1 is output; the positive terminal of the diode VD1 is connected to the resistor R4, the capacitor C2, and the input terminal of the Schmitt trigger G2, and the Schmitt trigger G2 outputs a reset signal RM1, which is connected to the reset terminal of the D1 trigger as the reset signal of the D1 trigger; the CP1 signal is connected to the input terminal of INV2, and the output signal CP2 is connected to the CP terminal of the D2 trigger as the clock signal of the D2 trigger; the output terminal of the D2 trigger The output terminal of INV3 is connected to the negative terminal of the resistor R5 and the diode VD2, and the output signal OC is connected; the positive terminal of the diode VD2 is connected to the resistor R5, the capacitor C3, and the input terminal of the Schmitt trigger G3; the Schmitt trigger G3 outputs a reset signal RM2, which is connected to the reset terminal of the D2 trigger as the reset signal of the D2 trigger; the OC signal is connected to the second input terminal of the OR gate and the first input terminal of the NOR gate; the conduction signal T on Connect to the first input of the OR gate, and the output signal is CTRL; the overcurrent signal OCP is connected to the second input of the NOR gate, and the CP1 signal is connected to the third input of the NOR gate, and the frequency reduction signal V is output through INV4. COMPLOCK ; V COMPLOCK The signal is connected to the gate terminal of the Mk tube to control the on and off of the Mk tube; Step 6: When the circuit is overcurrent, the OCP signal outputs a high level and generates a clock signal CP through the Schmitt trigger; the rising edge of the CP signal causes Flips to low level, CP1 is high level, the diode is cut off, and capacitor C2 is charged through resistor R4; when the capacitor is charged to the forward threshold voltage of the Schmitt trigger, the reset signal RM1 of the D1 trigger is valid at low level, Flip to high level, CP1 generates a falling edge, and CP2 gets a rising edge; using the rising edge of CP2, a precise delayed OC signal is generated, and the delay time of the OC signal and the OCP signal is equal to The low level pulse width; Step 7: When the system is working normally, the overcurrent signal OCP is at a low level, and OC is also at a low level. The conduction of the switch tube is mainly determined by T on Signal decision; when the system overcurrent occurs, in order to prevent the output voltage from dropping too low and causing the chip to shut down; the OC signal and T on The signal outputs the control signal CTRL through the OR gate, and the two jointly control the conduction of the switch tube, the overcurrent signal OCP, the delay signal OC and the clock signal CP1, and outputs V through the NOR gate and the inverter. COMPLOCK signal, as long as one of the input signals is high, the output signal V COMPLOCK is high level; when V COMPLOCK When the signal is high, the Mk tube is turned on, and the drain potential is pulled down, making V COMP <V FB , conduction signal T on Output low level; if OC is also low level at this time, the CTRL signal is low level, The off time of the switch tube is extended, the switching frequency is reduced, and a new cycle begins after the inductor current drops to a normal range.

4. The overcurrent protection method according to claim 3, characterized in that: Step 1 is as follows: the architecture includes a switch tube MN1, a freewheeling tube MN2, an inductor L, a resistor voltage divider network, and an output capacitor C out , load resistance R L And the system control loop; the system control loop is divided into a voltage inner loop and a voltage outer loop; the feedback voltage is input to the loop comparator as the voltage inner loop to obtain a fast transient response; the EA amplifier constitutes the voltage outer loop to ensure that V out The DC accuracy follows V REF .

5. The overcurrent protection method according to claim 3, characterized in that: Step 3 is as follows: the overcurrent protection circuit includes a sampling circuit, a comparator, and a frequency reduction circuit; when the gate drive signal of the freewheeling tube is at a high level, the Mn tube is turned on, and the current sampling circuit starts to work; the current sampling circuit generates a sampling voltage V through the Mn sampling tube. sen The sampling circuit also includes a reference voltage generating circuit output signal V th_oc , the sampling voltage V sen and reference voltage V th_oc The input is sent to CMP3 for comparison to obtain the over-current signal OCP.

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