Apparatus and method for making master and spare clock plate phase position alignment

Abstract

This invention discloses a device for aligning phases of master and backup clock boards including: a direct digit merging device for adjusting the phase of the local clock, a phase test module for testing the phase difference between the local output clock and the opposite clock, a central process unit computing the value of a phase register in the direct digit merger based on the phase difference tested by the phase test module, a phase-locking device for locking the phase to the input clock of the clock board. This invention also discloses a method for aligning phases of a master and a backup boards including: when this clock board is a backup one, the phase test module tests the phase difference of the output clock of this clock and that of the opposite, the central process unit lets the merging device align with the phase aligned by the master and the backup clocks based on tested phase difference.

Description

technical field [0001] The invention relates to a network communication technology, in particular to a device and a method for aligning the phases of the active and standby clock boards. Background technique [0002] The clock is a key component of communication equipment, and the performance of the clock will affect the performance of the single board and even the entire system. Therefore, it is very important for the communication equipment to ensure the accuracy and stability of various performances of the communication equipment clock. Therefore, all communication organizations, countries and operators must strictly test the performance of the clock of the device before the device is connected to the network. The performance indicators of the clock mainly include frequency and phase. Usually, the performance of the above indicators includes long-term stability, long-term accuracy, hold performance, phase transient and phase discontinuity, etc. [0003] Communication eq...

AI Technical Summary

Problems solved by technology

[0005] However, this method has the following disadvantages: the output signal needs to go through multi-stage frequency multiplication / division, which increases the phase noise, increases the jitter of the output signal, and affects the signal quality; it takes up a lot of logic resources and requires high speed of the logic circuit; Phase alignment accuracy is low, for example, using a high-frequency 100MHz counting clock, its phase accuracy is 10.0ns

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