Method of fast analog layout migration

a technology of analog layout and migration method, applied in the direction of cad techniques, instruments, program control, etc., can solve the problems of inability to move exactly the same topology in the migrated technology, the cad tools in analog circuits still require manual intervention, and the process is quite time-consuming and tedious, so as to achieve the effect of fast analog layout migration

Active Publication Date: 2012-11-29
SYNOPSYS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enables fast and systematic analog layout migration, reducing design time by generating optimized placements that maintain circuit performance and flexibility, while satisfying constraints, thus improving the efficiency of the layout migration process.

Problems solved by technology

On the contrary, CAD tools in analog circuits still require much manual intervention.
Such process is quite time consuming and tedious.
The new result with exactly the same topology may not be the desired placement in the migrated technology because of the layout dimension or the layout area.
As layout becomes complicated, it becomes very time-consuming.
As a result, layout compaction is not a good approach since it just shrinks the chip size according to new device dimensions without considering any other optimized layout solutions.
In addition, layout compaction does not provide sufficient flexibility for designers to modify layouts for other objectives as well.

Method used

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  • Method of fast analog layout migration
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Embodiment Construction

[0028]The detailed explanation of the present invention is described as following. The described preferred embodiments are presented for purposes of illustrations and description, and they are not intended to limit the scope of the present invention.

[0029]In this invention, a systematic and automatic methodology which can quickly produce multiple placement results based on a reference layout is described. These placement results can be viewed as initial solutions to allow designers to choose. First, a method of extracting relative placement pattern from the original layout placement and saving it into a constraint hierarchy tree is presented. Some important constraints such as symmetry or matching will be handled in the hierarchical construction. A relative placement pattern can be saved into a constraint tree node. Then, the new layout placement is generated by using the constraint tree to migrate an existing layout according to a new technology.

[0030]The methodology of the present...

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Abstract

A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of priority of U.S. Provisional Application No. 61 / 489,269, filed May 24, 2011, and titled “Constraint Hierarchy Driven Automatic IC Placement”, the contents of which are herein incorporated by reference in its entirety.[0002]This application is related to U.S. application Ser. No. 13 / 349,584, filed Jan. 13, 2012, and titled “Method of Constraint-Hierarchy-Driven IC Placement”, which claims the benefit of priority of the above-mentioned U.S. Provisional Application No. 61 / 489,269.BACKGROUND OF THE INVENTION[0003]1. Field of the Invention[0004]The present invention relates to an analog layout migration methodology for quickly providing multiple layouts for integrated circuit (IC), and more particularly, to a method for providing analog layout results with different aspect ratios while keeping similar or better circuit performance of the original layout.[0005]2. Description of the Prior Art[0006]In modern...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G06F17/50
CPCG06F17/5072G06F17/5081G06F2217/06G06F2111/04G06F30/392G06F30/398
InventorCHEN, TUNG-CHIEHCHEN, HUNG-MINGWENG, YI-PENG
OwnerSYNOPSYS INC