Image processing apparatus, method for controlling image processing apparatus, and storage medium
a technology for image processing and image processing equipment, which is applied in the direction of visual presentation, instruments, computing, etc., can solve the problem of processing taking longer to compl
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first embodiment
[0028]FIG. 1 is a diagram illustrating a configuration of a data processing system including an image processing apparatus indicating an embodiment of the present disclosure. This system has a configuration in which an image formation apparatus 101 and an image processing apparatus 102 are connected to each other over a network 103.
[0029]In FIG. 1, when a user performs printing using an application for the image processing apparatus 102, print data is generated by a driver and transmitted to the image formation apparatus 101 over the network 103. The image formation apparatus 101 performs printing on the basis of the print data.
[0030]FIG. 2 is a block diagram illustrating a hardware configuration of the image formation apparatus 101 illustrated in FIG. 1. In FIG. 2, the image formation apparatus 101 includes a read-only memory (ROM) 401, a random-access memory (RAM) 402, a central processing unit (CPU) 403, a hard disk drive (HDD) 404, a network interface (I / F) 405, an engine I / F 40...
second embodiment
[0073]The first embodiment has described securing a bit map memory for each page during generation of intermediate data. Hereinafter, the second embodiment will describe an example of, when performing first tile conversion processing, previously acquiring a bit map memory to be used in common to pages in preparation for second tile conversion processing, and sharing between pages the bit map memory firstly secured by managing release information about the bit map memory.
[0074]FIG. 11 is a flowchart illustrating a method for controlling an image processing apparatus indicating the present embodiment. This example is a detailed procedure of a bit map memory acquisition flow of S1003 illustrated in FIG. 4. Each step is implemented by a CPU 403 executing a stored control program. The following principally describes modules to be executed by the CPU 403 illustrated in FIG. 3.
[0075]In response to a request for bit map memory acquisition, a memory management unit 207 calculates a bit map m...
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