Integrated multimedia system
a multimedia system and integrated technology, applied in the field of data processing system, can solve the problems of system delaying bottlenecks, pci bus experiencing severe bottlenecking, and conventional microprocessor based systems employing 3d graphics processing have experienced bandwidth limitations
Inactive Publication Date: 2007-09-18
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Problems solved by technology
However, these systems experience delaying bottlenecks during data intensive operations that transfer data between the main processor and the graphics chip.
The bandwidth requirements to implement a 3D graphics system depends on the complexity of the system.
As mentioned above, conventional microprocessor based systems employing 3D graphics processing have experienced bandwidth limitations.
Thus, the PCI bus may experience severe bottle necking.
Another bandwidth limitation in implementing 3D graphics processing is data transfers from frame buffers to the 3D graphics chip.
Such data transfer rates are not feasible with the current memory technology.
Thus, current 3D graphics arrangements employ substantially lower resolutions, which would not lead to realistic images.
Another disadvantage with prior art multimedia systems is their data transfer arrangement methods.
However, the arrangement disclosed in the '965 patent does not provide for a priority based data movement.
Furthermore, it does not disclose a mechanism to handle data transfers between endpoints that exhibit mismatched bandwidth requirements.
Additionally, conventional data movement arrangements have failed to address application-specific requirements.
Another disadvantage with conventional systems is that the resources employed by the data movement arrangements cannot be flexibly specified based on a corresponding data transfer between two end points.
Method used
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, for the source side, this is “x” and for the destination transfer it is “y”. Every data location address used by a channel is first added to a base address. This base address value is held in the channel's state memory. When a channel is initialized by the ds_open_path ( ) call, this base address value is set to zero. This value can be changed by the user using the Control descriptor (described below).
[0244]Table 21 below shows how the descriptors for the source and destination transfers are configured, for a data transfer from SDRAM 128 into data cache 108, i.e., a cache pre-load operation.
[0245]The control word at the source indicates coherent data operation, but does not allocate. The halt bit is not set since there are no more descriptors, and the channel automatically halts when done transferring this data. The “No more descriptor” bit must be set.
[0246]
TABLE 21Source DescriptorSource DescriptorBitsExplanation 0:31 next descriptor0only one descriptor34:47 countn48:63 control ...
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An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I / O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I / O device driver units and external I / O devices via output pins.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of, and claims the benefit of priority to, Applicant's U.S. application Ser. No. 09 / 172,286, filed Oct. 14, 1998 now U.S. Pat. No. 6,347,344, which is incorporated by reference herein as fully as if set forth in its entirety.FIELD OF THE INVENTION[0002]The present invention relates to a data processing system having various modules, and more specifically to a system that is capable to perform a plurality of graphic tasks on a chip set.BACKGROUND OF THE INVENTION[0003]During the recent years, the demand for low cost multimedia systems that can be incorporated in a computer system or function as a stand alone system has been steadily increasing. There has been some effort to create multimedia processor systems that are primarily software driven or, alternatively, are primarily hardware driven. Some of these multimedia systems employ a separate three dimensional 3D graphic chip that is coupled to a main pro...
Claims
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IPC IPC(8): G06F3/00G06F1/00G06F13/14G06F15/16G06F15/76G06T1/20G06F13/10G06F13/12G06F13/28G06F13/36G06F15/78G06T15/00
CPCG06F13/102G06F13/124G06T15/005
InventorBAKER, DAVIDBASOGLU, CHRISTOPHERCUTLER, BENJAMINDEELEY, RICHARDGERVASIO, GREGORIOKAWAGUCHI, ATSUOKOJIMA, KEIJILEE, WOOBINMIYAZAKI, TAKESHIMUNDKUR, YATINNAIK, VINAYNISHIOKA, KIYOKAZUNOJIRI, TORUO'DONNELL, JOHNPADALKAR, SARANG
OwnerHITACHI LTD