A built-in regulator circuit with temperature compensation and its implementation method

Abstract

The present invention provides a built-in regulator circuit with temperature compensation. When the chip input is high voltage, the circuit generates a stable and reliable working voltage for other modules to work normally without the need for a specially designed bandgap reference circuit module and loop compensation at the output end. The design of the chip internal circuit is simple, and the standby current of the chip itself is very small when the chip is working. Various devices can effectively compensate the output voltage according to the change of temperature, and the output voltage can be made unstable without being affected by the temperature, thereby ensuring the normal operation of the chip in various temperature environments. The present invention has a simple circuit implementation, is applicable to various currently common high-voltage CMOS process circuits, and is safe and reliable in use, which not only saves costs but also greatly reduces the research and development cycle.

Description

Technical Field

[0001] The invention relates to the field of circuits, in particular to a high-voltage CMOS process circuit. Background Art

[0002] With the rapid development of the integrated circuit industry, people have higher and higher requirements for chip integration, but the chip area is getting smaller and smaller, which requires continuous simplification of the circuit design inside the chip. Figure 1 As shown: the circuit includes a circuit bias circuit, a startup circuit, a bandgap reference circuit, an operational amplifier circuit, an N-channel enhancement MOS tube, an operational amplifier compensation resistor and a feedback resistor. The current bias circuit generates a bias current in the circuit, and the bandgap reference circuit is started by the startup circuit, and then the output loop is compensated by the operational amplifier circuit and the capacitor. The use of this traditional design method not only makes the internal circuit complex and the chip's own standby circuit very large, but also when the chip is used in a high-voltage circuit, many high-voltage devices are used in the chip, resulting in a larger area required for the chip. In addition, a special compensation circuit must be designed at the output end for stability compensation, and some also require capacitors for output compensation, which further increases the chip's design area and makes the chip's design cost higher.

[0003] Therefore, it is urgent to develop a safe and reliable built-in regulator circuit with temperature compensation that can be applied to high-voltage circuits and has a simple internal circuit, does not require an output compensation circuit, has a small area, and has a low standby current. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the present invention provides a simple built-in Regulator circuit with temperature compensation, which can ensure that when the chip input is high voltage, a stable and reliable working voltage can be generated inside the circuit for the normal operation of other modules without the need for a specially designed bandgap reference circuit module inside the chip and without loop compensation at the output end, so as to solve the shortcomings of the above-mentioned problems.

[0005] The technical solution adopted by the present invention to solve its technical problem is:

[0006] A built-in regulator circuit with temperature compensation, comprising high-voltage P-channel enhancement MOS transistors PM1-PM2, high-voltage N-channel enhancement MOS transistors NM1-NM3, N-channel enhancement MOS transistors NM4-NM7, resistors R1-R3, a current bias circuit module, a VIN input port and VP1 and VP2 output ports, wherein the VIN port is a high-voltage input port, and VP1 and VP2 are regulator voltage output ports of the circuit;

[0007] The output end of the bias current circuit module is connected to the gate drain of the high-voltage P-channel enhancement mode MOS transistor PM1 and the gate of the high-voltage P-channel enhancement mode MOS transistor PM2, and provides a bias current with a positive temperature coefficient.

[0008] The source of the high-voltage P-channel enhancement type MOS transistor PM1 is connected to the VIN port, and the gate and drain are connected to the gate of the high-voltage P-channel enhancement type MOS transistor PM2 and the input end of the bias current circuit module; the source of the high-voltage P-channel enhancement type MOS transistor PM2 is connected to the VIN port, the gate is connected to the gate and drain of the high-voltage P-channel enhancement type MOS transistor PM1 and the input end of the bias current circuit module, and the drain is connected to the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2, and the gate of the high-voltage N-channel enhancement type MOS transistor NM3; the high-voltage P-channel enhancement type MOS transistors PM1 and PM2 form a current mirror structure circuit.

[0009] The gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1 are connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the cathode of the diode D1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the source is connected to the gate and drain of the N-channel enhancement type MOS transistor NM4; the drain of the high-voltage N-channel enhancement type MOS transistor NM2 is connected to the VIN port, the gate is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the source is connected to one end of the resistor R2 and the output port VP1; the drain of the high-voltage N-channel enhancement type MOS transistor NM3 is connected to one end of the resistor R1, the gate is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1 and the gate of the high-voltage N-channel enhancement type MOS transistor NM2, and the source is connected to one end of the resistor R3 and the output port VP2.

[0010] The gate and drain of the N-channel enhancement type MOS tube NM4 are connected to the source of the high-voltage N-channel enhancement type MOS tube NM1, and the source is connected to the gate and drain of the N-channel enhancement type MOS tube NM5; the gate and drain of the N-channel enhancement type MOS tube NM5 are connected to the source of the N-channel enhancement type MOS tube NM4, and the source is connected to the gate and drain of the N-channel enhancement type MOS tube NM6; the gate and drain of the N-channel enhancement type MOS tube NM6 are connected to the source of the N-channel enhancement type MOS tube NM5, and the source is connected to the gate and drain of the N-channel enhancement type MOS tube NM7; the gate and drain of the N-channel enhancement type MOS tube NM7 are connected to the source of the N-channel enhancement type MOS tube NM6, and the source is grounded; the N-channel enhancement type MOS tubes NM4-NM7 are all connected in a diode manner.

[0011] The cathode of the diode D1 is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate drain of the high-voltage N-channel enhancement type MOS transistor NM1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the anode is grounded; one end of the resistor R1 is connected to the VIN port, and the other end is connected to the drain of the high-voltage N-channel enhancement type MOS transistor NM3; one end of the resistor R2 is connected to the source of the high-voltage N-channel enhancement type MOS transistor NM2 and the output port of VP1, and the other end is grounded; one end of the resistor R3 is connected to the source of the high-voltage N-channel enhancement type MOS transistor NM3 and the output port of VP2, and the other end is grounded; the diode D1 has a voltage stabilizing effect, the resistor R1 has a current limiting and ESD protection effect, and the resistors R2 and R3 have a biasing effect on the output branches of VP1 and VP2.

[0012] The implementation method of the built-in regulator circuit with temperature compensation is:

[0013] When VIN is powered on normally, the current bias circuit module provides a current with a positive temperature coefficient. The current passes through the current mirror circuit composed of the high-voltage P-channel enhancement MOS transistors PM1 and PM2, and generates a mirror current I1 at the drain of the high-voltage P-channel enhancement MOS transistor PM2; N-channel enhancement MOS transistors NM4-NM7 all work in the saturation region in a diode connection mode, and are used as resistors and clamp their respective voltages. Since the resistance value Ron of the N-channel enhancement MOS transistor is equal to the inverse of the transconductance gm in the saturation region, the resistance value of each N-channel enhancement MOS transistor NM4-NM7 is:

[0014]

[0015] where μ n is the electron mobility of the N-channel enhancement mode MOS tube, C ox is the gate oxide capacitance per unit area, I D is the current flowing through the tube I 1 , L is the gate length in the source-drain direction of the N-channel enhancement type MOS tube, and W is the gate width in the source-drain direction of the N-channel enhancement type MOS tube.

[0016] The current I through the source and drain of each N-channel enhancement MOS tube NM4-NM7 1 It has a positive temperature coefficient, adjusts the bias current and the parameters of the N-channel enhancement MOS tubes NM4-NM7, so that the gate of the high-voltage N-channel enhancement MOS tube NM1 generates a voltage V that is independent of temperature. G , where the source and drain voltages of the diode-connected N-channel enhancement MOS transistors NM4-NM7 are V DS for:

[0017] V DS =Ron I 1 (2)

[0018] Will I D =I 1 Substituting into formula (1) we get:

[0019]

[0020] The source voltage of the high-voltage N-channel enhancement-mode MOS tube NM1 is:

[0021] V S =V DS4 +V DS5 +V DS6 +V DS7 (4)

[0022] Then the gate voltage of the high-voltage N-channel enhancement MOS tube NM1 is:

[0023] V G =V S +V TH1 (5)

[0024] Where V TH1 is the threshold voltage of the high voltage N-channel enhancement mode MOS tube NM1;

[0025] The high-voltage N-channel enhancement-type MOS transistors NM2 and NM3 match the high-voltage N-channel enhancement-type MOS transistor NM1, and the threshold voltages are equal, so the adjusted output voltage is:

[0026] VP1=V G -V TH2 (6)

[0027] Substituting formula (5) into the equation, we get:

[0028] VP1=V DS4 +V DS5 +V DS6 +V DS7 (7)

[0029] Similarly, we can get:

[0030] VP2=V DS4 +V DS5 +V DS6 +V DS7 (8)

[0031] In the VP2 branch, there is a resistor R1 between the drain of the high-voltage N-channel enhancement mode MOS tube NM3 and the VIN input port, which limits the current and performs ESD protection on the VP2 branch, thereby driving the subsequent stage and different circuit modules of VP1.

[0032] The required stable output Regulator voltage values ​​VP1 and VP2 are generated by changing the number of N-channel enhancement mode MOS transistors connected by diodes on the high-voltage N-channel enhancement mode MOS transistor NM1 branch and the width-to-length ratio of the N-channel enhancement mode MOS transistor itself.

[0033] The beneficial effect of the present invention is that the built-in regulator circuit with temperature compensation of the present invention can convert the high voltage input into a stable chip internal operating voltage without the need to design a bandgap reference circuit inside the chip, and does not need loop compensation at the output end. Due to the simple internal circuit of the chip designed in this way, the standby current of the chip itself is very small when the chip is working. In addition, since various devices in the internal circuit can effectively compensate the output voltage according to the change of temperature, the output voltage can be made unstable without being affected by the temperature, thereby ensuring the normal operation of the chip in various temperature environments. The present invention has a simple circuit implementation, is applicable to various currently common high-voltage CMOS process circuits, and is safe and reliable in use, which not only saves costs but also greatly reduces the research and development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of a traditional Regulator circuit.

[0035] Figure 2 Schematic diagram of a built-in regulator circuit with temperature compensation according to the present invention. DETAILED DESCRIPTION

[0036] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0037] A built-in regulator circuit with temperature compensation, such as Figure 2 As shown, it includes high-voltage P-channel enhancement MOS transistors PM1-PM2, high-voltage N-channel enhancement MOS transistors NM1-NM3, N-channel enhancement MOS transistors NM4-NM7, resistors R1-R3, a current bias circuit module, a VIN input port and VP1 and VP2 output ports, wherein the VIN port is a high-voltage input port, and VP1 and VP2 are the Regulator voltage output ports of the circuit;

[0038] The output end of the bias current circuit module is connected to the gate drain of the high-voltage P-channel enhancement mode MOS transistor PM1 and the gate of the high-voltage P-channel enhancement mode MOS transistor PM2, providing a bias current with a positive temperature coefficient for the overall circuit.

[0039] The source of the high-voltage P-channel enhancement type MOS transistor PM1 is connected to the VIN port, and the gate and drain are connected to the gate of the high-voltage P-channel enhancement type MOS transistor PM2 and the input end of the bias current circuit module; the source of the high-voltage P-channel enhancement type MOS transistor PM2 is connected to the VIN port, the gate is connected to the gate and drain of the high-voltage P-channel enhancement type MOS transistor PM1 and the input end of the bias current circuit module, and the drain is connected to the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2, and the gate of the high-voltage N-channel enhancement type MOS transistor NM3; the high-voltage P-channel enhancement type MOS transistors PM1 and PM2 form a current mirror structure circuit.

[0040] The gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1 are connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the cathode of the diode D1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the source is connected to the gate and drain of the N-channel enhancement type MOS transistor NM4; the drain of the high-voltage N-channel enhancement type MOS transistor NM2 is connected to the VIN port, the gate is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the source is connected to one end of the resistor R2 and the output port VP1; the drain of the high-voltage N-channel enhancement type MOS transistor NM3 is connected to one end of the resistor R1, the gate is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1 and the gate of the high-voltage N-channel enhancement type MOS transistor NM2, and the source is connected to one end of the resistor R3 and the output port VP2.

[0041] The gate and drain of the N-channel enhancement type MOS tube NM4 are connected to the source of the high-voltage N-channel enhancement type MOS tube NM1, and the source is connected to the gate and drain of the N-channel enhancement type MOS tube NM5; the gate and drain of the N-channel enhancement type MOS tube NM5 are connected to the source of the N-channel enhancement type MOS tube NM4, and the source is connected to the gate and drain of the N-channel enhancement type MOS tube NM6; the gate and drain of the N-channel enhancement type MOS tube NM6 are connected to the source of the N-channel enhancement type MOS tube NM5, and the source is connected to the gate and drain of the N-channel enhancement type MOS tube NM7; the gate and drain of the N-channel enhancement type MOS tube NM7 are connected to the source of the N-channel enhancement type MOS tube NM6, and the source is grounded; the N-channel enhancement type MOS tubes NM4-NM7 are all connected in a diode manner, act as resistors, and have a negative temperature coefficient.

[0042] The cathode of the diode D1 is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate drain of the high-voltage N-channel enhancement type MOS transistor NM1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the anode is grounded; one end of the resistor R1 is connected to the VIN port, and the other end is connected to the drain of the high-voltage N-channel enhancement type MOS transistor NM3; one end of the resistor R2 is connected to the source of the high-voltage N-channel enhancement type MOS transistor NM2 and the output port of VP1, and the other end is grounded; one end of the resistor R3 is connected to the source of the high-voltage N-channel enhancement type MOS transistor NM3 and the output port of VP2, and the other end is grounded; wherein the diode D1 plays a role of voltage stabilization, the resistor R1 plays a role of current limiting and ESD protection, and the resistors R2 and R3 play a role of biasing the output branches of VP1 and VP2.

[0043] The built-in regulator circuit with temperature compensation can generate the required stable output regulator voltage values ​​VP1 and VP2 by changing the number of N-channel enhancement MOS transistors connected by diodes on the high-voltage N-channel enhancement MOS transistor NM1 branch and the width-to-length ratio of the N-channel enhancement MOS transistor itself.

[0044] The implementation method of the built-in regulator circuit with temperature compensation is:

[0045] When VIN is powered on normally, the current bias circuit module provides a current with a positive temperature coefficient. The current passes through the current mirror circuit composed of the high-voltage P-channel enhancement MOS transistors PM1 and PM2, and generates a mirror current I1 at the drain of the high-voltage P-channel enhancement MOS transistor PM2; N-channel enhancement MOS transistors NM4-NM7 all work in the saturation region in a diode connection mode, and are used as resistors and clamp their respective voltages. Since the resistance value Ron of the N-channel enhancement MOS transistor is equal to the inverse of the transconductance gm in the saturation region, the resistance value of each N-channel enhancement MOS transistor NM4-NM7 is:

[0046]

[0047] where μ n is the electron mobility of the N-channel enhancement mode MOS tube, C ox is the gate oxide capacitance per unit area, I D is the current flowing through the tube, which is I in this circuit. 1 , L is the gate length in the source-drain direction of the N-channel enhancement type MOS tube, and W is the gate width in the source-drain direction of the N-channel enhancement type MOS tube.

[0048] Since the current I passes through the source and drain of each N-channel enhancement MOS tube NM4-NM7 1The N-channel enhancement MOS tubes NM4-NM7 with positive temperature coefficient and diode connection have a very small positive temperature coefficient when used as resistors, and the threshold voltage V TH1 It has a negative temperature coefficient, so the bias current and the parameters of the N-channel enhancement MOS transistors NM4-NM7 are adjusted so that the gate of the high-voltage N-channel enhancement MOS transistor NM1 generates a voltage V that is independent of temperature. G , where the source and drain voltages of the diode-connected N-channel enhancement MOS transistors NM4-NM7 are V DS for:

[0049] V DS =R on I 1 (2)

[0050] Will I D =I 1 Substituting into formula (1) we get:

[0051]

[0052] The source voltage of the high-voltage N-channel enhancement-mode MOS tube NM1 is:

[0053] V S =V DS4 +V DS5 +V DS6 +V DS7 (4)

[0054] Then the gate voltage of the high-voltage N-channel enhancement MOS tube NM1 is:

[0055] V G =V S +V TH1 (5)

[0056] Where V TH1 is the threshold voltage of the high voltage N-channel enhancement mode MOS tube NM1;

[0057] Because the high-voltage N-channel enhancement-mode MOS transistors NM2 and NM3 match the high-voltage N-channel enhancement-mode MOS transistor NM1 and their threshold voltages are equal, the adjusted output voltage is:

[0058] VP1=V G -V TH2 (6)

[0059] Substituting formula (5) into the equation, we get:

[0060] VP1=V DS4 +V DS5 +V DS6+V DS7 (7)

[0061] Similarly, we can get:

[0062] VP2=V DS4 +V DS5 +V DS6 +V DS7 (8)

[0063] Because a resistor R1 is added between the drain of the high-voltage N-channel enhancement mode MOS tube NM3 and the VIN input port in the VP2 branch, the VP2 branch is current limited and ESD protected, thereby being able to drive the subsequent circuit modules different from VP1.

[0064] In summary, the present invention proposes a simple built-in regulator circuit with temperature compensation. The implementation method is simple, no bandgap reference and loop compensation are required inside the circuit, it can be applied to various high-voltage CMOS process circuits, and has a series of advantages such as low standby current.

Claims

1. A built-in regulator circuit with temperature compensation, characterized in that: The built-in regulator circuit with temperature compensation includes high-voltage P-channel enhancement MOS tubes PM1-PM2, high-voltage N-channel enhancement MOS tubes NM1-NM3, N-channel enhancement MOS tubes NM4-NM7, resistors R1-R3, a current bias circuit module, a VIN input port and VP1 and VP2 output ports, wherein the VIN input port is a high-voltage input port, VP1 and VP2 are regulator voltage output ports of the circuit, and the output end of the current bias circuit module is connected to the gate drain of the high-voltage P-channel enhancement MOS tube PM1 and the gate of the high-voltage P-channel enhancement MOS tube PM2, providing a bias current with a positive temperature coefficient; The source of the high-voltage P-channel enhancement type MOS transistor PM1 is connected to the VIN port, and the gate and drain are connected to the gate of the high-voltage P-channel enhancement type MOS transistor PM2 and the input end of the current bias circuit module; the source of the high-voltage P-channel enhancement type MOS transistor PM2 is connected to the VIN port, the gate is connected to the gate and drain of the high-voltage P-channel enhancement type MOS transistor PM1 and the input end of the current bias circuit module, and the drain is connected to the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2, and the gate of the high-voltage N-channel enhancement type MOS transistor NM3; the high-voltage P-channel enhancement type MOS transistors PM1 and PM2 form a current mirror structure circuit; The gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1 are connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the cathode of the diode D1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the source is connected to the gate and drain of the N-channel enhancement type MOS transistor NM4; the drain of the high-voltage N-channel enhancement type MOS transistor NM2 is connected to the VIN port, the gate is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the source is connected to one end of the resistor R2 and the output port VP1; the drain of the high-voltage N-channel enhancement type MOS transistor NM3 is connected to one end of the resistor R1, the gate is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate and drain of the high-voltage N-channel enhancement type MOS transistor NM1, the cathode of the diode D1 and the gate of the high-voltage N-channel enhancement type MOS transistor NM2, and the source is connected to one end of the resistor R3 and the output port VP2; The gate and drain of the N-channel enhancement type MOS transistor NM4 are connected to the source of the high-voltage N-channel enhancement type MOS transistor NM1, and the source is connected to the gate and drain of the N-channel enhancement type MOS transistor NM5; the gate and drain of the N-channel enhancement type MOS transistor NM5 are connected to the source of the N-channel enhancement type MOS transistor NM4, and the source is connected to the gate and drain of the N-channel enhancement type MOS transistor NM6; the gate and drain of the N-channel enhancement type MOS transistor NM6 are connected to the source of the N-channel enhancement type MOS transistor NM5, and the source is connected to the gate and drain of the N-channel enhancement type MOS transistor NM7; the gate and drain of the N-channel enhancement type MOS transistor NM7 are connected to the source of the N-channel enhancement type MOS transistor NM6, and the source is grounded; the N-channel enhancement type MOS transistors NM4-NM7 are all connected in a diode manner; The cathode of the diode D1 is connected to the drain of the high-voltage P-channel enhancement type MOS transistor PM2, the gate drain of the high-voltage N-channel enhancement type MOS transistor NM1, the gate of the high-voltage N-channel enhancement type MOS transistor NM2 and the gate of the high-voltage N-channel enhancement type MOS transistor NM3, and the anode is grounded; one end of the resistor R1 is connected to the VIN port, and the other end is connected to the drain of the high-voltage N-channel enhancement type MOS transistor NM3; one end of the resistor R2 is connected to the source of the high-voltage N-channel enhancement type MOS transistor NM2 and the output port of VP1, and the other end is grounded; one end of the resistor R3 is connected to the source of the high-voltage N-channel enhancement type MOS transistor NM3 and the output port of VP2, and the other end is grounded; the diode D1 has a voltage stabilizing effect, the resistor R1 has a current limiting and ESD protection effect, and the resistors R2 and R3 have a biasing effect on the output branches of VP1 and VP2.

2. The built-in regulator circuit with temperature compensation according to claim 1, characterized in that: The required stable output Regulator voltage values ​​VP1 and VP2 are generated by changing the number of N-channel enhancement mode MOS transistors connected by diodes on the high-voltage N-channel enhancement mode MOS transistor NM1 branch and the width-to-length ratio of the N-channel enhancement mode MOS transistor itself.

3. A method for implementing the built-in regulator circuit with temperature compensation according to claim 1, characterized in that The steps include: When VIN is powered on normally, the current bias circuit module provides a current with a positive temperature coefficient. The current passes through the current mirror circuit composed of the high-voltage P-channel enhancement MOS transistors PM1 and PM2, and generates a mirror current I1 at the drain of the high-voltage P-channel enhancement MOS transistor PM2; N-channel enhancement MOS transistors NM4-NM7 all work in the saturation region in a diode connection mode, and are used as resistors and clamp their respective voltages. Since the resistance value Ron of the N-channel enhancement MOS transistor is equal to the inverse of the transconductance gm in the saturation region, the resistance value of each N-channel enhancement MOS transistor NM4-NM7 is: Where μn is the electron mobility of the N-channel enhancement MOS tube, Cox is the gate oxide capacitance per unit area, ID is the current I1 flowing through the tube, L is the gate length in the source-drain direction of the N-channel enhancement MOS tube, and W is the gate width in the source-drain direction of the N-channel enhancement MOS tube; By adjusting the bias current and the parameters of the N-channel enhancement type MOS tubes NM4-NM7, the gate of the high-voltage N-channel enhancement type MOS tube NM1 generates a voltage VG that is independent of temperature, and the source and drain voltages VDS of the N-channel enhancement type MOS tubes NM4-NM7 in diode connection are: VDS=Ron·I1 (2) Substituting ID=I1 and equation (1) into the equation, we get: The source voltage of the high-voltage N-channel enhancement-mode MOS tube NM1 is: VS=VDS4+VDS5+VDS6+VDS7 (4) Then the gate voltage of the high-voltage N-channel enhancement MOS tube NM1 is: VG=VS+VTH1 (5) Where VTH1 is the threshold voltage of the high-voltage N-channel enhancement-mode MOS transistor NM1; The high-voltage N-channel enhancement-type MOS transistors NM2 and NM3 match the high-voltage N-channel enhancement-type MOS transistor NM1, and the threshold voltages are equal, so the adjusted output voltage is: VP1=VG-VTH2 (6) Substituting formula (5) into the equation, we get: VP1=VDS4+VDS5+VDS6+VDS7 (7) Similarly, we can get: VP2=VDS4+VDS5+VDS6+VDS7 (8) In the VP2 branch, there is a resistor R1 between the drain of the high-voltage N-channel enhancement mode MOS tube NM3 and the VIN input port, which limits the current and performs ESD protection on the VP2 branch, thereby driving the subsequent stage and different circuit modules of VP1.

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