Manufacturing method of anti-fuse structure and anti-fuse structure

Abstract

The present invention provides a method for manufacturing an anti-fuse structure and an anti-fuse structure. A first ion implantation process is performed to form a functional well and a first bottom isolation well in a substrate enclosed by an isolation structure. The functional well extends from the upper surface of the substrate into the substrate. The first bottom isolation well is located below the functional well in the same pattern. A second ion implantation process is performed to form a side isolation well and a second bottom isolation well in a substrate complementary to the first ion implantation process pattern. The side isolation well extends from the upper surface of the substrate into the substrate and covers the isolation structure. The second bottom isolation well is located below the side isolation well in the same pattern. The first bottom isolation well, the side isolation well and the second bottom isolation well belong to the same ion implantation type and belong to different ion implantation types from the functional well. The first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer. Thus, the anti-fuse structure can be formed through fewer mask processes, thereby reducing the manufacturing cost of the anti-fuse structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a manufacturing method of an anti-fuse structure and the anti-fuse structure. Background Art

[0002] When at least one unit cell in a semiconductor device is defective or fails during the manufacturing process, the semiconductor device cannot be used as a memory device. A memory having at least one faulty unit cell is classified as a defective product and results in reduced production efficiency. Therefore, a technology has been developed to replace defective cells with redundant cells to repair defective cells in a memory device. For example, one type of memory circuit includes a dynamic random access memory (DRAM) array of memory cells arranged in rows and columns, each of which is addressable for storing information bits. If a defective cell is detected in a test operation after the memory device is manufactured, a write operation is performed in the internal circuit of the memory device to replace the defective cell with a redundant cell.

[0003] At present, the selection of redundant cells is mainly achieved by designing fuse structures and / or anti-fuse structures in the memory. The method of repairing semiconductor devices through fuse structures is to perform a write repair process at the wafer level, which cannot be applied to packaged semiconductor devices. Moreover, as the integration of semiconductors gradually increases, the fuse structure is limited by the spot size of the laser beam, so the existing repair method more often chooses the anti-fuse structure.

[0004] The repair method of the antifuse structure is that when it is not written, the antifuse is usually non-conductive (high resistance), and when the voltage applied to the antifuse exceeds a certain value, the antifuse is turned on and becomes a conductor. The unwritten antifuse is equivalent to a capacitor, and the current is extremely small or zero during the read operation; the written antifuse is equivalent to a resistor, and the current will increase significantly during the read operation. The antifuse structure selectively connects parts of the circuit together, so that previously unconnected devices can be used in the circuit to complete the repair process.

[0005] In the existing process, the manufacturing cost of the anti-fuse structure remains high, so how to reduce the manufacturing cost of the anti-fuse structure has become a problem that those skilled in the art have been looking forward to solving. Summary of the invention

[0006] The object of the present invention is to provide a method for manufacturing an anti-fuse structure and an anti-fuse structure, so as to solve the problem of high manufacturing cost of the anti-fuse structure in the prior art.

[0007] In order to solve the above technical problems, the present invention provides a method for manufacturing an anti-fuse structure, comprising:

[0008] A substrate is provided, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are ring-shaped and enclose a portion of the substrate;

[0009] Performing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate enclosed by the isolation structure, respectively, wherein the functional well extends from the upper surface of the substrate into the substrate, and the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types;

[0010] Performing a second ion implantation process, including forming a side isolation well and a second bottom isolation well in the substrate complementary to the first ion implantation process pattern, the side isolation well extending from the upper surface of the substrate into the substrate and covering the isolation structure to isolate the adjacent functional wells, the second bottom isolation well being located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well are of the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and

[0011] An anti-fuse is formed on the functional well.

[0012] Optionally, in the method for manufacturing the antifuse structure, performing the first ion implantation process comprises the following steps:

[0013] Under a first mask, performing a first step of a first ion implantation process to form one of the functional well and the first bottom isolation well in the substrate; and

[0014] A second step of the first ion implantation process is continued under the first mask to form the other of the functional well and the first bottom isolation well in the substrate.

[0015] Optionally, in the manufacturing method of the anti-fuse structure, the ion implantation energy for forming the functional well is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the first bottom isolation well is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e13.

[0016] Optionally, in the method for manufacturing the anti-fuse structure, performing the second ion implantation process comprises the following steps:

[0017] Under a second mask, performing a first step of a second ion implantation process to form one of the side isolation well and the second bottom isolation well in the substrate; and

[0018] A second step of a second ion implantation process is continued under the second mask to form the other of the side isolation well and the second bottom isolation well in the substrate.

[0019] Optionally, in the manufacturing method of the anti-fuse structure, the ion implantation energy for forming the side isolation well is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the second bottom isolation well is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e13.

[0020] Optionally, in the method for manufacturing the anti-fuse structure, the functional well and the side isolation well have the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

[0021] Optionally, in the method for manufacturing the anti-fuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well;

[0022] The method of forming an antifuse on the functional well comprises the following steps:

[0023] forming an anti-fuse active region in the functional well, wherein the anti-fuse active region extends from an upper surface of the functional well into the functional well; and

[0024] A conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region, so that the anti-fuse is formed by using the anti-fuse active region, the separated portion of the dielectric layer and the conductive layer.

[0025] Optionally, in the method for manufacturing the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

[0026] Optionally, in the method for manufacturing the anti-fuse structure, the anti-fuse active area is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer, and the conductive layer extends to cover a portion of the side isolation well.

[0027] Optionally, in the method for manufacturing the anti-fuse structure, after forming the anti-fuse, the method for manufacturing the anti-fuse structure further includes:

[0028] A contact point is formed in the anti-fuse active region, wherein the contact point extends from a portion of the upper surface of the anti-fuse active region outside the coverage area of ​​the conductive layer to the anti-fuse active region.

[0029] The present invention also provides an anti-fuse structure, comprising:

[0030] A substrate, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are ring-shaped and enclose a portion of the substrate;

[0031] a functional well formed in the substrate enclosed by the isolation structure, wherein the functional well extends from the upper surface of the substrate into the substrate;

[0032] a first bottom isolation well formed in the substrate enclosed by the isolation structure, wherein the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types;

[0033] A side isolation well is formed in the substrate in a complementary manner to the functional well pattern, the side isolation well extends from the upper surface of the substrate into the substrate and covers the isolation structure to isolate the adjacent functional wells;

[0034] a second bottom isolation well formed in the substrate, the second bottom isolation well being located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well are of the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and

[0035] An anti-fuse is formed on the functional well.

[0036] Optionally, in the anti-fuse structure, the functional well and the side isolation well have the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

[0037] Optionally, in the anti-fuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; the anti-fuse includes:

[0038] an anti-fuse active region, the anti-fuse active region is formed in the functional well, and the anti-fuse active region extends from the upper surface of the functional well into the functional well;

[0039] a conductive layer, wherein the conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region; and

[0040] The dielectric layer is spaced apart from a spacer portion between the conductive layer and the anti-fuse active region.

[0041] Optionally, in the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

[0042] Optionally, in the anti-fuse structure, the conductive layer extends to cover a portion of the side isolation well.

[0043] Optionally, in the anti-fuse structure, the anti-fuse structure further includes a contact point formed in the anti-fuse active region, and the contact point extends from the upper surface portion of the anti-fuse active region outside the coverage area of ​​the conductive layer to the anti-fuse active region.

[0044] The present invention also provides a method for manufacturing an anti-fuse structure, comprising:

[0045] A substrate is provided, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are ring-shaped and enclose a portion of the substrate;

[0046] Performing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate enclosed by the isolation structure, respectively, wherein the functional well extends from the upper surface of the substrate into the substrate, and the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types;

[0047] Performing a second ion implantation process, including forming a second bottom isolation well in the substrate having a complementary pattern to the first ion implantation process, wherein the second bottom isolation well extends from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well are of the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer that isolates the functional wells; and

[0048] An anti-fuse is formed on the functional well.

[0049] Optionally, in the method for manufacturing the anti-fuse structure, the second bottom isolation well covers an inner sidewall of the isolation structure.

[0050] Optionally, in the method for manufacturing the anti-fuse structure, the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

[0051] Optionally, in the method for manufacturing the antifuse structure, performing the first ion implantation process comprises the following steps:

[0052] Under a first mask, performing a first step of a first ion implantation process to form one of the functional well and the first bottom isolation well in the substrate; and

[0053] A second step of the first ion implantation process is continued under the first mask to form the other of the functional well and the first bottom isolation well in the substrate.

[0054] Optionally, in the manufacturing method of the anti-fuse structure, the ion implantation energy for forming the functional well is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the first bottom isolation well is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e13.

[0055] Optionally, in the method for manufacturing the antifuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well;

[0056] The method of forming an antifuse on the functional well comprises the following steps:

[0057] forming an anti-fuse active region in the functional well, wherein the anti-fuse active region extends from an upper surface of the functional well into the functional well; and

[0058] A conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region, so that the anti-fuse is formed by using the anti-fuse active region, the separated portion of the dielectric layer and the conductive layer.

[0059] Optionally, in the method for manufacturing the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

[0060] Optionally, in the method for manufacturing the anti-fuse structure, the anti-fuse active area is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer, and the conductive layer extends to cover a portion of the second bottom isolation well.

[0061] Optionally, in the method for manufacturing the anti-fuse structure, after forming the anti-fuse, the method for manufacturing the anti-fuse structure further includes:

[0062] A contact point is formed in the anti-fuse active region, wherein the contact point extends from a portion of the upper surface of the anti-fuse active region outside the coverage area of ​​the conductive layer to the anti-fuse active region.

[0063] The present invention also provides an anti-fuse structure, comprising:

[0064] A substrate, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are ring-shaped and enclose a portion of the substrate;

[0065] a functional well formed in the substrate enclosed by the isolation structure, wherein the functional well extends from the upper surface of the substrate into the substrate;

[0066] a first bottom isolation well formed in the substrate enclosed by the isolation structure, wherein the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types;

[0067] a second bottom isolation well formed in the substrate in a complementary manner to the functional well pattern, the second bottom isolation well extending from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well are of the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer that isolates the functional wells; and

[0068] An anti-fuse is formed on the functional well.

[0069] Optionally, in the anti-fuse structure, the second bottom isolation well covers the inner sidewall of the isolation structure.

[0070] Optionally, in the anti-fuse structure, the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

[0071] Optionally, in the anti-fuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; the anti-fuse includes:

[0072] an anti-fuse active region, the anti-fuse active region is formed in the functional well, and the anti-fuse active region extends from the upper surface of the functional well into the functional well;

[0073] a conductive layer, wherein the conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region; and

[0074] The dielectric layer is spaced apart from a spacer portion between the conductive layer and the anti-fuse active region.

[0075] Optionally, in the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

[0076] Optionally, in the anti-fuse structure, the conductive layer extends to cover a portion of the second bottom isolation well.

[0077] Optionally, in the anti-fuse structure, the anti-fuse structure further includes a contact point formed in the anti-fuse active region, and the contact point extends from the upper surface portion of the anti-fuse active region outside the coverage area of ​​the conductive layer to the anti-fuse active region.

[0078] In the manufacturing method and anti-fuse structure provided by the present invention, a first ion implantation process is performed, including forming a functional well and a first bottom isolation well in the substrate enclosed by the isolation structure, respectively, wherein the functional well extends from the upper surface of the substrate into the substrate, and the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types; a second ion implantation process is performed, including forming a side isolation well and a second bottom isolation well in the substrate complementary to the first ion implantation process pattern, respectively, wherein the side isolation well extends from the upper surface of the substrate into the substrate and covers the isolation structure to isolate adjacent functional wells, and the second bottom isolation well is located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer, thereby the anti-fuse structure can be formed through fewer mask processes, thereby reducing the manufacturing cost of the anti-fuse structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 The invention is a cross-sectional schematic diagram of a substrate provided in a method for manufacturing an anti-fuse structure.

[0080] Figure 2 is Figure 1 The cross-sectional schematic diagram of the structure obtained after performing the first ion implantation process on the structure shown.

[0081] Figure 3 is Figure 2 The cross-sectional schematic diagram of the structure obtained after performing the second ion implantation process on the structure shown.

[0082] Figure 4 is Figure 3 The cross-sectional schematic diagram of the structure obtained after the third ion implantation process is performed on the structure shown.

[0083] Figure 5 is Figure 4 The cross-sectional view of the structure after an anti-fuse is formed on the structure shown.

[0084] Figure 6It is a cross-sectional schematic diagram of a substrate provided in the method for manufacturing an anti-fuse structure according to an embodiment of the present invention.

[0085] Figure 7 is Figure 6 The cross-sectional schematic diagram of the structure obtained after performing the first ion implantation process on the structure shown.

[0086] Figure 8 is Figure 7 The cross-sectional schematic diagram of the structure obtained after performing the second ion implantation process on the structure shown.

[0087] Fig. 9 is Figure 8 The cross-sectional view of the structure after an anti-fuse is formed on the structure shown.

[0088] Fig.10 It is a cross-sectional schematic diagram of a substrate provided in the method for manufacturing an anti-fuse structure according to an embodiment of the present invention.

[0089] Fig.11 is Fig.10 The cross-sectional schematic diagram of the structure obtained after performing the first ion implantation process on the structure shown.

[0090] Fig.12 is Fig.11 The cross-sectional schematic diagram of the structure obtained after performing the second ion implantation process on the structure shown.

[0091] Fig.13 is Fig.12 The cross-sectional view of the structure after an anti-fuse is formed on the structure shown.

[0092] exist Figures 1 to 13 middle,

[0093] 100-substrate; 101-dielectric layer; 110-isolation structure; 120-bottom isolation well; 130-functional well; 140-side isolation well; 150-antifuse; 151-antifuse active area; 152-conductive layer; 160-contact point; M10-first mask; M11-second mask; M12-third mask;

[0094] 200-substrate; 201-dielectric layer; 210-isolation structure; 220-functional well; 230-first bottom isolation well; 240-side isolation well; 250-second bottom isolation well; 260-antifuse; 261-antifuse active region; 262-conductive layer; 270-contact point; M20-first mask; M21-second mask;

[0095] 300-substrate; 301-dielectric layer; 310-isolation structure; 320-functional well; 330-first bottom isolation well; 340-second bottom isolation well; 350-antifuse; 351-antifuse active area; 352-conductive layer; 360-contact point; M30-first mask; M31-second mask. DETAILED DESCRIPTION

[0096] The following is a further detailed description of the anti-fuse structure manufacturing method and the anti-fuse structure proposed in the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0097] In a method for manufacturing an anti-fuse structure, at least three mask processes are required to form the anti-fuse structure, resulting in a high manufacturing cost of the anti-fuse structure. Figures 1 to 5 ,in, Figure 1 A schematic cross-sectional view of a substrate provided in a method for manufacturing an anti-fuse structure; Figure 2 is Figure 1 A schematic cross-sectional view of a structure obtained after a first ion implantation process is performed on the structure shown; Figure 3 is Figure 2 A schematic cross-sectional view of a structure obtained after performing a second ion implantation process on the structure shown; Figure 4 is Figure 3 A schematic cross-sectional view of a structure obtained after performing a third ion implantation process on the structure shown; Figure 5 is Figure 4 The cross-sectional view of the structure after an anti-fuse is formed on the structure shown.

[0098] First, if Figure 1 As shown, a substrate 100 is provided, and a plurality of isolation structures 110 are formed in the substrate 100. The isolation structures 110 extend from the upper surface of the substrate 100 into the substrate 100. The isolation structures 110 are annular and enclose a portion of the substrate 100. Furthermore, a dielectric layer 101 is formed on the substrate 100.

[0099] Then, if Figure 2 As shown, under the first mask M10 , a first ion implantation process is performed to form a bottom isolation well 120 in the substrate 100 , wherein the bottom isolation well 120 overlaps with a portion of the isolation structure 110 away from the surface of the substrate 100 .

[0100] Then, if Figure 3As shown, under the second mask M11 , a second ion implantation process is performed to form a functional well 130 in the substrate 100 enclosed by the isolation structure 110 . The functional well 130 extends from the surface of the substrate 100 to the bottom isolation well 120 .

[0101] like Figure 4 As shown, under the third mask M12, a third ion implantation process is performed to form a side isolation well 140 in the substrate that is complementary to the pattern of the functional well 130, the side isolation well 140 covers the isolation structure 110 and the side isolation well 140 extends from the surface of the substrate 100 to the bottom isolation well 120. Here, the complementary patterns of the side isolation well 140 and the functional well 130 refer to that, in the horizontal direction, the pattern of the side isolation well 140 can be considered as an extension of the pattern of the functional well 130.

[0102] Then as Figure 5 As shown, an anti-fuse 150 is formed on the functional well 130. Specifically, an anti-fuse active region 151 is formed in the functional well 130, and the anti-fuse active region 151 extends from the upper surface of the functional well 130 to the functional well 130; and a conductive layer 152 is formed on the dielectric layer 101, and the dielectric layer 101 covers the portion under the conductive layer 152 to separate the conductive layer 152 and the anti-fuse active region 151, so that the anti-fuse active region 151, the spaced portion of the dielectric layer 101 and the conductive layer 152 are used to form the anti-fuse 150. Further, a contact point 160 can also be formed in the anti-fuse active region 151, and the contact point 160 extends from the upper surface portion of the anti-fuse active region 151 outside the coverage area of ​​the conductive layer 152 to the anti-fuse active region 151.

[0103] It can be seen that in a method for manufacturing an anti-fuse structure, three mask processes are required, namely, a first mask M10, a second mask M11 and a third mask M12, to form the anti-fuse structure, which results in a high manufacturing cost of the anti-fuse structure.

[0104] On this basis, an embodiment of the present invention provides a method for manufacturing an anti-fuse structure and an anti-fuse structure, by performing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate enclosed by the isolation structure, respectively, the functional well extending from the upper surface of the substrate into the substrate, the first bottom isolation well being located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types, by performing a second ion implantation process, including forming a side isolation well and a second bottom isolation well in the substrate complementary to the first ion implantation process pattern, respectively, the side isolation well extending from the upper surface of the substrate into the substrate and covering the isolation structure to isolate adjacent functional wells, the second bottom isolation well being located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well belong to the same ion implantation type, the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer, thereby being able to form an anti-fuse structure through fewer mask processes, thereby being able to reduce the manufacturing cost of the anti-fuse structure.

[0105] For details, please refer to Figures 6 to 9 ,in, Figure 6 is a cross-sectional schematic diagram of a substrate provided in a method for manufacturing an anti-fuse structure according to an embodiment of the present invention; Figure 7 is Figure 6 A schematic cross-sectional view of a structure obtained after a first ion implantation process is performed on the structure shown; Figure 8 is Figure 7 A schematic cross-sectional view of a structure obtained after performing a second ion implantation process on the structure shown; Fig. 9 is Figure 8 The cross-sectional view of the structure after an anti-fuse is formed on the structure shown.

[0106] like Figure 6 As shown, first, a substrate 200 is provided, and a plurality of isolation structures 210 are formed in the substrate 200. The isolation structures 210 extend from the upper surface of the substrate 200 to the substrate 200. The isolation structures 210 are annular and enclose a portion of the substrate 200. The isolation structures 210 may be made of silicon oxide or silicon nitride.

[0107] Furthermore, a dielectric layer 201 is formed on the substrate 200. Preferably, the thickness of the dielectric layer 201 is less than 40 angstroms, for example, the thickness of the dielectric layer 201 may be 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms or 30 angstroms, etc. The material of the dielectric layer 201 may be selected from one of silicon oxide and silicon nitride.

[0108] Then, if Figure 7As shown, a first ion implantation process is performed, including forming a functional well 220 and a first bottom isolation well 230 in the substrate 200 enclosed by the isolation structure 210, respectively. The functional well 220 extends from the upper surface of the substrate 200 to the substrate 200, and the first bottom isolation well 230 is located below the functional well 220 in the same pattern, wherein the functional well 220 and the first bottom isolation well 230 belong to different ion implantation types. Here, the first bottom isolation well 230 is connected to the bottom of the functional well 220, and the first bottom isolation well 230 is located below the functional well 220 in the same pattern, which means that in the vertical direction, the pattern of the first bottom isolation well 230 can be considered as an extension of the pattern of the functional well 220. Further, the functional well 220 can be a P-type ion implantation, and accordingly, the first bottom isolation well 230 can be an N-type ion implantation; or, the functional well 220 can be an N-type ion implantation, and accordingly, the first bottom isolation well 230 can be a P-type ion implantation.

[0109] Specifically, performing the first ion implantation process includes the following steps: performing the first step of the first ion implantation process under the first mask M20 to form one of the functional well 220 and the first bottom isolation well 230 in the substrate 200; and continuing to perform the second step of the first ion implantation process under the first mask M20 to form the other of the functional well 220 and the first bottom isolation well 230 in the substrate 200. Here, the functional well 220 and the first bottom isolation well 230 can be formed by using the first mask M20. Further, in the specific formation process of the functional well 220 and the first bottom isolation well 230, the functional well 220 can be formed first and then the first bottom isolation well 230, or the first bottom isolation well 230 can be formed first and then the functional well 220.

[0110] The ion implantation energy for forming the functional well 220 is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the first bottom isolation well 230 is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e13.

[0111] Then as Figure 8As shown, a second ion implantation process is performed, including forming a side isolation well 240 and a second bottom isolation well 250 in the substrate 200 complementary to the first ion implantation process pattern, wherein the side isolation well 240 extends from the upper surface of the substrate 200 into the substrate 200 and covers the isolation structure 210 to isolate the adjacent functional well 220, and the second bottom isolation well 250 is located below the side isolation well 240 in the same pattern, wherein the first bottom isolation well 230, the side isolation well 240 and the second bottom isolation well 250 belong to the same ion implantation type, and the first bottom isolation well 230 and the second bottom isolation well 250 are connected to form a bottom isolation well combination layer.

[0112] Here, the patterns of the side isolation well 240 and the functional well 220 are complementary. Specifically, in the horizontal direction, the pattern of the side isolation well 240 can be considered as an extension of the pattern of the functional well 220. The patterns of the second bottom isolation well 250 and the first bottom isolation well 230 are complementary. Specifically, in the horizontal direction, the pattern of the second bottom isolation well 250 can be considered as an extension of the pattern of the first bottom isolation well 230. Further, the second bottom isolation well 250 is located below the side isolation well 240, which means that in the vertical direction, the pattern of the second bottom isolation well 250 can be considered as an extension of the pattern of the side isolation well 240.

[0113] That is, in the embodiment of the present application, the functional well 220 and the side isolation well 240 have the same depth in the substrate 200, and the first bottom isolation well 230 and the second bottom isolation well 250 have the same depth in the substrate 200. Specifically, the upper surfaces of the functional well 220 and the side isolation well 240 are at the same horizontal plane (here, the surface of the substrate 200), and the lower surfaces of the functional well 220 and the side isolation well 240 are at the same horizontal plane; the upper surfaces of the first bottom isolation well 230 and the second bottom isolation well 250 are at the same horizontal plane (here, they are connected to the bottom of the functional well 220 and the side isolation well 240, respectively), and the lower surfaces of the first bottom isolation well 230 and the second bottom isolation well 250 are at the same horizontal plane.

[0114] In an embodiment of the present application, the injected ions of the first bottom isolation well 230, the side isolation well 240 and the second bottom isolation well 250 may all be P-type ions, in which case the injected ions of the functional well 220 are N-type ions; or, the injected ions of the first bottom isolation well 230, the side isolation well 240 and the second bottom isolation well 250 may all be N-type ions, in which case the injected ions of the functional well 220 are P-type ions.

[0115] Specifically, performing the second ion implantation process includes the following steps: performing the first step of the second ion implantation process under the second mask M21 to form one of the side isolation well 240 and the second bottom isolation well 250 in the substrate 200; and continuing to perform the second step of the second ion implantation process under the second mask M21 to form the other of the side isolation well 240 and the second bottom isolation well 250 in the substrate 200. Here, the side isolation well 240 and the second bottom isolation well 250 can be formed by using the second mask M21. Further, in the specific formation process of the side isolation well 240 and the second bottom isolation well 250, the side isolation well 240 can be formed first and then the second bottom isolation well 250 can be formed, or the second bottom isolation well 250 can be formed first and then the side isolation well 240 can be formed.

[0116] The ion implantation energy for forming the side isolation well 240 is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the second bottom isolation well 250 is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e13.

[0117] It can be seen that in the embodiment of the present application, only two mask processes are needed to form the functional well 220 and the bowl-shaped isolation well (here including the side isolation well 240, the first bottom isolation well 230 and the second bottom isolation well 250) that isolates the functional well 220, thereby using fewer mask processes and reducing the manufacturing cost of the anti-fuse structure.

[0118] Please refer to Fig. 9 , forming an anti-fuse 260 on the functional well 220. Specifically, it includes: forming an anti-fuse active region 261 in the functional well 220, wherein the anti-fuse active region 261 extends from the upper surface of the functional well 220 to the functional well 220; and forming a conductive layer 262 on the dielectric layer 201, wherein the dielectric layer 201 covers a portion under the conductive layer 262 to space the conductive layer 262 and the anti-fuse active region 261, so as to form the anti-fuse 260 using the anti-fuse active region 261, the spaced portion of the dielectric layer 201 and the conductive layer 262.

[0119] Specifically, the anti-fuse active region 261 can be formed by performing an ion implantation process on the functional well 220; the conductive layer 262 is formed by depositing polysilicon on the dielectric layer 201, and the conductive layer 262 extends to cover a portion of the side isolation well 240. Specifically, in the embodiment of the present application, the conductive layer 262 is located on the dielectric layer 201, and the conductive layer 262 covers a portion of the anti-fuse active region 261 and extends to cover a portion of the side isolation well 240.

[0120] Please continue to refer to Fig. 9 The method for manufacturing the anti-fuse structure further includes: forming a contact point 270 in the anti-fuse active region 261, wherein the contact point 270 extends from the upper surface portion of the anti-fuse active region 261 outside the coverage area of ​​the conductive layer 262 to the anti-fuse active region 261. The contact point 270 may be formed by performing an ion implantation process on the anti-fuse active region 261.

[0121] Accordingly, the embodiment of the present invention further provides an anti-fuse structure formed by the manufacturing method of the anti-fuse structure, which can be referred to accordingly. Fig. 9 Specifically, the anti-fuse structure includes:

[0122] A substrate 200, wherein a plurality of isolation structures 210 are formed in the substrate 200, wherein the isolation structures 210 extend from the upper surface of the substrate 200 into the substrate 200, and the isolation structures 210 are ring-shaped and enclose a portion of the substrate 200;

[0123] a functional well 220 formed in the substrate 200 enclosed by the isolation structure 210, wherein the functional well 220 extends from the upper surface of the substrate 200 into the substrate 200;

[0124] a first bottom isolation well 230 formed in the substrate 200 enclosed by the isolation structure 210, wherein the first bottom isolation well 230 is located below the functional well 220 in the same pattern, wherein the functional well 220 and the first bottom isolation well 230 are of different ion implantation types;

[0125] A side isolation well 240 is formed in the substrate 200 in a complementary manner to the functional well 220. The side isolation well 240 extends from the upper surface of the substrate 200 into the substrate 200 and covers the isolation structure 210 to isolate the adjacent functional well 220.

[0126] a second bottom isolation well 250 formed in the substrate 200, wherein the second bottom isolation well 250 is located below the side isolation well 240 in the same pattern, wherein the first bottom isolation well 230, the side isolation well 240 and the second bottom isolation well 250 are of the same ion implantation type, and the first bottom isolation well 230 and the second bottom isolation well 250 are connected to form a bottom isolation well combination layer; and

[0127] An anti-fuse 260 is formed on the functional well 220 .

[0128] Specifically, the functional well 220 and the side isolation well 240 have the same depth in the substrate 200 , and the first bottom isolation well 230 and the second bottom isolation well 250 have the same depth in the substrate 200 .

[0129] Further, a dielectric layer 201 is formed on the substrate 200, and the dielectric layer 201 covers the functional well 220; the anti-fuse 260 includes: an anti-fuse active region 261, the anti-fuse active region 261 is formed in the functional well 220, and the anti-fuse active region 261 extends from the upper surface of the functional well 220 to the functional well 220; a conductive layer 262 is formed on the dielectric layer 201, and the dielectric layer 201 covers the portion under the conductive layer 262 to separate the conductive layer 262 and the anti-fuse active region 261; and the dielectric layer 201 is spaced between the conductive layer 262 and the anti-fuse active region 261. Preferably, the thickness of the dielectric layer 201 is less than 40 angstroms. Further, the dielectric layer 201 extends to cover the portion of the side isolation well 240, and the conductive layer 262 extends to cover the portion of the side isolation well 240. The anti-fuse structure further includes a contact point 270 formed in the anti-fuse active region 261 . The contact point 270 extends from the upper surface portion of the anti-fuse active region 261 outside the coverage area of ​​the conductive layer 262 to the anti-fuse active region 261 .

[0130] An embodiment of the present invention also provides a method for manufacturing an anti-fuse structure and an anti-fuse structure, by performing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate circled by the isolation structure, respectively, the functional well extending from the upper surface of the substrate into the substrate, the first bottom isolation well being located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types; by performing a second ion implantation process, including forming a second bottom isolation well in the substrate complementary to the first ion implantation pattern, the second bottom isolation well extending from the upper surface of the substrate into the substrate to isolate adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well belong to the same ion implantation type, the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer that isolates the functional wells, thereby enabling the anti-fuse structure to be formed through fewer mask processes, thereby enabling the manufacturing cost of the anti-fuse structure to be reduced.

[0131] For details, please refer to Figures 10 to 13 ,in, Fig.10 is a cross-sectional schematic diagram of a substrate provided in a method for manufacturing an anti-fuse structure according to an embodiment of the present invention; Fig.11 is Fig.10 A schematic cross-sectional view of a structure obtained after a first ion implantation process is performed on the structure shown; Fig.12 is Fig.11 A schematic cross-sectional view of a structure obtained after performing a second ion implantation process on the structure shown; Fig.13 is Fig.12 The cross-sectional view of the structure after an anti-fuse is formed on the structure shown.

[0132] First, if Fig.10 As shown, a substrate 300 is provided, and a plurality of isolation structures 310 are formed in the substrate 300. The isolation structures 310 extend from the upper surface of the substrate 300 into the substrate 300. The isolation structures 310 are annular and enclose a portion of the substrate 300. The isolation structures 310 may be made of silicon oxide or silicon nitride.

[0133] Furthermore, a dielectric layer 301 is formed on the substrate 300. Preferably, the thickness of the dielectric layer 301 is less than 40 angstroms, for example, the thickness of the dielectric layer 301 may be 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms or 30 angstroms, etc. The material of the dielectric layer 301 may be selected from one of silicon oxide and silicon nitride.

[0134] Then, if Fig.11As shown, a first ion implantation process is performed, including forming a functional well 320 and a first bottom isolation well 330 in the substrate 300 enclosed by the isolation structure 310, respectively. The functional well 320 extends from the upper surface of the substrate 300 to the substrate 300, and the first bottom isolation well 330 is located below the functional well 320 in the same pattern, wherein the functional well 320 and the first bottom isolation well 330 belong to different ion implantation types. Here, the first bottom isolation well 330 is connected to the bottom of the functional well 320, and the first bottom isolation well 330 is located below the functional well 320 in the same pattern, which means that in the vertical direction, the pattern of the first bottom isolation well 330 can be considered as an extension of the pattern of the functional well 320. Further, the functional well 320 can be a P-type ion implantation, and accordingly, the first bottom isolation well 330 can be an N-type ion implantation; or, the functional well 320 can be an N-type ion implantation, and accordingly, the first bottom isolation well 330 can be a P-type ion implantation.

[0135] Specifically, performing the first ion implantation process includes the following steps: performing the first step of the first ion implantation process under the first mask M30 to form one of the functional well 320 and the first bottom isolation well 330 in the substrate 300; and continuing to perform the second step of the first ion implantation process under the first mask M30 to form the other of the functional well 320 and the first bottom isolation well 330 in the substrate 300. Here, the functional well 320 and the first bottom isolation well 330 can be formed by using the first mask M30. Further, in the specific formation process of the functional well 320 and the first bottom isolation well 330, the functional well 320 can be formed first and then the first bottom isolation well 330, or the first bottom isolation well 330 can be formed first and then the functional well 320.

[0136] The ion implantation energy for forming the functional well 320 is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the first bottom isolation well 330 is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e13.

[0137] Then as Fig.12As shown, a second ion implantation process is performed, including forming a second bottom isolation well 340 in the substrate 300 complementary to the first ion implantation process pattern, wherein the second bottom isolation well 340 extends from the upper surface of the substrate 300 into the substrate 300 to isolate the adjacent functional well 320, wherein the first bottom isolation well 330 and the second bottom isolation well 340 belong to the same ion implantation type, and the first bottom isolation well 330 and the second bottom isolation well 340 are connected to form a bottom isolation well combination layer that isolates the functional wells.

[0138] Specifically, the second ion implantation process may be performed under the second mask M31 to form the second bottom isolation well 340. The ion implantation energy of the second ion implantation process may be between 70 KeV and 200 KeV, and the ion implantation dose may be between 1e12 and 5e13.

[0139] Further, the second bottom isolation well 340 may cover the inner sidewall of the isolation structure 310, that is, the second bottom isolation well 340 covers the sidewall of the isolation structure 310 close to the functional well 320. Here, the pattern of the second bottom isolation well 340 is complementary to (a combination of) the patterns of the functional well 320 and the first bottom isolation well 330. Specifically, in the horizontal direction, the pattern of the portion of the second bottom isolation well 340 close to the upper surface of the substrate 300 can be considered as an extension of the pattern of the functional well 320; the pattern of the portion of the second bottom isolation well 340 far from the upper surface of the substrate 300 can be considered as an extension of the pattern of the first bottom isolation well 330.

[0140] In the embodiment of the present application, the thickness of the second bottom isolation well 340 in the vertical direction is greater than the thickness of the first bottom isolation well 330. Further, the first bottom isolation well 330 and the second bottom isolation well 340 have the same depth in the substrate 300, that is, the lower surface of the first bottom isolation well 330 and the lower surface of the second bottom isolation well 340 are on the same horizontal plane.

[0141] In an embodiment of the present application, the injected ions of the first bottom isolation well 330 and the second bottom isolation well 340 may both be P-type ions, in which case the injected ions of the functional well 320 are N-type ions; or, the injected ions of the first bottom isolation well 330 and the second bottom isolation well 340 may both be N-type ions, in which case the injected ions of the functional well 320 are P-type ions.

[0142] It can be seen that in the embodiment of the present application, only two mask processes are needed to form the functional well 320 and the bowl-shaped isolation well (here including the first bottom isolation well 330 and the second bottom isolation well 340) that isolates the functional well 320, thereby using fewer mask processes and reducing the manufacturing cost of the anti-fuse structure.

[0143] like Fig.13 As shown, an anti-fuse 350 is formed on the functional well 320. Specifically, it includes: forming an anti-fuse active region 351 in the functional well 320, wherein the anti-fuse active region 351 extends from the upper surface of the functional well 320 to the functional well 320; and forming a conductive layer 352 on the dielectric layer 301, wherein the dielectric layer 301 covers a portion under the conductive layer 352 to space the conductive layer 352 and the anti-fuse active region 351, so that the anti-fuse 350 is formed by using the anti-fuse active region 351, the spaced portion of the dielectric layer 301 and the conductive layer 352.

[0144] Specifically, the anti-fuse active region 351 can be formed by performing an ion implantation process on the functional well 320; the conductive layer 352 is formed by depositing polysilicon on the dielectric layer 301, and the conductive layer 352 extends to cover a portion of the second bottom isolation well 340. Specifically, in the embodiment of the present application, the conductive layer 352 is located on the dielectric layer 301, and the conductive layer 352 covers a portion of the anti-fuse active region 351 and extends to cover a portion of the second bottom isolation well 340.

[0145] Please continue to refer to Fig.13 The method for manufacturing the anti-fuse structure further includes: forming a contact point 360 in the anti-fuse active region 351, wherein the contact point 360 extends from the upper surface portion of the anti-fuse active region 351 outside the coverage area of ​​the conductive layer 352 to the anti-fuse active region 351. The contact point 360 may be formed by performing an ion implantation process on the anti-fuse active region 351.

[0146] Accordingly, the embodiment of the present invention further provides an anti-fuse structure formed by the manufacturing method of the anti-fuse structure, which can be referred to accordingly. Fig.13 Specifically, the anti-fuse structure includes:

[0147] A substrate 300, wherein a plurality of isolation structures 310 are formed in the substrate 300, wherein the isolation structures 310 extend from the upper surface of the substrate 300 into the substrate 300, and the isolation structures 310 are ring-shaped and enclose a portion of the substrate 300;

[0148] A functional well 320 is formed in the substrate 300 enclosed by the isolation structure 310, and the functional well 320 extends from the upper surface of the substrate 300 into the substrate 300;

[0149] a first bottom isolation well 330 formed in the substrate 300 enclosed by the isolation structure 310, wherein the first bottom isolation well 330 is located below the functional well 320 in the same pattern, wherein the functional well 320 and the first bottom isolation well 330 are of different ion implantation types;

[0150] a second bottom isolation well 340 formed in the substrate 300 in a complementary pattern to the functional well 320, the second bottom isolation well 340 extending from the upper surface of the substrate 300 into the substrate 300 to isolate the adjacent functional well 320, wherein the first bottom isolation well 330 and the second bottom isolation well 340 are of the same ion implantation type, and the first bottom isolation well 330 and the second bottom isolation well 340 are connected to form a bottom isolation well combination layer that isolates the functional wells; and

[0151] An anti-fuse 350 is formed on the functional well 320 .

[0152] The second bottom isolation well 340 covers the inner sidewall of the isolation structure 310. The first bottom isolation well 330 and the second bottom isolation well 340 have the same depth in the substrate 300.

[0153] Further, a dielectric layer 301 is formed on the substrate 300, and the dielectric layer 301 covers the functional well 320; the anti-fuse 350 includes: an anti-fuse active region 351, the anti-fuse active region 351 is formed in the functional well 320, and the anti-fuse active region 351 extends from the upper surface of the functional well 320 to the functional well 320; a conductive layer 352 is formed on the dielectric layer 301, and the dielectric layer 301 covers the portion under the conductive layer 352 to separate the conductive layer 352 and the anti-fuse active region 351; and the dielectric layer 301 is spaced between the conductive layer 352 and the anti-fuse active region 351. Preferably, the thickness of the dielectric layer 301 is less than 40 angstroms. The conductive layer 352 extends to cover a portion of the second bottom isolation well 340. In the embodiment of the present application, the anti-fuse structure further includes a contact point 360 formed in the anti-fuse active region 351 , and the contact point 360 extends from the upper surface portion of the anti-fuse active region 351 outside the coverage area of ​​the conductive layer 352 to the anti-fuse active region 351 .

[0154] In summary, it can be seen that in the anti-fuse structure manufacturing method and the anti-fuse structure provided by the present invention, the anti-fuse structure can be formed by using fewer mask processes, thereby reducing the manufacturing cost of the anti-fuse structure.

[0155] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing an anti-fuse structure, characterized in that: include: A substrate is provided, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are ring-shaped and enclose a portion of the substrate; Performing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate enclosed by the isolation structure, respectively, wherein the functional well extends from the upper surface of the substrate into the substrate, and the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types; Performing a second ion implantation process, including forming a side isolation well and a second bottom isolation well in the substrate complementary to the first ion implantation process pattern, the side isolation well extending from the upper surface of the substrate into the substrate and covering the isolation structure to isolate the adjacent functional wells, the second bottom isolation well being located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well are of the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and An anti-fuse is formed on the functional well.

2. The method for manufacturing an anti-fuse structure according to claim 1, wherein: The first ion implantation process includes the following steps: Under a first mask, performing a first step of a first ion implantation process to form one of the functional well and the first bottom isolation well in the substrate; and A second step of the first ion implantation process is continued under the first mask to form the other of the functional well and the first bottom isolation well in the substrate.

3. The method for manufacturing an anti-fuse structure according to claim 2, wherein: The ion implantation energy for forming the functional well is between 70 KeV and 150 KeV, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the first bottom isolation well is between 80 KeV and 200 KeV, and the ion implantation dose is between 1e12 and 5e13.

4. The method for manufacturing an anti-fuse structure according to claim 1, wherein: The second ion implantation process includes the following steps: Under a second mask, performing a first step of a second ion implantation process to form one of the side isolation well and the second bottom isolation well in the substrate; and A second step of a second ion implantation process is continued under the second mask to form the other of the side isolation well and the second bottom isolation well in the substrate.

5. The method for manufacturing an anti-fuse structure according to claim 4, wherein: The ion implantation energy for forming the side isolation well is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the second bottom isolation well is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e13.

6. The method for manufacturing an anti-fuse structure according to claim 1, wherein: The functional well and the side isolation well have the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

7. The method for manufacturing an anti-fuse structure according to any one of claims 1 to 6, characterized in that: A dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; The method of forming an antifuse on the functional well comprises the following steps: forming an anti-fuse active region in the functional well, wherein the anti-fuse active region extends from an upper surface of the functional well into the functional well; and A conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region, so that the anti-fuse is formed by using the anti-fuse active region, the separated portion of the dielectric layer and the conductive layer.

8. The method for manufacturing an anti-fuse structure according to claim 7, wherein: The thickness of the dielectric layer is less than 40 angstroms.

9. The method for manufacturing an anti-fuse structure according to claim 7, wherein: The anti-fuse active region is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer, and the conductive layer extends to cover a portion of the side isolation well.

10. The method for manufacturing an anti-fuse structure according to claim 7, wherein: After forming the anti-fuse, the method for manufacturing the anti-fuse structure further includes: A contact point is formed in the anti-fuse active region, wherein the contact point extends from a portion of the upper surface of the anti-fuse active region outside the coverage area of ​​the conductive layer to the anti-fuse active region.

11. An anti-fuse structure, characterized in that: include: A substrate, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, the isolation structures are annular and enclose a portion of the substrate, and the isolation structures are made of silicon oxide or silicon nitride; a functional well formed in the substrate enclosed by the isolation structure, wherein the functional well extends from the upper surface of the substrate into the substrate; a first bottom isolation well formed in the substrate enclosed by the isolation structure, wherein the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types; A side isolation well is formed in the substrate in a complementary manner to the functional well pattern, the side isolation well extends from the upper surface of the substrate into the substrate and covers the isolation structure to isolate the adjacent functional wells; a second bottom isolation well formed in the substrate, the second bottom isolation well being located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well are of the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and An anti-fuse is formed on the functional well.

12. The anti-fuse structure according to claim 11, wherein: The functional well and the side isolation well have the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

13. The anti-fuse structure according to claim 11, wherein: A dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; the antifuse comprises: an anti-fuse active region, the anti-fuse active region is formed in the functional well, and the anti-fuse active region extends from the upper surface of the functional well into the functional well; a conductive layer, wherein the conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region; and The dielectric layer is spaced apart from a spacer portion between the conductive layer and the anti-fuse active region.

14. The anti-fuse structure according to claim 13, wherein: The thickness of the dielectric layer is less than 40 angstroms.

15. The anti-fuse structure according to claim 13, wherein: The conductive layer extends to cover a portion of the side isolation well.

16. The anti-fuse structure according to any one of claims 13 to 15, characterized in that: The anti-fuse structure further includes a contact point formed in the anti-fuse active region, wherein the contact point extends from a portion of an upper surface of the anti-fuse active region outside a coverage area of ​​the conductive layer to the anti-fuse active region.

17. A method for manufacturing an anti-fuse structure, characterized in that: include: A substrate is provided, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are ring-shaped and enclose a portion of the substrate; Performing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate enclosed by the isolation structure, respectively, wherein the functional well extends from the upper surface of the substrate into the substrate, and the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types; Performing a second ion implantation process, including forming a second bottom isolation well in the substrate complementary to the first ion implantation process pattern, wherein the second bottom isolation well extends from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer that isolates the functional wells; and An anti-fuse is formed on the functional well.

18. The method for manufacturing an anti-fuse structure according to claim 17, wherein: The second bottom isolation well covers the inner sidewall of the isolation structure.

19. The method for manufacturing an anti-fuse structure according to claim 17, wherein: The first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

20. The method for manufacturing an anti-fuse structure according to claim 17, wherein: The first ion implantation process includes the following steps: Under a first mask, performing a first step of a first ion implantation process to form one of the functional well and the first bottom isolation well in the substrate; and A second step of the first ion implantation process is continued under the first mask to form the other of the functional well and the first bottom isolation well in the substrate.

21. The method for manufacturing an anti-fuse structure according to claim 20, wherein: The ion implantation energy for forming the functional well is between 70 KeV and 150 KeV, and the ion implantation dose is between 1e12 and 5e13; the ion implantation energy for forming the first bottom isolation well is between 80 KeV and 200 KeV, and the ion implantation dose is between 1e12 and 5e13.

22. The method for manufacturing an anti-fuse structure according to any one of claims 17 to 21, characterized in that: A dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; The method of forming an antifuse on the functional well comprises the following steps: forming an anti-fuse active region in the functional well, wherein the anti-fuse active region extends from an upper surface of the functional well into the functional well; and A conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region, so that the anti-fuse is formed by using the anti-fuse active region, the separated portion of the dielectric layer and the conductive layer.

23. The method for manufacturing an anti-fuse structure according to claim 22, wherein: The thickness of the dielectric layer is less than 40 angstroms.

24. The method for manufacturing an anti-fuse structure according to claim 22, wherein: The anti-fuse active region is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer, and the conductive layer extends to cover a portion of the second bottom isolation well.

25. The method for manufacturing an anti-fuse structure according to claim 22, wherein: After forming the anti-fuse, the method for manufacturing the anti-fuse structure further includes: A contact point is formed in the anti-fuse active region, wherein the contact point extends from a portion of the upper surface of the anti-fuse active region outside the coverage area of ​​the conductive layer to the anti-fuse active region.

26. An anti-fuse structure, characterized in that: include: A substrate, wherein a plurality of isolation structures are formed in the substrate, wherein the isolation structures extend from the upper surface of the substrate into the substrate, the isolation structures are annular and enclose a portion of the substrate, and the isolation structures are made of silicon oxide or silicon nitride; a functional well formed in the substrate enclosed by the isolation structure, wherein the functional well extends from the upper surface of the substrate into the substrate; a first bottom isolation well formed in the substrate enclosed by the isolation structure, wherein the first bottom isolation well is located below the functional well in the same pattern, wherein the functional well and the first bottom isolation well belong to different ion implantation types; a second bottom isolation well formed in the substrate in a complementary manner to the functional well pattern, the second bottom isolation well extending from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well are of the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer that isolates the functional wells; and An anti-fuse is formed on the functional well.

27. The anti-fuse structure according to claim 26, wherein: The second bottom isolation well covers the inner sidewall of the isolation structure.

28. The anti-fuse structure according to claim 26, wherein: The first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

29. The anti-fuse structure according to claim 26, wherein: A dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; the antifuse comprises: an anti-fuse active region, the anti-fuse active region is formed in the functional well, and the anti-fuse active region extends from the upper surface of the functional well into the functional well; a conductive layer, wherein the conductive layer is formed on the dielectric layer, and the dielectric layer covers a portion below the conductive layer to separate the conductive layer and the anti-fuse active region; and The dielectric layer is spaced apart from a spacer portion between the conductive layer and the anti-fuse active region.

30. The anti-fuse structure according to claim 29, wherein: The thickness of the dielectric layer is less than 40 angstroms.

31. The anti-fuse structure according to claim 29, wherein: The conductive layer extends to cover a portion of the second bottom isolation well.

32. The anti-fuse structure according to any one of claims 29 to 31, wherein: The anti-fuse structure further includes a contact point formed in the anti-fuse active region, wherein the contact point extends from a portion of an upper surface of the anti-fuse active region outside a coverage area of ​​the conductive layer to the anti-fuse active region.

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