A readout circuit with pixel mismatch correction function

Abstract

The present invention relates to a readout circuit with a pixel mismatch correction function, which constructs a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104, and an integral amplifier circuit module 105. Through the connection relationship between the circuit modules, a final uncooled photoelectric focal plane array readout circuit is constructed, which can reduce the influence of pixel mismatch, has the advantages of low circuit noise and strong adaptability, can realize the pixel mismatch correction function, and improve the accuracy of photoelectric detection.

Description

Technical Field

[0001] The invention relates to a readout circuit with a pixel mismatch correction function, belonging to the field of uncooled infrared focal plane array readout circuits. Background Art

[0002] Infrared detection refers to a technology that uses photoelectric and other means to detect the infrared radiation signal of an object and convert it into an electrical signal. The microbolometer type uncooled infrared focal plane detector uses thermosensitive materials to make microbolometer pixels. Under the condition that the infrared radiation produces a temperature rise change, its own equivalent resistance changes, and then responds to infrared detection. The microbolometer pixel is prepared using MEMS technology. However, due to undesirable and unavoidable factors, the resistance of the microbolometer pixel may vary greatly, resulting in pixel mismatch effects, and then circuit noise and non-uniformity problems appear, which directly affects the accuracy of the detected signal in the actual operation of the infrared detector. In the worst case, this non-uniformity will cause the readout circuit to fail. Therefore, the detection accuracy of the prior art microbolometer type uncooled infrared focal plane detector needs to be further improved. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a readout circuit with a pixel mismatch correction function, which can reduce the influence of pixel mismatch, has the advantages of low circuit noise and strong adaptability, can realize the pixel mismatch correction function, and improve the accuracy of photoelectric detection.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a readout circuit with pixel mismatch correction function, which is used to realize the infrared radiation signal reading of the pixel, including a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104, and an integral amplifier circuit module 105;

[0005] The bias circuit module 101 includes a dummy pixel branch circuit, and a detection pixel and a blind pixel branch circuit, which are used to bias the detection pixel and the blind pixel;

[0006] The subtraction circuit module 102 is respectively connected to the output end of the dummy pixel branch circuit and the output end of the detection pixel and blind pixel branch circuits, and is used to perform a subtraction operation on the outputs of the two branch circuits;

[0007] The first current mirror DAC module 103 is connected to the output end of the subtraction circuit module 102 and scales the output current of the subtraction circuit module 102 according to a preset ratio;

[0008] The second current mirror DAC module 104 is connected to the output end of the first current mirror DAC module 103 and the output end of the dummy pixel branch circuit in the bias circuit module 101, and scales the connected current according to a preset ratio;

[0009] The integral amplifier circuit module 105 is connected to the output end of the second current mirror DAC module 104 and the output end of the detection pixel and blind pixel branch circuit in the bias circuit module 101, integrates and amplifies the connected current, and outputs it to realize the infrared radiation signal reading of the pixel.

[0010] As a preferred technical solution of the present invention: the detection pixel and blind pixel branch circuit in the bias circuit module 101 includes the detection pixel R s and blind pixel R b , where the detection pixel R s One end of the blind pixel R b One end of each is connected to the power supply, and the detection pixel R s The other end of is connected to the source end of the first MOS transistor MP1, the gate end of the first MOS transistor MP1 is connected to the gate end of the second MOS transistor MP2, the gate end of the third MOS transistor MP3, and the gate end of the fourth MOS transistor MP4 respectively, the drain end of the first MOS transistor MP1 constitutes the second output end of the detection pixel and the blind pixel branch circuit, and the drain end of the first MOS transistor MP1 is connected to the source end of the second MOS transistor MP2, and the drain end of the second MOS transistor MP2 is grounded; the blind pixel R b The other end of the transistor is connected to the source end of the third MOS transistor MP3, the drain end of the third MOS transistor MP3 constitutes the first output end of the detection pixel and the blind pixel branch circuit, and the drain end of the third MOS transistor MP3 is connected to the source end of the fourth MOS transistor MP4, and the drain end of the fourth MOS transistor MP4 is grounded.

[0011] As a preferred technical solution of the present invention: the dummy pixel branch circuit in the bias circuit module 101 includes a first reference pixel R b1 and the second reference pixel R b2 , where the first reference pixel R b1 One end of the second reference pixel R b2 One end of each of the two reference pixels R b1The other end of the fifth MOS transistor MP5 is connected to the source end of the fifth MOS transistor MP5, the gate end of the fifth MOS transistor MP5 is connected to the gate end of the sixth MOS transistor MP6, the gate end of the seventh MOS transistor MP7, and the gate end of the eighth MOS transistor MP8 respectively, the drain end of the fifth MOS transistor MP5 constitutes the first output end of the dummy pixel branch circuit, and the drain end of the fifth MOS transistor MP5 is connected to the source end of the sixth MOS transistor MP6, and the drain end of the sixth MOS transistor MP6 is grounded; the second reference pixel R b2 The other end of the MOS transistor MP7 is connected to the source end of the seventh MOS transistor MP7, the drain end of the seventh MOS transistor MP7 constitutes the second output end of the dummy pixel branch circuit, and the drain end of the seventh MOS transistor MP7 is connected to the source end of the eighth MOS transistor MP8, and the drain end of the eighth MOS transistor MP8 is grounded.

[0012] As a preferred technical solution of the present invention: the subtraction circuit module 102 includes an operational amplifier A1, wherein the positive input end of the operational amplifier A1 is respectively connected to one end of the third semiconductor resistor R3 and one end of the fifth semiconductor resistor R5, the other end of the fifth semiconductor resistor R5 is grounded, the other end of the third semiconductor resistor R3 is respectively connected to the first output end of the detection pixel and blind pixel branch circuit, and one end of the first semiconductor resistor R1, and the other end of the first semiconductor resistor R1 is grounded; the negative input end of the operational amplifier A1 is respectively connected to one end of the fourth semiconductor resistor R4 and one end of the sixth semiconductor resistor R6, the other end of the fourth semiconductor resistor R4 is respectively connected to the first output end of the dummy pixel branch circuit, and one end of the second semiconductor resistor R2, and the other end of the second semiconductor resistor R2 is grounded; the output end of the operational amplifier A1 constitutes the output end of the subtraction circuit module 102, and the output end of the operational amplifier A1 is respectively connected to the other end of the sixth semiconductor resistor R6 and one end of the seventh semiconductor resistor R7, and the other end of the seventh semiconductor resistor R7 is grounded.

[0013] As a preferred technical solution of the present invention: the second current mirror DAC module 104 includes an eleventh MOS transistor MP11 and a twelfth MOS transistor MP12, wherein the drain end of the eleventh MOS transistor MP11 is connected to the gate end thereof and constitutes the input end of the second current mirror DAC module 104, and the input end is connected to the second output end of the dummy pixel branch circuit and the output end of the first current mirror DAC module 103, and at the same time, the gate end of the eleventh MOS transistor MP11 is connected to the gate end of the twelfth MOS transistor MP12, the source end of the eleventh MOS transistor MP11 is connected in series with the eighth semiconductor resistor R8 and then grounded; the source end of the twelfth MOS transistor MP12 is connected in series with the ninth semiconductor resistor R9 and then grounded, and the drain end of the twelfth MOS transistor MP12 constitutes the output end of the second current mirror DAC module 104.

[0014] As a preferred technical solution of the present invention: the integral amplifier circuit module 105 includes an operational amplifier A2, wherein the positive input terminal of the operational amplifier A2 is connected to a preset correction voltage V ref The negative input terminal of the operational amplifier A2 is connected in series with the tenth semiconductor resistor R 10 After that, the input end of the integral amplifier circuit module 105 is connected to the second output end of the detection pixel and the blind pixel branch circuit, and the output end of the second current mirror DAC module 104. At the same time, the negative input end of the operational amplifier A2 is connected to the capacitor C int One end of the control switch S rst One end of the capacitor C int The other end of the control switch S rst The other end of and the output end of the operational amplifier A2 are connected to form the output end of the integral amplifier circuit module 105.

[0015] As a preferred technical solution of the present invention: the first current mirror DAC module 103 includes a ninth MOS transistor MP9 and a tenth MOS transistor MP10, wherein the source end of the ninth MOS transistor MP9 and the source end of the tenth MOS transistor MP10 are respectively connected to the power supply, the drain end of the ninth MOS transistor MP9 is connected to the gate end thereof and constitutes the input end of the first current mirror DAC module 103, and the gate end of the ninth MOS transistor MP9 is connected to the gate end of the tenth MOS transistor MP10, and the drain end of the tenth MOS transistor MP10 constitutes the output end of the first current mirror DAC module 103.

[0016] The readout circuit with pixel mismatch correction function described in the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0017] The readout circuit with pixel mismatch correction function designed in the present invention constructs a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104, and an integral amplifier circuit module 105. Through the connection relationship between the circuit modules, a final uncooled photoelectric focal plane array readout circuit is constructed, which can reduce the influence of pixel mismatch, has the advantages of low circuit noise and strong adaptability, can realize the pixel mismatch correction function, and improve the accuracy of photoelectric detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a readout circuit with a pixel mismatch correction function designed by the present invention. DETAILED DESCRIPTION

[0019] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0020] The present invention designs a readout circuit with pixel mismatch correction function, which is used to realize the reading of infrared radiation signals of pixels. Figure 1 As shown, it specifically includes a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104, and an integral amplifier circuit module 105.

[0021] The bias circuit module 101 includes a dummy pixel branch circuit, and a detection pixel and a blind pixel branch circuit, which are used to bias the detection pixel and the blind pixel;

[0022] The subtraction circuit module 102 is respectively connected to the output end of the dummy pixel branch circuit and the output end of the detection pixel and blind pixel branch circuits, and is used to perform a subtraction operation on the outputs of the two branch circuits;

[0023] The first current mirror DAC module 103 is connected to the output end of the subtraction circuit module 102 and scales the output current of the subtraction circuit module 102 according to a preset ratio;

[0024] The second current mirror DAC module 104 is connected to the output end of the first current mirror DAC module 103 and the output end of the dummy pixel branch circuit in the bias circuit module 101, and scales the connected current according to a preset ratio;

[0025] The integral amplifier circuit module 105 is connected to the output end of the second current mirror DAC module 104 and the output end of the detection pixel and blind pixel branch circuit in the bias circuit module 101, integrates and amplifies the connected current, and outputs it to realize the infrared radiation signal reading of the pixel.

[0026] Based on the connection between the bias circuit module 101, the subtraction circuit module 102, the first current mirror DAC module 103, the second current mirror DAC module 104, and the integral amplifier circuit module 105, the detailed circuit structure of each circuit module is further specifically designed, wherein the detection pixel and blind pixel branch circuit in the bias circuit module 101 includes the detection pixel R s and blind pixel R b , where the detection pixel R s One end of the blind pixel R b One end of each is connected to the power supply, and the detection pixel R s The other end of is connected to the source end of the first MOS transistor MP1, the gate end of the first MOS transistor MP1 is connected to the gate end of the second MOS transistor MP2, the gate end of the third MOS transistor MP3, and the gate end of the fourth MOS transistor MP4 respectively, the drain end of the first MOS transistor MP1 constitutes the second output end of the detection pixel and the blind pixel branch circuit, and the drain end of the first MOS transistor MP1 is connected to the source end of the second MOS transistor MP2, and the drain end of the second MOS transistor MP2 is grounded; the blind pixel R b The other end of the transistor is connected to the source end of the third MOS transistor MP3, the drain end of the third MOS transistor MP3 constitutes the first output end of the detection pixel and the blind pixel branch circuit, and the drain end of the third MOS transistor MP3 is connected to the source end of the fourth MOS transistor MP4, and the drain end of the fourth MOS transistor MP4 is grounded.

[0027] The dummy pixel branch circuit in the bias circuit module 101 includes a first reference pixel R b1 and the second reference pixel R b2 , where the first reference pixel R b1 One end of the second reference pixel R b2 One end of each of the two reference pixels R b1 The other end of the fifth MOS transistor MP5 is connected to the source end of the fifth MOS transistor MP5, the gate end of the fifth MOS transistor MP5 is connected to the gate end of the sixth MOS transistor MP6, the gate end of the seventh MOS transistor MP7, and the gate end of the eighth MOS transistor MP8 respectively, the drain end of the fifth MOS transistor MP5 constitutes the first output end of the dummy pixel branch circuit, and the drain end of the fifth MOS transistor MP5 is connected to the source end of the sixth MOS transistor MP6, and the drain end of the sixth MOS transistor MP6 is grounded; the second reference pixel R b2 The other end of the MOS transistor MP7 is connected to the source end of the seventh MOS transistor MP7, the drain end of the seventh MOS transistor MP7 constitutes the second output end of the dummy pixel branch circuit, and the drain end of the seventh MOS transistor MP7 is connected to the source end of the eighth MOS transistor MP8, and the drain end of the eighth MOS transistor MP8 is grounded.

[0028] The subtraction circuit module 102 includes an operational amplifier A1, wherein the positive input terminal of the operational amplifier A1 is respectively connected to one end of the third semiconductor resistor R3 and one end of the fifth semiconductor resistor R5, the other end of the fifth semiconductor resistor R5 is grounded, the other end of the third semiconductor resistor R3 is respectively connected to the first output end of the detection pixel and blind pixel branch circuit, and one end of the first semiconductor resistor R1, and the other end of the first semiconductor resistor R1 is grounded; the negative input terminal of the operational amplifier A1 is respectively connected to one end of the fourth semiconductor resistor R4 and one end of the sixth semiconductor resistor R6, the other end of the fourth semiconductor resistor R4 is respectively connected to the first output end of the dummy pixel branch circuit, and one end of the second semiconductor resistor R2, and the other end of the second semiconductor resistor R2 is grounded; the output terminal of the operational amplifier A1 constitutes the output terminal of the subtraction circuit module 102, and the output terminal of the operational amplifier A1 is respectively connected to the other end of the sixth semiconductor resistor R6 and one end of the seventh semiconductor resistor R7, and the other end of the seventh semiconductor resistor R7 is grounded.

[0029] The first current mirror DAC module 103 includes a ninth MOS transistor MP9 and a tenth MOS transistor MP10, wherein the source end of the ninth MOS transistor MP9 and the source end of the tenth MOS transistor MP10 are respectively connected to the power supply, the drain end of the ninth MOS transistor MP9 is connected to the gate end thereof and constitutes the input end of the first current mirror DAC module 103, and the gate end of the ninth MOS transistor MP9 is connected to the gate end of the tenth MOS transistor MP10, and the drain end of the tenth MOS transistor MP10 constitutes the output end of the first current mirror DAC module 103.

[0030] The second current mirror DAC module 104 includes an eleventh MOS transistor MP11 and a twelfth MOS transistor MP12, wherein the drain end of the eleventh MOS transistor MP11 is connected to the gate end thereof and constitutes the input end of the second current mirror DAC module 104, and the input end is connected to the second output end of the dummy pixel branch circuit and the output end of the first current mirror DAC module 103. Meanwhile, the gate end of the eleventh MOS transistor MP11 is connected to the gate end of the twelfth MOS transistor MP12, the source end of the eleventh MOS transistor MP11 is connected in series with the eighth semiconductor resistor R8 and then grounded; the source end of the twelfth MOS transistor MP12 is connected in series with the ninth semiconductor resistor R9 and then grounded, and the drain end of the twelfth MOS transistor MP12 constitutes the output end of the second current mirror DAC module 104.

[0031] The integral amplifier circuit module 105 includes an operational amplifier A2, wherein the positive input terminal of the operational amplifier A2 is connected to a preset correction voltage V refThe negative input terminal of the operational amplifier A2 is connected in series with the tenth semiconductor resistor R 10 After that, the input end of the integral amplifier circuit module 105 is connected to the second output end of the detection pixel and the blind pixel branch circuit, and the output end of the second current mirror DAC module 104. At the same time, the negative input end of the operational amplifier A2 is connected to the capacitor C int One end of the control switch S rst One end of the capacitor C int The other end of the control switch S rst The other end of and the output end of the operational amplifier A2 are connected to form the output end of the integral amplifier circuit module 105.

[0032] The readout circuit with pixel mismatch correction function designed by the present invention is applied in practice, such as Figure 1 As shown in the figure, it is assumed that at the initial temperature, due to the MEMS process error, when the detection pixel R s Resistance R' s With blind pixel R b Resistance R' b The ratio is:

[0033]

[0034] That is, the detection pixel R is obtained s Resistance R' s With blind pixel R b Resistance R' b The ratio is (1+k):1. In practical applications, the DC bias current I DC , Current change ΔI due to self-heating effect SH , due to infrared radiation heat, the current changes ΔI IR :

[0035]

[0036] Among them, V bias is the pixel bias voltage, R0 is the initial resistance value of the pixel, α is the resistance temperature coefficient, C th , R th is the thermal constant of the pixel bridge leg, P IR It is the infrared radiation energy absorbed by the detection pixel.

[0037] That is Figure 1 As shown, after the blind pixel R b The current I b =I DC +ΔI SH ; After detecting pixel R s Current

[0038] Then the subtraction circuit module 102 first converts the current I DC and I b The voltage is converted into voltage on the semiconductor resistor R2 and the semiconductor resistor R1 respectively, and then the difference voltage is obtained through the subtraction circuit, and finally the difference voltage is converted into current ΔI through the semiconductor resistor R7. SH , and is input to the first current mirror DAC module 103, and the first current mirror DAC module 103 is used to detect the current ΔI SH , scaled by 1:(1+k), to obtain the mirror current ΔI SH / (1+k), and then transmitted to the second current mirror DAC module 104.

[0039] In the second current mirror DAC module 104, the current I DC and mirror current ΔI SH / (1+k) and then the total current I DC +ΔI SH / (1+k), scaled by 1:(1+k), to obtain the mirror current I DC / (1+k)+ΔI SH / (1+k) 2 , and continues to be transmitted to the integration amplifier circuit module 105.

[0040] In the integral amplifier circuit module 105, for the current I s and mirror current I DC / (1+k)+ΔI SH / (1+k) 2 The difference is made and the integral amplification of the small difference current is realized, and finally the output voltage V with pixel mismatch correction is obtained. out .

[0041] The readout circuit with pixel mismatch correction function designed by the above technical solution constructs a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104, and an integral amplifier circuit module 105. Through the connection relationship between the various circuit modules, a final uncooled photoelectric focal plane array readout circuit is constructed, which can reduce the influence of pixel mismatch, has the advantages of low circuit noise and strong adaptability, can realize the pixel mismatch correction function, and improve the accuracy of photoelectric detection.

[0042] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A readout circuit with pixel mismatch correction function, used to realize the reading of infrared radiation signals of pixels, characterized in that: It comprises a bias circuit module (101), a subtraction circuit module (102), a first current mirror DAC module (103), a second current mirror DAC module (104), and an integral amplifier circuit module (105); The bias circuit module (101) comprises a dummy pixel branch circuit, and a detection pixel and blind pixel branch circuit, and is used to bias the detection pixel and the blind pixel; The subtraction circuit module (102) is respectively connected to the output end of the dummy pixel branch circuit and the output end of the detection pixel and blind pixel branch circuits, and is used to perform a subtraction operation on the outputs of the two branch circuits; The first current mirror DAC module (103) is connected to the output end of the subtraction circuit module (102) and performs scaling according to a preset ratio of the output current of the subtraction circuit module (102); The second current mirror DAC module (104) is connected to the output end of the first current mirror DAC module (103) and the output end of the dummy pixel branch circuit in the bias circuit module (101), and scales the connected current according to a preset ratio; The integral amplifier circuit module (105) is connected to the output end of the second current mirror DAC module (104) and the output end of the detection pixel and blind pixel branch circuit in the bias circuit module (101), integrates and amplifies the connected current, and outputs it, so as to realize the reading of the infrared radiation signal of the pixel; The detection pixel and blind pixel branch circuit in the bias circuit module (101) includes a detection pixel R s and blind pixel R b , where the detection pixel R s One end of the blind pixel R b One end of each is connected to the power supply, and the detection pixel R s The other end of is connected to the source end of the first MOS transistor MP1, the gate end of the first MOS transistor MP1 is connected to the gate end of the second MOS transistor MP2, the gate end of the third MOS transistor MP3, and the gate end of the fourth MOS transistor MP4 respectively, the drain end of the first MOS transistor MP1 constitutes the second output end of the detection pixel and the blind pixel branch circuit, and the drain end of the first MOS transistor MP1 is connected to the source end of the second MOS transistor MP2, and the drain end of the second MOS transistor MP2 is grounded; the blind pixel R b The other end of the third MOS transistor MP3 is connected to the source end of the third MOS transistor MP3, the drain end of the third MOS transistor MP3 constitutes the first output end of the detection pixel and the blind pixel branch circuit, and the drain end of the third MOS transistor MP3 is connected to the source end of the fourth MOS transistor MP4, and the drain end of the fourth MOS transistor MP4 is grounded; The first current mirror DAC module (103) comprises a ninth MOS transistor MP9 and a tenth MOS transistor MP10, wherein the source end of the ninth MOS transistor MP9 and the source end of the tenth MOS transistor MP10 are respectively connected to a power supply, the drain end of the ninth MOS transistor MP9 is connected to its gate end and constitutes the input end of the first current mirror DAC module (103), and the gate end of the ninth MOS transistor MP9 is connected to the gate end of the tenth MOS transistor MP10, and the drain end of the tenth MOS transistor MP10 constitutes the output end of the first current mirror DAC module (103).

2. A readout circuit with pixel mismatch correction function according to claim 1, characterized in that: The dummy pixel branch circuit in the bias circuit module (101) includes a first reference pixel R b1 and the second reference pixel R b2 , where the first reference pixel R b1 One end of the second reference pixel R b2 One end of each of the two reference pixels R b1 The other end of the fifth MOS transistor MP5 is connected to the source end of the fifth MOS transistor MP5, the gate end of the fifth MOS transistor MP5 is connected to the gate end of the sixth MOS transistor MP6, the gate end of the seventh MOS transistor MP7, and the gate end of the eighth MOS transistor MP8 respectively, the drain end of the fifth MOS transistor MP5 constitutes the first output end of the dummy pixel branch circuit, and the drain end of the fifth MOS transistor MP5 is connected to the source end of the sixth MOS transistor MP6, and the drain end of the sixth MOS transistor MP6 is grounded; the second reference pixel R b2 The other end of the MOS transistor MP7 is connected to the source end of the seventh MOS transistor MP7, the drain end of the seventh MOS transistor MP7 constitutes the second output end of the dummy pixel branch circuit, and the drain end of the seventh MOS transistor MP7 is connected to the source end of the eighth MOS transistor MP8, and the drain end of the eighth MOS transistor MP8 is grounded.

3. The readout circuit with pixel mismatch correction function according to claim 2, characterized in that: The subtraction circuit module (102) comprises an operational amplifier A1, wherein the positive input end of the operational amplifier A1 is respectively connected to one end of the third semiconductor resistor R3 and one end of the fifth semiconductor resistor R5, the other end of the fifth semiconductor resistor R5 is grounded, the other end of the third semiconductor resistor R3 is respectively connected to the first output end of the detection pixel and blind pixel branch circuit and one end of the first semiconductor resistor R1, the other end of the first semiconductor resistor R1 is grounded; the negative input end of the operational amplifier A1 is respectively connected to one end of the fourth semiconductor resistor R4 and one end of the sixth semiconductor resistor R6, the other end of the fourth semiconductor resistor R4 is respectively connected to the first output end of the dummy pixel branch circuit and one end of the second semiconductor resistor R2, the other end of the second semiconductor resistor R2 is grounded; the output end of the operational amplifier A1 constitutes the output end of the subtraction circuit module (102), and the output end of the operational amplifier A1 is respectively connected to the other end of the sixth semiconductor resistor R6 and one end of the seventh semiconductor resistor R7, the other end of the seventh semiconductor resistor R7 is grounded.

4. A readout circuit with pixel mismatch correction function according to claim 2 or 3, characterized in that: The second current mirror DAC module (104) comprises an eleventh MOS transistor MP11 and a twelfth MOS transistor MP12, wherein the drain end of the eleventh MOS transistor MP11 is connected to its gate end and constitutes the input end of the second current mirror DAC module (104), and the input end is connected to the second output end of the dummy pixel branch circuit and the output end of the first current mirror DAC module (103); at the same time, the gate end of the eleventh MOS transistor MP11 is connected to the gate end of the twelfth MOS transistor MP12; the source end of the eleventh MOS transistor MP11 is connected in series with the eighth semiconductor resistor R8 and then grounded; the source end of the twelfth MOS transistor MP12 is connected in series with the ninth semiconductor resistor R9 and then grounded, and the drain end of the twelfth MOS transistor MP12 constitutes the output end of the second current mirror DAC module (104).

5. The readout circuit with pixel mismatch correction function according to claim 4, characterized in that: The integral amplifier circuit module (105) comprises an operational amplifier A2, wherein the positive input terminal of the operational amplifier A2 is connected to a preset correction voltage V ref The negative input terminal of the operational amplifier A2 is connected in series with the tenth semiconductor resistor R 10 After that, the input end of the integral amplifier circuit module (105) is formed, and the input end is connected to the second output end of the detection pixel and blind pixel branch circuit, and the output end of the second current mirror DAC module (104), and the negative input end of the operational amplifier A2 is connected to the capacitor C int One end of the control switch S rst One end of the capacitor C int The other end of the control switch S rst The other end of the amplifier and the output end of the operational amplifier A2 are connected to form the output end of the integral amplifier circuit module (105).

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