A low-capacitance low-clamping voltage transient voltage suppressor and a manufacturing method thereof

Abstract

The present invention relates to a low-capacitance low-clamping voltage transient voltage suppressor and a manufacturing method thereof. The low-capacitance low-clamping voltage transient voltage suppressor, based on the TVS tube structure, comprises an N-type silicon substrate N-sub silicon wafer, a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power supply metal layer VCC, and a TVS device of a signal terminal IO1 and IO2 metal, characterized in that: at least the first to fourth P-type wells PW1-4 are included on the N-type silicon substrate N-sub or the grown N-type epitaxial layer N-epi, and the TVS tube is composed of a bipolar transistor composed of N+ / PW2 / PW3 / N+. The TVS tube of the low-capacitance low-clamping voltage transient voltage suppressor structure of the present invention is a bipolar transistor effect, which not only has the advantages of low breakdown voltage and trigger voltage, and faster protection response; it also has the characteristics of smaller on-resistance and clamping voltage, and stronger protection capability for subsequent integrated circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor protection devices, and in particular to a low-capacitance and low-clamping voltage transient voltage suppressor and a manufacturing method thereof, which are used in the field of protection device design and manufacturing for high-speed signal ports. Background Art

[0002] Transient voltage suppressor (TVS for short) is a clamping overvoltage protection device that can fix the surge voltage at a relatively low voltage level in a very short time, thereby protecting the subsequent integrated circuits from the impact of excessive electrostatic discharge or surge voltage and avoiding damage.

[0003] TVS devices are mainly used in various interface circuits. For example, there are a large number of TVS protection devices in mobile phones, tablets, televisions, and computer hosts. Usually, the IO end of the TVS device is connected to the IO end of the circuit, and the ground end is connected to the ground in the circuit, that is, the TVS device and the protected chip are in parallel. When static electricity is released or surge voltage enters from the IO end of the circuit, the TVS device will be triggered to conduct first, and the current will be released through the TVS device to the ground, clamping the voltage at a lower level, thereby effectively protecting the subsequent integrated circuits.

[0004] With the rapid development of science and technology, integrated circuits are constantly developing in the direction of low voltage, low power consumption and high-speed transmission, and higher performance requirements are also put forward for the corresponding TVS protection devices. It is required that the clamping voltage of the TVS should be as low as possible and the capacitance should be as small as possible. It is usually used in high-speed ports such as HDMI3.0 / 3.1 and USB3.1. The capacitance is required to be less than 0.5pF. Larger capacitance will cause abnormalities such as packet loss during the transmission of high-frequency signals. Summary of the invention

[0005] To solve the above problems, the object of the present invention is to provide a low-capacitance and low-clamping voltage transient voltage suppressor.

[0006] Another object of the present invention is to provide a method for manufacturing the low-capacitance and low-clamping voltage transient voltage suppressor.

[0007] The object of the present invention is achieved through the following scheme: A TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure, comprising an N-type silicon substrate N-sub silicon wafer, a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and a signal terminal IO1 and IO2 metal TVS device, characterized in that: at least the first to fourth P-type wells PW1-4 are included on the N-type silicon substrate N-sub or the grown N-type epitaxial layer N-epi, wherein:

[0008] The first and fourth P-type wells PW1, 4 have the same structure as the lightly doped P-type wells, and the wells include a P+ region and an N+ region;

[0009] The second P-type well PW2 includes a heavily doped N+ region; and

[0010] The third P-type well PW3 sequentially includes an N+ region, a P+ region and a lightly doped N+ region, and the width of the P+ region in the third P-type well PW3 is smaller than the width of the N+ region;

[0011] The TVS tube is a bipolar transistor composed of N+ / PW2 / PW3 / N+, and its base region second P-type well PW2 and third P-type well PW3 are short-circuited with the collector N+ of the ground terminal through P+ lead; when static electricity is released or surge occurs, since the second P-type well PW2 is heavily doped, the N+ / PW2 breakdown voltage is relatively low. After the N+ / PW2 junction is broken down, the current passes through the second P-type well PW2 to the third P-type well PW3, and then flows out from the P+ terminal to the ground terminal; at the same time, because the third P-type well PW3 is lightly doped, its higher resistance makes the voltage difference generated by the current from the third P-type well PW3 to P+ easily greater than 0.7V. At this time, the bipolar transistor effect occurs, and the current can not only flow out from the P+ terminal, but also from the N+ of the ground terminal, showing a significant negative resistance characteristic, that is, the current-voltage curve has a significant snapback;

[0012] A P-type buried layer (P-BL) is added under the second P-type well PW2 and the third P-type well PW3, which, when matched with the N-type substrate, can form a wider depletion region, greatly reducing the parasitic capacitance of the bottom junction of the TVS tube, and significantly reducing the capacitance of the device as a whole, which is more than 10% smaller than the capacitance of the device with the traditional structure;

[0013] The P+ region is an ultra-shallow junction or has the same junction depth as the N+ region. When the TVS tube is turned on, the path from the second and third P-type wells PW2 and PW3 to the base region P+ is lengthened. At the same time, the width of the base region P+ is set to be narrower, which is smaller than the N+ on its two sides. Under the combined effect of the two, the resistance on the current path is greater. Therefore, only a small current is needed to reach the base region P+, which can trigger the bipolar transistor effect, and the negative resistance snapback occurs in advance, further reducing the clamping voltage.

[0014] The two diodes formed are: the first type of diode from the IO terminal to the VCC terminal is formed by P+ / N-epi / N+, N-epi is a high-resistance epitaxial, and the P+ and N-epi form a wider space charge region to reduce the capacitance of this diode; the second type of diode from the ground terminal (Gnd) to the signal terminal IO is formed by P+ / PW1 / N+ and / or P+ / PW4 / N+. The first P-type well PW1 and the fourth P-type well PW4 are lightly doped, so a wider space charge region is formed between N+ and the first P-type well PW1 and the fourth P-type well PW4 to reduce the capacitance of this diode. The overall capacitance of the device is also reduced.

[0015] Furthermore, the implanted element of the first and fourth P-type wells PW1, 4 is boron, and the implanted dose is 5E11~1E13CM -2 The injection energy is 60~100KeV; the injection element of the second P-type well PW2 is boron, and the injection dose is 1E14~9E14CM -2 The injection energy is 60~100KeV; the injection element of the third P-type well PW3 is boron, and the injection dose is 1E12~1E14CM -2 , the injection energy is 60~100KeV.

[0016] Furthermore, the N-type epitaxial growth is doped with phosphorus or arsenic impurities, and its resistivity is 50~300Ω*CM, and the epitaxial thickness is 3~8μm; P+ is an ultra-shallow junction, the implanted element is boron, and the implantation dose is 1E15~8E15CM -2 , the implantation energy is 40~80KeV; the N+ region is heavily doped, the implantation element is phosphorus or arsenic, and the implantation dose is 2E15~1.2E16 CM -2 , the injection energy is 80~150KeV; in the diode formed by P+ / N-epi / N+ from the IO end to the VCC end, a smaller junction area is formed by P+ and N-epi, and the diode has a smaller capacitance, which can reduce the capacitance of the entire device.

[0017] Based on the above scheme, the third P-type well PW3 and the second P-type well PW2 are configured in a surrounding shape or an interdigitated shape to further increase the current path area and improve the surge peak current to obtain better electrostatic discharge and surge protection capabilities.

[0018] On the basis of the above scheme, the present invention provides a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure, wherein an N-type epitaxial layer and a P-type buried layer P-BL are grown on an N-type silicon substrate silicon wafer, and the surface of the N-type epitaxial layer is sequentially provided from left to right with a first P-type well PW1 including a P+ region and an N+ region, a P+ region and an N+ region on the surface of the N-type epitaxial layer on one side, a second P-type well PW2 with an N+ region, a third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence, a fourth P-type well PW4 including a P+ region and an N+ region, a P+ region and an N+ region on the surface of the N-type epitaxial layer on the other side, and the bottoms of the second P-type well PW2 and the third P-type well PW3 are connected to the P-type buried layer P-BL; the P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to a metal ground terminal; The N+ region on the surface of the N-type epitaxial layer and the N+ region of the second P-type well PW2 are connected to the power metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2.

[0019] Wherein, the resistivity of the N-substrate is 200~300Ω*CM.

[0020] Furthermore, the P-type buried layer (P-BL) has a thickness of 200-500Å, and ions are implanted with boron or boron difluoride, with an implantation energy of 60-100 KeV and an implantation dose of 5E11-5E12CM. -2 .

[0021] Preferably, the junction depth of the P+ region is shallower than the junction depth of the N+ region.

[0022] Based on the above scheme, no N-type epitaxial layer is grown on the N-type substrate, and the P+ region and N+ region originally arranged on the N-type epitaxial layer are directly arranged on the surface of the N-type substrate to form the P+ region and N+ region on the surface of the N-type substrate.

[0023] Furthermore, the P+ region and N+ region in the N-type substrate are arranged in the N-type well NW, and the shapes of the second and third P-type wells PW2 and 3 are adjusted so that the third P-type well PW3 surrounds the second P-type well PW2.

[0024] Furthermore, a deep P-region Deep P- is added at the bottom of the third P-type well PW3.

[0025] On the basis of the above solution, a P+ buried layer P+BL may be added between the upper surface of the P-type buried layer P-BL and the bottom of the second and third P-type wells PW2 and 3.

[0026] On the basis of the above scheme, the present invention provides another TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure, wherein an N-type epitaxial layer and a P-type buried layer (P-BL) are grown on the N-type silicon substrate silicon wafer, and from left to right on the surface of the N-type epitaxial layer are a first P-type well PW1 including a P+ region and an N+ region, a P+ region and an N+ region on the surface of the N-type epitaxial layer on one side, a third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence, a second P-type well PW2 with an N+ region, a fifth P-type well PW5 including an N+ region, a P+ region and an N+ region in sequence, and a third P-type well PW6 including an N+ region, a P+ region and an N+ region in sequence. Four P-type wells PW4, the P+ region and N+ region on the surface of the N-type epitaxial layer on the other side, and the bottom of the third, second and fifth P-type wells PW3, 2 and 5 are connected to the P-type buried layer P-BL; the P+ region in the first P-type well PW1, the third P-type well PW3 and the fifth P-type well PW5 are connected to the metal ground terminal; the N+ region on the surface of the N-type epitaxial layer and the N+ region of the second P-type well PW2 are connected to the power supply metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2.

[0027] In order to further reduce the capacitance, a lightly doped P-type well PW region is added around the P+ region on the surface of the N-type epitaxial layer. The diode from the IO end to VCC is formed by P+ / lightly doped PW / N-epi / N+, and the lightly doped PW and the N-type epitaxial layer N-epi form a wider space charge region.

[0028] The present invention provides a method for manufacturing a TVS tube according to the above-mentioned low-capacitance and low-clamping-voltage transient voltage suppressor structure, comprising the following steps:

[0029] Step 1: Use an N-type substrate silicon wafer and grow a thin oxide layer on its upper surface. Through photolithography, ion implantation, and thermal process advancement, a P-type buried layer P-BL is formed. The thin oxide layer on the surface is then removed by wet etching.

[0030] Step 2: growing an N-type epitaxial layer on the surface of the silicon wafer;

[0031] Step 3: On the epitaxial surface of the silicon wafer, perform photolithography and ion implantation on PWell1 and 4, photolithography and ion implantation on the second P-type well PW2, and photolithography and ion implantation on PWell3 in sequence, wherein the positions of the second and third P-type wells PWell2 and 3 correspond to the position of the P-type buried layer P-BL, and the first and fourth P-type wells PW1 and 4 have the same structure;

[0032] Step 4: Place the silicon wafer into a high-temperature furnace tube, and push the first to fourth P-type wells PW1-4 simultaneously, so that the second P-type well PW2 and the third P-type well PW3 are connected to the P-type buried layer P-BL;

[0033] Step 5: Perform N+ selective implantation on the above surface by photolithography and ion implantation process, the N+ implantation element is phosphorus or arsenic, and then enter the furnace tube for annealing to repair the implantation damage;

[0034] Step 6: Perform P+ selective implantation on the above surface by photolithography and ion implantation process. The P+ implantation element is boron. The spacing between P+ and N+ in PW3 is set to 0~5μm. The implantation energy is less than that of N+ implantation. Then, perform rapid thermal annealing to repair the implantation damage.

[0035] Step 7: depositing a dielectric on the surface to form a dielectric layer, and then performing photolithography and etching to form contact holes, wherein the dielectric layer is an oxide layer, borophosphorus glass, or a multi-layer insulating film composite layer;

[0036] Step 8: Perform metal deposition, and then form a front metal layer through photolithography and etching. The metal layer is a pure aluminum layer, an aluminum silicon compound layer or a metal composite layer structure.

[0037] Preferably, in step 1, the thickness of the thin oxide layer is 200-500Å, and boron or boron difluoride is ion-implanted with an injection energy of 60-100 KeV and an injection dose of 5E11-5E12CM. -2 The injection angle is 7 degrees, and the thermal process is promoted into the high-temperature furnace tube with a temperature of 950℃~1100℃ and a time of 60~120 minutes.

[0038] Preferably, in step 2, the N-type epitaxial growth is doped with phosphorus or arsenic impurities, and its resistivity is 50-300Ω*CM, and the epitaxial thickness is 3-8μm.

[0039] Preferably, in step 3, the first and fourth P-type wells PW1, 4 are implanted with boron, and the implantation dose is 5E11~1E13CM -2 The injection energy is 60~100KeV, and the injection angle is 7 degrees. The second P-type well PW2 is injected with boron, and the injection dose is 1E14~9E14CM -2 The injection energy is 60~100KeV, and the injection angle is 7 degrees. The third P-type well PW3 is injected with boron, and the injection dose is 1E12~1E14CM -2 The injection energy is 60~100KeV and the injection angle is 7 degrees.

[0040] Preferably, in step 4, the furnace tube temperature is 1000-1150° C., and the time is 60-120 minutes.

[0041] Preferably, in step 5, the N+ implanted element is phosphorus or arsenic, and the implantation dose is 2E15~1.2E16 CM -2 The implantation energy is 80~150KeV, the annealing process temperature is 850℃~950℃, and the time is 30~60 minutes.

[0042] Preferably, in step 6, the P+ implant element is boron, and the implant dose is 1E15 to 8E15CM -2 The injection energy is 40-80 KeV; the rapid thermal annealing temperature is 950-1050°C and the time is 10-30 seconds, so that the P+ junction depth is significantly shallower than the N+ junction depth.

[0043] Furthermore, in step 6, the distance between the P+ region and the N+ region in the third P-type well PW3 is 0 μm, and the P+ width in the third P-type well PW3 is set to 1-5 μm.

[0044] Furthermore, in step 6, the P+ width in the third P-type well PW3 is set to 0.5-1.5 μm.

[0045] Preferably, in step 8, the metal composite layer structure is a three-layer structure of titanium, titanium nitride, and aluminum silicon copper from bottom to top, wherein the thickness of titanium is 200~500Å, the thickness of titanium nitride is 400~1000Å, and the thickness of aluminum silicon copper is 2~4μm.

[0046] The advantages of the present invention are: the TVS tube of the low-capacitance and low-clamping voltage transient voltage suppressor structure of the present invention is a bipolar transistor effect, which not only has the advantages of low breakdown voltage and trigger voltage, and faster protection response; it also has the characteristics of smaller on-resistance and clamping voltage, and has stronger protection capability for subsequent integrated circuits. The present invention also provides a manufacturing method of the above-mentioned TVS tube, which has a high yield rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic cross-sectional view of embodiment 1 of the present invention;

[0048] Figure 2 Step 1: Schematic diagram of a silicon wafer structure in which a P-type buried layer (P-BL) is formed on an N-type substrate silicon wafer;

[0049] Figure 3 Step 2: Schematic diagram of silicon wafer structure for growing N-type epitaxial layer;

[0050] Figure 4 , step 3 is a schematic diagram of the silicon wafer structure in which PWell1-4 is implanted on the surface of the N-type epitaxial layer;

[0051] Figure 5, step 4, putting the silicon wafer of step 3 into the high temperature furnace tube, and pushing PWell1-4 at the same time, so that PWell2, PWell3 and P-BL area are connected to the silicon wafer structure schematic diagram;

[0052] Figure 6 Schematic diagram of the silicon wafer structure in which N+ selective implantation is performed on the silicon wafer in step 5 to form an N+ junction;

[0053] Figure 7 Step 6 is a schematic diagram of the silicon wafer structure in which P+ is selectively implanted on the silicon wafer surface in step 5, and a schematic diagram of the silicon wafer of the P+ junction is formed between the P+ junction and the N+ deep junction of PWell3 by implanting P+ in PWell1, the N-type epitaxial surface N+, and PWell4;

[0054] Figure 8 Step 7: deposit dielectric on the upper surface of the silicon wafer in step 6, then perform photolithography and etching to form contact holes. The dielectric layer can be an oxide layer, borophosphorus glass, or a multi-layer insulating film composite layer;

[0055] Fig. 9 It is a schematic diagram of the structure of the P+ and N+ junctions of Example 2 with equal depths;

[0056] Fig.10 , is a schematic diagram of the structure of Example 3 in which the P+N+ junctions are of equal depth and no epitaxial layer is grown;

[0057] Fig.11 , is a schematic diagram of the structure of Example 4, in which no epitaxial growth is performed, the P+ and N+ in the N-type substrate are arranged in the NWell, the PWell2 is arranged in the PWell3, and the P+ and N+ junctions are of equal depth, and no epitaxial layer is grown;

[0058] Fig.12 , is a schematic diagram of the structure of Example 5, in which no epitaxial growth is performed, the P+ and N+ in the N-type substrate are arranged in the NWell, the PWell2 is in the PWell3, and a deep P-junction is connected below the PWell3;

[0059] Fig.13 , is a schematic diagram of the structure of Example 6. Different from Example 1, a P+ type buried layer (P+BL) and a P- type buried layer (P-BL) are sequentially provided at the bottom of PWell2-3;

[0060] Fig.14 , is a schematic diagram of the structure of Example 7, a PWell5 having the same structure as PWell3 is added to the left side of PWell2, and the bottoms of PWell5, 2 and 3 are connected to the P-type buried layer (P-BL);

[0061] Fig.15, is a schematic diagram of the structure of Example 8, a PWell5 having the same structure as PWell3 is added on the left side of PWell2, the P+ on the N-type epitaxial is PWell6, 7, and the bottom of PWell5, 2 and 3 is connected to the P-type buried layer (P-BL);

[0062] Fig.16 Circuit schematic diagram;

[0063] Description of the numbers in the figure:

[0064] N-sub——N-type silicon substrate; N-epi——N-type epitaxial layer;

[0065] P-BL——P-type buried layer;

[0066] Deep P-——deep P-area;

[0067] PW——P-type well;

[0068] PW1-7——first to seventh P-type wells;

[0069] NW——N-type well;

[0070] NW1, 2——first and second N-type wells;

[0071] Gnd——ground metal layer, VCC——power supply metal layer;

[0072] D1-4——Diodes 1 to 4;

[0073] 1——Dielectric layer; 2——Metal layer. DETAILED DESCRIPTION

[0074] Example 1

[0075] A TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure, such as Figure 1 As shown, a TVS device including a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and signal terminals IO1 and IO2 metals is grown on an N-type silicon substrate N-sub silicon wafer on the basis of the existing TVS device structure. In this example, an N-type epitaxial layer N-epi and a P-type buried layer P-BL are grown on an N-type silicon substrate N-sub silicon wafer.

[0076] From left to right on the surface of the N-type epitaxial layer are:

[0077] A first P-type well PW1 including a P+ region and an N+ region;

[0078] P+ region and N+ region on the surface of the N-type epitaxial layer on one side;

[0079] A second P-type well PW2 having an N+ region;

[0080] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence;

[0081] A fourth P-type well PW4 including a P+ region and an N+ region;

[0082] P+ region and N+ region on the surface of the N-type epitaxial layer on the other side;

[0083] The P-type buried layer P-BL is connected at the bottom of the second P-type well PW2 and the third P-type well PW3; the P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to the ground metal layer Gnd; the N+ region on the surface of the N-type epitaxial layer N-epi and the N+ region of the second P-type well PW2 are connected to the power supply metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2.

[0084] In this embodiment, the first and fourth P-type wells PW1, 4 are lightly doped P-type wells with the same structure, and the wells include a P+ region and an N+ region;

[0085] The second P-type well PW2 includes a heavily doped N+ region; and

[0086] The third P-type well PW3 sequentially includes an N+ region, a P+ region and a lightly doped N+ region, and the width of the P+ region in the third P-type well PW3 is smaller than the width of the N+ region;

[0087] The TVS tube is a bipolar transistor composed of N+ / PW2 / PW3 / N+, and its base region second P-type well PW2 and third P-type well PW3 are short-circuited with the collector N+ connected to the ground metal layer Gnd through the P+ lead; when static electricity is released or a surge is generated, since the second P-type well PW2 is heavily doped, the N+ / PW2 breakdown voltage is relatively low. After the N+ / PW2 junction is broken down, the current passes through the second P-type well PW2 to the third P-type well PW3, and then flows out from the P+ end to the ground end; at the same time, because the third P-type well PW3 is lightly doped, its higher resistance makes the voltage difference generated by the current from the third P-type well PW3 to P+ easily greater than 0.7V. At this time, the bipolar transistor effect is generated, and the current can not only flow out from the P+ end, but also from the collector N+ at the ground end, showing a significant negative resistance characteristic, that is, the current-voltage curve has a significant snapback;

[0088] A P-type buried layer P-BL is added under the second P-type well PW2 and the third P-type well PW3, and is matched with the N-type substrate N-sub to form a wider depletion region, which greatly reduces the parasitic capacitance of the bottom junction of the TVS tube, and the overall capacitance of the device is significantly reduced, which is more than 10% smaller than the capacitance of the device with a traditional structure;

[0089] The P+ region is an ultra-shallow junction. When the TVS tube is turned on, the path from the second and third P-type wells PW2 and PW3 to the base region P+ is lengthened. At the same time, the width of the base region P+ is set to be narrower, which is smaller than the N+ regions on both sides. Under the combined effect of the two, the resistance on the current path is greater. Therefore, only a small current is needed to reach the base region P+, which can trigger the bipolar transistor effect, and the negative resistance snapback occurs in advance, further reducing the clamping voltage.

[0090] The two diodes formed are: the first diode D1 from IO1 to VCC and the third diode D3 from IO2 to VCC are formed by P+ / N-epi / N+ junction, N-epi is high-resistance epitaxy, and the P+ and N-epi form a wider space charge region to reduce the capacitance of this diode; the second diode D2 from the ground terminal (Gnd) to IO1 and the fourth diode D4 from the ground terminal Gnd to the signal terminal IO2, that is, the second diode D2 is composed of P+ / PW1 / N+ and the fourth diode D4 is composed of P+ / PW4 / N+, the first P-type well PW1 and the fourth P-type well PW4 are lightly doped, so a wider space charge region is formed between N+ and the first P-type well PW1 and the fourth P-type well PW4 to reduce the capacitance of this diode. The overall capacitance of the device is also reduced. See the circuit schematic diagram Fig.16 shown.

[0091] In this embodiment, the implanted element of the first and fourth P-type wells PW1 and PW4 is boron, and the implantation dose is 5E11-1E13CM. -2 The injection energy is 60-100 KeV; the injection element of the second P-type well PW2 is boron, and the injection dose is 1E14-9E14CM -2 The injection energy is 60-100 KeV; the injection element of the third P-type well PW3 is boron, and the injection dose is 1E12-1E14CM -2 , the injection energy is 60~100KeV.

[0092] The N-type epitaxial layer N-epi is grown and doped with phosphorus or arsenic impurities, and its resistivity is 50-300Ω*CM, and the epitaxial thickness is 3-8μm; P+ is an ultra-shallow junction, the implanted element is boron, and the implantation dose is 1E15-8E15CM -2 , the implantation energy is 40~80KeV; the N+ region is heavily doped, the implantation element is phosphorus or arsenic, and the implantation dose is 2E15~1.2E16 CM -2 The injection energy is 80~150KeV; in the diode formed by P+ / N-epi / N+ from the IO end to the VCC end, a smaller junction area is formed by P+ and N-epi.

[0093] This embodiment is manufactured according to the following steps:

[0094] Step 1: See Figure 2 As shown, an N-type substrate N-sub with a resistivity of 200~300Ω*CM is used, a thin oxide layer is grown on its upper surface, and a P-type buried layer P-BL is formed by photolithography, ion implantation, and thermal process advancement, and then the thin surface oxide layer is removed by wet etching.

[0095] Preferably, N-substrate, thin oxide layer growth thickness is 200~500Å. Ion implantation of boron or boron difluoride, implantation energy is 60~100KeV, implantation dose is 5E11~5E12CM -2 The injection angle is 7 degrees. The thermal process is carried out by sending it into a high-temperature furnace tube at a temperature of 950℃~1100℃ for 60~120 minutes to form a P-type buried layer P-BL.

[0096] Step 2: If Figure 3 As shown, N-type epitaxial growth is performed on the surface of the silicon wafer. Preferably, the N-type epitaxial growth is doped with phosphorus or arsenic impurities, and the resistivity is 50~300Ω*CM and the thickness is 3~8μm.

[0097] Step 3: On the epitaxial surface of the silicon wafer, the first and fourth P-type wells PW1, 4 are photolithographically processed, ion implanted, the second P-type well PW2 is photolithographically processed, ion implanted, and the third P-type well PW3 is photolithographically processed, ion implanted, and the silicon wafer structure formed is shown in FIG. Figure 4 shown.

[0098] As a preference, the implanted element of PW1 is boron, and the implantation dose is 5E11~1E13CM -2 The injection energy is 60~100KeV, and the injection angle is 7 degrees. The PW2 injection element is boron, and the injection dose is 1E14~9E14CM -2 The implantation energy is 60~100KeV, and the implantation angle is 7 degrees. The implantation element of PW3 is boron, and the implantation dose is 1E12~1E14CM -2 The injection energy is 60~100KeV and the injection angle is 7 degrees.

[0099] Step 4: Place the silicon wafer from step 3 into a high-temperature furnace tube, and push the first to fourth P-type wells PW1-4 simultaneously, so that the second and third P-type wells PW2, 3 are connected to the P-type buried layer P-BL. Figure 5 As shown, preferably, the furnace temperature is 1000-1150° C. and the time is 60-120 minutes.

[0100] Step 5: Perform N+ selective implantation on the above surface, which is achieved through photolithography and ion implantation processes. Then enter the furnace tube for annealing to repair the implantation damage. Figure 6As shown. Preferably, the N+ implant element is phosphorus or arsenic, and the implantation dose is 2E15~1.2E16 CM -2 The implantation energy is 80~150KeV. The annealing process temperature is 850℃~950℃, and the time is 30~60 minutes.

[0101] Step 6: Perform P+ selective implantation on the above surface by photolithography and ion implantation. Then perform rapid thermal annealing to repair implantation damage. In this embodiment, the P+ implantation element is boron, and the implantation dose is 1E15~8E15CM -2 The injection energy is 40~80KeV. The rapid thermal annealing temperature is 950~1050℃ and the time is 10~30 seconds. This makes the P+ junction depth significantly shallower than the N+ junction depth. Figure 7 shown.

[0102] Preferably, the distance between P+ and N+ in the third P-type well PW3 is set to 0-5 μm, more preferably 0 μm.

[0103] Preferably, the P+ width in the third P-type well PW3 is set to 1-5 μm, more preferably 0.5-1.5 μm.

[0104] Step 7: Dielectric deposition is performed on the above surface, followed by photolithography and etching to form contact holes. Figure 8 The dielectric layer 1 may be an oxide layer, borophosphorus glass, or a multi-layer insulating film composite layer.

[0105] Step 8: Perform metal deposition, and then use photolithography and etching to form a front metal, which serves as the power supply metal layer 2, the grounding metal layer and the signal terminals IO1 and IO2 respectively.

[0106] Preferably, the metal can be pure aluminum or aluminum silicon compound; more preferably, it is a three-layer composite structure, which is titanium, titanium nitride, and aluminum silicon copper from bottom to top, wherein the thickness of titanium is 200~500Å, the thickness of titanium nitride is 400~1000Å, and the thickness of aluminum silicon copper is 2~4μm. Figure 1 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0107] Example 2

[0108] This embodiment is similar to embodiment 1. Fig. 9As shown, other structures are the same as those in the embodiment, and the manufacturing method is also the same, except that the junction depths of the P+ region and the N+ region are the same or close, and the TVS device includes a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and signal terminals IO1 and IO2. On the basis of the existing TVS device structure, an N-type epitaxial layer N-epi and a P-type buried layer P-BL are grown on an N-type silicon substrate N-sub silicon wafer, wherein:

[0109] From left to right on the surface of the N-type epitaxial layer are:

[0110] A first P-type well PW1 including a P+ region and an N+ region;

[0111] P+ region and N+ region on the surface of the N-type epitaxial layer on one side;

[0112] A second P-type well PW2 having an N+ region;

[0113] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence;

[0114] A fourth P-type well PW4 including a P+ region and an N+ region;

[0115] P+ region and N+ region on the surface of the N-type epitaxial layer on the other side;

[0116] The P-type buried layer P-BL is connected at the bottom of the second P-type well PW2 and the third P-type well PW3; the P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to the ground metal layer Gnd; the N+ region on the surface of the N-type epitaxial layer N-epi and the N+ region of the second P-type well PW2 are connected to the power metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2. The structure is as follows Fig. 9 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0117] Example 3

[0118] The structure is similar to that of Example 1, using an N-type substrate N-sub, without growing an N-type epitaxial layer, and without a P-type buried layer. Fig.10 As shown, the TVS device including the P-type well PW, the P+ region, the N+ region, the dielectric, the ground metal layer Gnd, the power metal layer VCC, the signal terminals IO1 and IO2 are, based on the existing TVS device structure, on the N-type silicon substrate N-sub surface from left to right:

[0119] A first P-type well PW1 including a P+ region and an N+ region;

[0120] P+ region and N+ region on the surface of N-sub, an N-type silicon substrate;

[0121] A second P-type well PW2 having an N+ region;

[0122] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence;

[0123] A fourth P-type well PW4 including a P+ region and an N+ region;

[0124] P+ region and N+ region on the surface of N-type silicon substrate N-sub on the other side;

[0125] The P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to the ground metal layer Gnd; the N+ region on the surface of the N-type silicon substrate N-sub and the N+ region of the second P-type well PW2 are connected to the power metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type silicon substrate N-sub on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type silicon substrate N-sub on the other side are connected to the signal terminal IO2, forming the following Fig.10 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0126] Example 4

[0127] An N-type substrate N-sub is used, an N-type epitaxial layer is not grown, and the shapes of the second P-type well PW2 and the third P-type well PW3 are adjusted so that the third P-type well PW3 surrounds the second P-type well PW2, and the P+ region and N+ region on the N-type substrate N-sub are in the N-type well, such as Fig.11 As shown, the TVS device including the P-type well PW, the P+ region, the N+ region, the dielectric, the ground metal layer Gnd, the power metal layer VCC, the signal terminals IO1 and IO2 are, based on the existing TVS device structure, on the N-type silicon substrate N-sub surface from left to right:

[0128] A first P-type well PW1 including a P+ region and an N+ region;

[0129] A first N-type well NW1 including a P+ region and an N+ region;

[0130] A second P-type well PW2 having an N+ region;

[0131] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence, the third P-type well PW3 surrounding the second P-type well PW2;

[0132] A fourth P-type well PW4 including a P+ region and an N+ region;

[0133] A second N-type well NW2 including a P+ region and an N+ region;

[0134] The P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to the ground metal layer Gnd; the N+ region in the N-type well NW and the N+ region of the second P-type well PW2 are connected to the power metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region in the first N-type well NW1 are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region in the second N-type well NW1 are connected to the signal terminal IO2, forming a circuit as shown in FIG. Fig.11 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0135] Example 5

[0136] Similar to the fourth embodiment, except that a deep P-region Deep P- is connected to the third P-type well PW3.

[0137] like Fig.12 As shown, an N-type substrate is used, no epitaxial growth is performed, and the shapes of PW2 and PW3 are adjusted so that PW3 surrounds PW2, while a deep P-region (Deep P-) is added.

[0138] The TVS device includes a P-type well PW, an N-type well NW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and signal terminals IO1 and IO2. Based on the existing TVS device structure, a deep P-region Deep P- is grown on the surface of the N-type silicon substrate N-sub. From left to right, they are:

[0139] A first P-type well PW1 including a P+ region and an N+ region;

[0140] A first N-type well NW1 including a P+ region and an N+ region;

[0141] A second P-type well PW2 having an N+ region;

[0142] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence, the third P-type well PW3 surrounds the second P-type well PW2, and the bottom of the third P-type well PW3 is connected to a deep P-region Deep P-;

[0143] A fourth P-type well PW4 including a P+ region and an N+ region;

[0144] A second N-type well NW2 including a P+ region and an N+ region;

[0145] The P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to the ground metal layer Gnd; the N+ region in the N-type well NW and the N+ region of the second P-type well PW2 are connected to the power metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region in the first N-type well NW1 are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region in the second N-type well NW1 are connected to the signal terminal IO2, forming a circuit as shown in FIG. Fig.12 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0146] Example 6

[0147] Similar to the embodiment, a P+ buried layer P+BL is added so that the P+BL is located above the P-BL.

[0148] like Fig.13 As shown, a TVS device including a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and signal terminals IO1 and IO2 is constructed based on the existing TVS device structure.

[0149] On the N-type silicon substrate N-sub silicon wafer, a P-buried layer P-BL is first grown, then a P+buried layer P+BL is grown at the same position, and then an N-type epitaxial layer N-epi is grown. The following are the N-type epitaxial layer surfaces from left to right:

[0150] A first P-type well PW1 including a P+ region and an N+ region;

[0151] P+ region and N+ region on the surface of the N-type epitaxial layer on one side;

[0152] A second P-type well PW2 having an N+ region;

[0153] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence;

[0154] A fourth P-type well PW4 including a P+ region and an N+ region;

[0155] P+ region and N+ region on the surface of the N-type epitaxial layer on the other side;

[0156] The P+ region is an ultra-shallow junction;

[0157] The P+ buried layer P+BL is connected at the bottom of the second P-type well PW2 and the third P-type well PW3; the P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to the ground metal layer Gnd; the N+ region on the surface of the N-type epitaxial layer N-epi and the N+ region of the second P-type well PW2 are connected to the power supply metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2, forming a Fig.13 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0158] This embodiment is the same as Embodiment 1. The diode from the IO terminal to the VCC terminal is formed by P+ / N-epi / N+. Since P+ is an ultra-shallow junction, the junction area formed by P+ and N-epi is also smaller, and the diode has a smaller capacitance, which can reduce the capacitance of the entire device.

[0159] Example 7

[0160] The embodiment is similar to the first embodiment, except that the third P-type well PW3 and the second P-type well PW2 are arranged as a surrounding structure or an interdigitated structure.

[0161] like Fig.14 As shown, a TVS device including a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and signal terminals IO1 and IO2 metals is grown on an N-type silicon substrate N-sub silicon wafer on the basis of the existing TVS device structure. In this example, an N-type epitaxial layer N-epi and a P-type buried layer P-BL are grown on an N-type silicon substrate N-sub silicon wafer.

[0162] From left to right on the surface of the N-type epitaxial layer are:

[0163] A first P-type well PW1 including a P+ region and an N+ region;

[0164] P+ region and N+ region on the surface of the N-type epitaxial layer on one side;

[0165] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence;

[0166] A second P-type well PW2 having an N+ region;

[0167] A fifth P-type well PW5 having the same structure as the third P-type well PW3;

[0168] A fourth P-type well PW4 including a P+ region and an N+ region;

[0169] P+ region and N+ region on the surface of the N-type epitaxial layer on the other side;

[0170] The bottom of the second to fifth P-type wells PW2-5 is connected to the P-type buried layer P-BL; the P+ region in the first P-type well PW1 and the third and fifth P-type wells PW3 and 5 are connected to the ground metal layer Gnd; the N+ region on the surface of the N-type epitaxial layer N-epi and the N+ region of the second P-type well PW2 are connected to the power supply metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2, forming a Fig.14 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0171] Similar to Example 1, the diode from the IO terminal to the VCC terminal in this embodiment is formed by P+ / N-epi / N+. Since P+ is an ultra-shallow junction, the junction area formed by P+ and N-epi is also smaller, and the diode has a smaller capacitance, which can reduce the capacitance of the entire device.

[0172] By configuring the third P-type well PW3 and the second P-type well PW2 as a surrounding or interdigitated structure, the current path area is increased, and the surge peak current is improved to obtain better electrostatic discharge and surge protection capabilities.

[0173] Example 8

[0174] Similar to Embodiment 7, except that a layer of lightly doped P-type well PW is added around the P+ region on the surface of the N-type epitaxial layer N-epi.

[0175] like Fig.14 As shown, a TVS device including a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and signal terminals IO1 and IO2 metals is grown on an N-type silicon substrate N-sub silicon wafer on the basis of the existing TVS device structure. Among them: On the surface of the N-type epitaxial layer from left to right are:

[0176] A first P-type well PW1 including a P+ region and an N+ region;

[0177] A P+ region and an N+ region on the surface of the N-type epitaxial layer on one side, wherein the P+ region is lightly doped around to form a sixth P-type well PW6;

[0178] A third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence;

[0179] A second P-type well PW2 having an N+ region;

[0180] A fifth P-type well PW5 having the same structure as the third P-type well PW3;

[0181] A fourth P-type well PW4 including a P+ region and an N+ region;

[0182] The P+ region and N+ region on the surface of the N-type epitaxial layer on the other side, wherein the P+ region is lightly doped around to form a seventh P-type well PW76;

[0183] The bottom of the second to fifth P-type wells PW2-5 is connected to the P-type buried layer P-BL; the P+ region in the first P-type well PW1 and the third and fifth P-type wells PW3 and 5 are connected to the ground metal layer Gnd; the N+ region on the surface of the N-type epitaxial layer N-epi and the N+ region of the second P-type well PW2 are connected to the power supply metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region in the sixth P-type well PW6 are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region in the seventh P-type well PW7 are connected to the signal terminal IO2, forming a Fig.14 The TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure is shown.

[0184] In this embodiment, a lightly doped PW4 region is added to the diode from the IO terminal to the VCC terminal, that is, a diode is formed by P+ / PW4 / N-epi / N+, and PW4 and N-epi can form a wider space charge region, so the capacitance is further reduced.

[0185] The present invention is characterized in that:

[0186] (1) The TVS tube of the structure of the present invention is a bipolar transistor composed of N+ / PW2 / PW3 / N+, and its base regions PW2 and PW3 are short-circuited with the collector N+ at the ground terminal through the P+ lead. When electrostatic discharge or surge occurs, since PW2 is heavily doped, the breakdown voltage of N+ / PW2 is relatively low. After the N+ / PW2 junction is broken down, the current passes through PW2 to PW3, and then flows out from the P+ terminal to the ground. At the same time, because PW3 is lightly doped and has a high resistance, the voltage difference generated by the current from PW3 to P+ is easily greater than 0.7V. At this time, the bipolar transistor effect occurs, and the current can flow not only from the P+ terminal, but also from the N+ at the ground terminal, showing a significant negative resistance characteristic, that is, the current-voltage curve has a significant snapback. In summary, the device of the present invention not only has the advantages of low breakdown voltage and trigger voltage, and faster protection response; it also has the characteristics of smaller on-resistance and clamping voltage, and has a stronger protection capability for the subsequent integrated circuit.

[0187] (2) In order to reduce the device capacitance, the conventional technology only considers reducing the capacitance of the small capacitance diode, but this method ignores the parasitic capacitance of the TVS tube. The present invention forms a wider depletion region by adding a P-buried layer P-BL below the TVS tube, such as below the second and third P-type wells PW2 and PW3, and matches it with the N-type substrate, thereby greatly reducing the parasitic capacitance of the bottom junction of the TVS tube. The overall capacitance of the device is significantly reduced, which is more than 10% smaller than the capacitance of the device with the conventional structure.

[0188] (3) Embodiments 1, 6 and 7 of the present invention: The P+ is an ultra-shallow junction. When the TVS tube is turned on, the path from PW2 and PW3 to the base region P+ is lengthened. At the same time, the width of P+ is set to be narrower. Under the combined effect of the two, the resistance on the current path is larger. Therefore, only a small current is needed to reach the base region P+ to trigger the bipolar transistor effect, causing negative resistance snapback in advance, further reducing the clamping voltage.

[0189] (4) The present invention includes two types of diodes: the first type of diode from the IO terminal to the VCC terminal is formed by P+ / N-epi / N+. Since N-epi is a high-resistance epitaxial, the space charge region formed by P+ and N+ is wider, and the capacitance of this type of diode is reduced. The second type of diode from the ground terminal (Gnd) to the IO terminal is formed by P+ / PW1 / N+. PW1 is lightly doped, so the space charge region formed by N+ and N+ is wider, and the capacitance of this type of diode is also reduced. The overall capacitance of the device is also reduced.

[0190] The embodiment of the present invention has two IO ports. Obviously, more IO ports can be added or IO ports can be removed on this basis. Such changes are still within the protection scope of the present invention.

[0191] The above description is only for illustrating the technical idea and technical features of the present invention. It should be understood that the present invention is not limited to the above embodiments. Many changes, repetitions, modifications and even equivalences may be made to the present invention within the spirit and scope defined by the claims of the present invention, and will still fall within the protection scope of the present invention.

Claims

1. A low capacitance and low clamping voltage transient voltage suppressor, based on the TVS tube structure, comprising an N-type silicon substrate N-sub silicon wafer, a P-type well PW, a P+ region, an N+ region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, and a TVS device of signal terminals IO1 and IO2, characterized in that: At least first to fourth P-type wells PW1, PW2, PW3 and PW4 are included on an N-type silicon substrate N-sub silicon wafer or an N-type epitaxial layer N-epi grown on the silicon wafer, wherein: The first P-type well PW1 and the fourth P-type well PW4 are lightly doped P-type wells with the same structure, and the wells include a P+ region and an N+ region; The second P-type well PW2 includes a heavily doped N+ region; and, The third P-type well PW3 sequentially includes an N+ region, a P+ region and a lightly doped N+ region, and the width of the P+ region in the third P-type well PW3 is smaller than the width of the N+ region; The TVS tube is composed of an N+ region, PW2, PW3 and N+ to form a bipolar transistor, and the second P-type well PW2 and the third P-type well PW3 in the base region are short-circuited with the collector N+ at the ground terminal through the P+ lead; when static electricity is released or a surge occurs, since the second P-type well PW2 is heavily doped, the N+ / PW2 breakdown voltage is relatively low. After the N+ / PW2 junction is broken down, the current passes through the second P-type well PW2 to the third P-type well PW3, and then flows out from the P+ terminal to the ground terminal; at the same time, because the third P-type well PW3 is lightly doped, its resistance is relatively high, so the voltage difference generated by the current from the third P-type well PW3 to P+ is easily greater than 0.7V. At this time, a bipolar transistor effect occurs, and the current not only flows out from the P+ terminal, but also flows out from the N+ at the ground terminal, presenting a significant negative resistance characteristic, that is, the current-voltage curve has a significant snapback; A P-type buried layer P-BL is added below the second P-type well PW2 and the third P-type well PW3, and is matched with the N-type silicon substrate to form a wider depletion region, thereby reducing the parasitic capacitance of the bottom junction of the TVS tube; The P+ region is an ultra-shallow junction or has the same junction depth as the N+ region. When the TVS tube is turned on, the path from the second P-type well PW2 and the third P-type well PW3 to the base region P+ is lengthened. At the same time, the width of the base region P+ is set to be narrower, and the width is smaller than the width of the N+ on both sides thereof. The TVS tube forms two types of diodes: the first type of diode from the IO terminal to the VCC terminal is formed by the P+ region, N-epi, and N+ region, N-epi is a high-resistance epitaxial layer, and the P+ region and N-epi form a wider space charge region to reduce the capacitance of this diode; the second type of diode from the ground terminal Gnd to the signal terminal IO is formed by the P+ region, PW1, N+ region and / or the P+ region, PW4, and N+ region. The first P-type well PW1 and the fourth P-type well PW4 are lightly doped, so a wider space charge region is formed between N+ and the first P-type well PW1 and the fourth P-type well PW4 to reduce the capacitance of this diode; The implanted element of the first and fourth P-type wells PW1 and PW4 is boron, and the implanted dose is 5E11~1E13CM -2 The injection energy is 60~100KeV; the injection element of the second P-type well PW2 is boron, and the injection dose is 1E14~9E14CM -2 The injection energy is 60~100KeV; the injection element of the third P-type well PW3 is boron, and the injection dose is 1E12~1E14CM -2 , the injection energy is 60~100KeV; The N-type epitaxial layer is grown with phosphorus or arsenic impurities, and its resistivity is 50~300Ω*CM, and the thickness of the epitaxial layer is 3~8μm; the P+ region is an ultra-shallow junction, the implanted element is boron, and the implantation dose is 1E15~8E15CM -2 , the implantation energy is 40~80KeV; the N+ region is heavily doped, the implantation element is phosphorus or arsenic, and the implantation dose is 2E15~1.2E16 CM -2 , the injection energy is 80~150KeV; in the diode formed by P+ / N-epi / N+ from the IO end to the VCC end, a smaller junction area is formed by P+ and N-epi; An N-type epitaxial layer and a P-type buried layer P-BL are grown on an N-type silicon substrate silicon wafer. From left to right, the surface of the N-type epitaxial layer is sequentially a first P-type well PW1 including a P+ region and an N+ region, a P+ region and an N+ region on the surface of the N-type epitaxial layer on one side, a second P-type well PW2 with an N+ region, a third P-type well PW3 including an N+ region, a P+ region and an N+ region in sequence, a fourth P-type well PW4 including a P+ region and an N+ region, a P+ region and an N+ region on the surface of the N-type epitaxial layer on the other side, and the bottoms of the second and third P-type wells PW2 and PW3 are connected to the P-type buried layer P-BL; the P+ region in the first P-type well PW1 and the third P-type well PW3 are connected to a metal ground terminal; The N+ region on the surface of the N-type epitaxial layer and the N+ region of the second P-type well PW2 are connected to the power metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2.

2. The low capacitance and low clamping voltage transient voltage suppressor according to claim 1, characterized in that: The third P-type well PW3 and the second P-type well PW2 are arranged in a surrounding shape or an interdigitated shape.

3. The low capacitance and low clamping voltage transient voltage suppressor according to claim 1, characterized in that: The resistivity of the N-type silicon substrate is 200-300Ω*CM.

4. The low capacitance and low clamping voltage transient voltage suppressor according to claim 1, characterized in that: The P-type buried layer P-BL has a thickness of 200~500Å, and ions are implanted with boron or boron difluoride, with an implantation energy of 60~100KeV and an implantation dose of 5E11~5E12CM. -2 .

5. The low capacitance and low clamping voltage transient voltage suppressor according to claim 1, characterized in that: The junction depth of the P+ region is shallower than that of the N+ region.

6. The low capacitance and low clamping voltage transient voltage suppressor according to claim 3, characterized in that: No N-type epitaxial layer is grown on the N-type silicon substrate, and the P+ region and N+ region originally arranged on the N-type epitaxial layer are directly arranged on the surface of the N-type silicon substrate, that is, the P+ region and N+ region are formed on the surface of the N-type silicon substrate.

7. The low capacitance and low clamping voltage transient voltage suppressor according to claim 6, characterized in that: The P+ region and N+ region in the N-type silicon substrate are arranged in the N-type well NW, and the shapes of the second and third P-type wells PW2 and PW3 are adjusted so that the third P-type well PW3 surrounds the second P-type well PW2.

8. The low capacitance and low clamping voltage transient voltage suppressor according to claim 7, characterized in that: A deep P-region Deep P- is added at the bottom of the second and third P-type wells PW2 and PW3.

9. The low capacitance and low clamping voltage transient voltage suppressor according to claim 1, characterized in that: A P+ buried layer P+BL is added between the upper surface of the P-type buried layer P-BL and the bottoms of the second P-type well PW2 and the third P-type well PW3.

10. The low capacitance and low clamping voltage transient voltage suppressor according to claim 2, characterized in that: An N-type epitaxial layer and a P-type buried layer P-BL are grown on an N-type silicon substrate silicon wafer. From left to right on the surface of the N-type epitaxial layer are the first P-type well PW1 including the P+ region and the N+ region, the P+ region and the N+ region on the surface of the N-type epitaxial layer on one side, the third P-type well PW3 including the N+ region, the P+ region and the N+ region in sequence, the second P-type well PW2 with the N+ region, the fifth P-type well PW5 including the N+ region, the P+ region and the N+ region in sequence, the fourth P-type well PW4 including the P+ region and the N+ region, the P+ region and the N+ region on the surface of the N-type epitaxial layer on the other side, The bottom of the third P-type well PW3, the second P-type well PW2 and the fifth P-type well PW5 are connected to the P-type buried layer P-BL; the P+ region in the first P-type well PW1, the third P-type well PW3 and the fifth P-type well PW5 are connected to the metal ground terminal; the N+ region on the surface of the N-type epitaxial layer and the N+ region of the second P-type well PW2 are connected to the power supply metal layer VCC; the N+ region in the first P-type well PW1 and the P+ region on the surface of the N-type epitaxial layer on one side are connected to the signal terminal IO1; the N+ region in the fourth P-type well PW4 and the P+ region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2.

11. The low capacitance and low clamping voltage transient voltage suppressor according to claim 10, characterized in that: A lightly doped P-type well PW region is added around the P+ region on the surface of the N-type epitaxial layer. The diode from the IO end to VCC is formed by P+ / lightly doped P-type well PW, N-epi and N+. The lightly doped P-type well PW and the N-type epitaxial layer N-epi form a wider space charge region to further reduce the capacitance.

12. A method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to any one of claims 1 to 5, characterized in that The steps include: Step 1: Use an N-type silicon substrate N-sub silicon wafer, grow a thin oxide layer on its upper surface, and form a P-type buried layer P-BL through photolithography, ion implantation, and thermal process advancement. Then remove the thin oxide layer on the surface by wet etching; Step 2: growing an N-type epitaxial layer on the surface of the silicon wafer; Step 3: On the surface of the epitaxial layer of the silicon wafer, the first and fourth P-type wells PW1 and PW4 are photolithographically processed, ion implanted, the second P-type well PW2 is photolithographically processed, ion implanted, and the third PW3 is photolithographically processed, ion implanted, wherein the positions of the second and third P-type wells PW2 and PW3 correspond to the position of the P-type buried layer P-BL, and the first and fourth P-type wells PW1 and PW4 have the same structure; Step 4: Place the silicon wafer into a high-temperature furnace tube, and push the first to fourth P-type wells PW1-PW4 simultaneously, so that the second and third P-type wells PW2 and PW3 are connected to the P-type buried layer P-BL region; Step 5: Perform N+ selective implantation on the above surface by photolithography and ion implantation process, the N+ implantation element is phosphorus or arsenic, and then enter the furnace tube for annealing to repair the implantation damage; Step 6: Perform P+ selective implantation on the above surface by photolithography and ion implantation process, the P+ implantation element is boron, wherein the spacing between P+ and N+ in the third P-type well PW3 is set to 0~5μm, the implantation energy is less than that of N+, and then rapid thermal annealing is performed to repair the implantation damage; Step 7: depositing a dielectric on the surface to form a dielectric layer, and then performing photolithography and etching to form contact holes, wherein the dielectric layer is an oxide layer, borophosphorus glass, or a multi-layer insulating film composite layer; Step 8: Perform metal deposition, and then form a front metal layer through photolithography and etching. The metal layer is a pure aluminum layer, an aluminum silicon compound layer or a metal composite layer structure.

13. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 12, characterized in that: In step 1, a thin oxide layer is grown to a thickness of 200-500Å, and ions are implanted with boron or boron difluoride at an energy of 60-100 KeV and a dose of 5E11-5E12CM. -2 The injection angle is 7 degrees, and the thermal process is promoted into the high-temperature furnace tube with a temperature of 950℃~1100℃ and a time of 60~120 minutes.

14. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 12, characterized in that: In step 2, N-type epitaxial growth is doped with phosphorus or arsenic impurities, with a resistivity of 50~300Ω*CM and an epitaxial thickness of 3~8μm.

15. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 12, characterized in that: In step 3, the first and fourth P-type wells PW1 and PW4 are implanted with boron, and the implantation dose is 5E11~1E13CM -2 The injection energy is 60~100KeV, the injection angle is 7 degrees; the second P-type well PW2 is injected with boron, and the injection dose is 1E14~9E14CM -2 The injection energy is 60~100KeV, the injection angle is 7 degrees; the injection element of the third P-type well PW3 is boron, and the injection dose is 1E12~1E14CM -2 The injection energy is 60~100KeV and the injection angle is 7 degrees.

16. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 12, characterized in that: In step 4, the furnace tube temperature is 1000-1150° C. for 60-120 minutes.

17. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 12, characterized in that: In step 5, the N+ region is implanted with phosphorus or arsenic, and the implantation dose is 2E15~1.2E16 CM -2 The implantation energy is 80~150KeV, the annealing process temperature is 850℃~950℃, and the time is 30~60 minutes.

18. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 12, characterized in that: In step 6, the element implanted in the P+ region is boron, and the implantation dose is 1E15~8E15CM -2 The injection energy is 40-80 KeV; the rapid thermal annealing temperature is 950-1050°C and the time is 10-30 seconds, so that the junction depth of the P+ region is significantly shallower than that of the N+ region.

19. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 18, characterized in that: In step 6, the distance between the P+ region and the N+ region in the third P-type well PW3 is 0 μm, and the width of the P+ region in the third P-type well PW3 is set to 1-5 μm.

20. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 19, characterized in that: In step 6, the width of the P+ region in the third P-type well PW3 is set to 0.5-1.5 μm.

21. The method for manufacturing a TVS tube with a low capacitance and low clamping voltage transient voltage suppressor structure according to claim 12, characterized in that: In step 8, the metal composite layer structure is a three-layer structure of titanium, titanium nitride, and aluminum silicon copper from bottom to top, wherein the thickness of titanium is 200~500Å, the thickness of titanium nitride is 400~1000Å, and the thickness of aluminum silicon copper is 2~4μm.

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