Analog-to-digital conversion device and method based on differential capacitor array

Abstract

The present invention provides an analog-to-digital conversion device and method based on a differential capacitor array, the device comprising: a comparator; a common-phase low-order capacitor array connected to the common-phase input terminal of the comparator and a plurality of common-phase high-order split capacitors, wherein the capacitance value of the capacitor in the common-phase low-order capacitor array is C Pm =2 m‑1 C, the capacitance value of each common-phase high-bit split capacitor is 2 n‑5 C; an inverting low-order capacitor array and a plurality of inverting high-order split capacitors connected to the inverting input terminal of the comparator, wherein the capacitance value of the capacitor in the inverting low-order capacitor array is C Nm =2 m‑1 C, the capacitance value of each inverting high-bit split capacitor is 2 n‑5 C; a switch selection unit for adjusting the voltage value on each capacitor respectively; and a gradual approximation logic control circuit connected to the output end of the comparator for controlling the switch selection unit to be connected to the corresponding voltage unit. The present invention solves the problem of relatively large power consumption generated by the analog-to-digital converter in the data conversion process in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitor array switches, and in particular to an analog-to-digital conversion device and method based on a differential capacitor array. Background Art

[0002] Low power consumption has become the mainstream trend of chip design, and low-voltage and low-power analog-to-digital converters are important components of mobile devices, portable medical diagnostics, monitoring equipment, and wireless sensors. These portable smart devices are usually limited by size and usage time, so they usually work at low power supply voltage to achieve the purpose of reducing power consumption. Compared with analog-to-digital converters (ADCs) of other structures, successive approximation ADCs (SAR ADCs) have the advantages of low power consumption and small size.

[0003] However, the capacitance value of the capacitor array of the traditional charge redistribution SAR ADC increases exponentially, which is not only not conducive to reducing the capacitor area and optimizing power consumption, but also affects the increase of the sampling rate. In addition, the larger highest-order capacitance will cause a larger circuit load, so the analog front end needs to have a larger driving capability, which makes the power consumption of the entire successive approximation analog-to-digital converter relatively large.

[0004] Therefore, it is necessary to study an analog-to-digital conversion method to reduce the power consumption generated during the data conversion process. Summary of the invention

[0005] The object of the present invention is to provide an analog-to-digital conversion device and method based on a differential capacitor array to solve the problem of relatively large power consumption generated by the analog-to-digital converter during data conversion in the prior art.

[0006] To achieve the above object, the present invention is achieved as follows:

[0007] In a first aspect, the present invention provides an analog-to-digital conversion device based on a differential capacitor array, comprising:

[0008] Comparator;

[0009] A common-phase low-order capacitor array and a plurality of common-phase high-order split capacitors connected to the common-phase input terminal of the comparator, wherein the capacitance value of the capacitor in the common-phase low-order capacitor array is C Pm =2 m-1 C, the capacitance value of each common-phase high-bit split capacitor is 2 n-5 C;

[0010] An inverting low-order capacitor array and a plurality of inverting high-order split capacitors connected to the inverting input terminal of the comparator, wherein the capacitance value of the capacitor in the inverting low-order capacitor array is C Nm =2 m-1 C, the capacitance value of each inverting high-bit split capacitor is 2 n-5 C;

[0011] a switch selection unit connected to the in-phase low-order capacitor array, the plurality of in-phase high-order split capacitors, the inverted low-order capacitor array, and the plurality of inverted high-order split capacitors, respectively, for adjusting the voltage value on each capacitor; and

[0012] A successive approximation logic control circuit connected to the output terminal of the comparator, used for controlling the switch selection unit to be connected to the corresponding voltage unit;

[0013] Where m∈[1,n-4], n is greater than or equal to 5, C P0 =C, C N0 =C.

[0014] As a further improvement of the present invention, the number of the multiple in-phase high-bit split capacitors and the number of the multiple inverted high-bit split capacitors are both two, and the two in-phase high-bit split capacitors are connected in parallel, and the two inverted high-bit split capacitors are connected in parallel.

[0015] As a further improvement of the present invention, the switch selection unit is composed of two in-phase high-order selection switches correspondingly connected to two in-phase high-order split capacitors, two inverting high-order selection switches correspondingly connected to two inverting high-order split capacitors, a in-phase low-order selection switch correspondingly connected to each capacitor in the in-phase low-order capacitor array, and an inverting low-order selection switch correspondingly connected to each capacitor in the inverting low-order capacitor array.

[0016] As a further improvement of the present invention, the voltage unit includes a first reference voltage V cm , the second reference voltage V ref and a third reference voltage GND.

[0017] As a further improvement of the present invention, the total capacitance value of the analog-to-digital conversion device is 2 n-2 C.

[0018] As a further improvement of the present invention, before the comparator performs the first comparison, the two in-phase high-bit selection switches and the two inverted high-bit selection switches are connected to the third reference voltage GND, and the in-phase low-bit selection switch and the inverted low-bit selection switch are connected to the first reference voltage V cm ;

[0019] Before the comparator performs the second comparison, based on the first comparison result, two inverting high-position selection switches or two in-phase high-position selection switches are switched to connect to the first reference voltage V cm , and the inverting low-position selection switch or the non-inverting low-position selection switch is switched to connect to the second reference voltage V ref ;

[0020] Before the comparator performs the third comparison, based on the first comparison result and the second comparison result, the two inverting high-bit selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm , two in-phase high-position selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm ;

[0021] Among them, n = 5, the in-phase low-position capacitor array consists of capacitor C P1 and capacitor C P0 The inverting low-order capacitor array consists of capacitor C N1 and capacitor C N0 constitute.

[0022] As a further improvement of the present invention, when the first comparison result is 1, the two inverting high-bit selection switches are switched to connect to the first reference voltage V cm , the inverting low select switch is connected to the second reference voltage V ref ;

[0023] When the first comparison result is 0, the two in-phase high-bit selection switches are switched to the first reference voltage V cm , the in-phase low position selection switch is switched to connect to the second reference voltage V ref .

[0024] As a further improvement of the present invention, when the first comparison result is 1 and the second comparison result is 1, the two inverting high-bit selection switches are switched to connect to the second reference voltage V ref ;

[0025] When the first comparison result is 1 and the second comparison result is 0, the two in-phase high-bit selection switches are switched to the first reference voltage V cm ;

[0026] When the first comparison result is 0 and the second comparison result is 1, the two inverting high-bit selection switches are switched to the first reference voltage V cm ;

[0027] When the first comparison result is 0 and the second comparison result is 0, the two same-phase high-bit selection switches are switched to connect to the second reference voltage V ref .

[0028] As a further improvement of the present invention, before the comparator performs the fourth comparison, based on the first comparison result, the second comparison result and the third comparison result, the capacitor C of the same-phase low-order capacitor array is P1 The connected in-phase low-position selection switch is switched to the first reference voltage V cm or the third reference voltage GND, or the capacitor C of the inverting low-order capacitor array N1 The connected inverting low select switch is switched to the first reference voltage V cm or a third reference voltage GND;

[0029] Before the comparator performs the fifth comparison, based on the first comparison result, the second comparison result, the third comparison result and the fourth comparison result, the capacitance C of the in-phase low-order capacitance array P0 The voltage on the lower board decreases to the first reference voltage V cm Half of C P1 The voltage on the lower board decreases or increases to the first reference voltage V cm Half of the capacitance C of the inverting low-order capacitor array N1 or C N0 The voltage on the lower board decreases to the first reference voltage V cm Half of C N1 The voltage on the lower board decreases or increases to the first reference voltage V cm half.

[0030] In a second aspect, an analog-to-digital conversion method based on a differential capacitor array is provided, comprising:

[0031] Control the switch selection unit to switch and connect to the corresponding voltage unit;

[0032] The signals of the in-phase input terminal and the inverting input terminal of the comparator are collected. The in-phase input terminal of the comparator is connected to the in-phase low-order capacitor array and multiple in-phase high-order split capacitors. The capacitance value of the in-phase low-order capacitor array is C Pm =2 m-1 C, m∈[1,n-4], n is greater than or equal to 5, C P0 = C, the size of each common-phase high-bit split capacitor is 2 n-5 C, the inverting input terminal of the comparator is connected to an inverting low-order capacitor array and a plurality of inverting high-order split capacitors, and the capacitance value of the inverting low-order capacitor array is C N(m) =2 m-1 C, C N0 = C, the size of each inverting high-bit split capacitor is 2 n-5 C;

[0033] Comparing the signal at the in-phase input terminal with the signal at the inverting input terminal by a comparator to output a digital signal corresponding to the signal at the in-phase input terminal or a digital signal corresponding to the signal at the inverting input terminal;

[0034] Among them, the switch selection unit is respectively connected to the in-phase low-order capacitor array, multiple in-phase high-order split capacitors, the inverted low-order capacitor array, and multiple inverted high-order split capacitors, so as to adjust the voltage value on each capacitor respectively through the switch selection unit.

[0035] The beneficial effects of the embodiments of the present invention are:

[0036] In the analog-to-digital conversion device based on the differential capacitor array of the present invention, the non-inverting input terminal of the comparator is connected to a capacitor having a capacitance value satisfying 2 m-1 The capacitors of C form a low-order capacitor array with the same phase, and the capacitance value is 2 n-5 C is a multiple in-phase high-bit split capacitor, and the inverting input of the comparator is connected with a capacitor whose value satisfies 2 m-1 The inverting low-order capacitor array composed of capacitors C has a capacitance value of 2 n-5 C has a plurality of inverted high-order split capacitors, whereby the total capacitance value in the capacitor array of the present invention is greatly reduced, thereby reducing the loss generated in the analog-to-digital conversion process.

[0037] Secondly, since the multiple in-phase high-bit split capacitors (such as two in-phase high-bit split capacitors) connected to the in-phase input terminal of the comparator are connected in parallel, and the multiple inverted high-bit split capacitors (such as two inverted high-bit split capacitors) connected to the inverted input terminal are connected in parallel, therefore, compared with the solution of the MSB bit capacitor array (i.e., high-bit capacitor array) formed by a capacitor matrix in the prior art, the present invention can greatly reduce the capacitance value of the MSB bit through the in-phase high-bit split capacitors connected in parallel and the inverted high-bit split capacitors connected in parallel, thereby further reducing the power consumption generated by analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic structural block diagram of an analog-to-digital conversion device based on a differential capacitor array according to an embodiment of the present invention;

[0039] Figure 2 is a schematic structural diagram of a voltage unit 60 according to an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the first three comparisons of an analog-to-digital conversion device based on a differential capacitor array according to a specific embodiment of the present invention;

[0041] Figure 4 Based on Figure 3 A schematic diagram of executing the fourth and fifth comparisons based on the third comparison result A;

[0042] Figure 5 Based on Figure 3 A schematic diagram of executing the fourth and fifth comparisons based on the third comparison result B;

[0043] Figure 6 Based on Figure 3 A schematic diagram of executing the fourth and fifth comparisons based on the third comparison result C;

[0044] Figure 7 Based on Figure 3 A schematic diagram of executing the fourth and fifth comparisons based on the third comparison result D;

[0045] Figure 8 Based on Figure 3 Schematic diagram of executing the fourth and fifth comparisons based on the third comparison result E;

[0046] Fig. 9 Based on Figure 3 Schematic diagram of executing the fourth and fifth comparisons based on the third comparison result F;

[0047] Fig.10 Based on Figure 3 Schematic diagram of executing the fourth and fifth comparisons based on the third comparison result G;

[0048] Fig.11 Based on Figure 3 A schematic diagram of executing the fourth and fifth comparisons based on the third comparison result H;

[0049] Fig.12 Schematic curve diagram showing the data switching power consumption of the analog-to-digital conversion device based on the differential capacitor array according to the embodiment of the present invention and the SAR ADC with the common model switching strategy in the prior art respectively changing with the output code;

[0050] Fig.13 The figure is a schematic flow chart of an analog-to-digital conversion method based on a differential capacitor array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The present invention is described in detail below in conjunction with the various embodiments shown in the accompanying drawings, but it should be noted that these embodiments are not limitations of the present invention, and any equivalent transformations or substitutions in functions, methods, or structures made by ordinary technicians in the field based on these embodiments are all within the scope of protection of the present invention.

[0052] The technical solutions provided by various embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0053] Combination Figure 1 and Figure 2 To illustrate, an embodiment of the present invention provides an analog-to-digital conversion device based on a differential capacitor array, comprising: a comparator 10; and a common-phase input terminal V IP (i.e., the positive electrode "+" end of the comparator 10) is connected to a common-phase low-order capacitor array 201 and a plurality of common-phase high-order split capacitors 202, and the capacitance value of the common-phase low-order capacitor array 201 is C Pm =2 m-1 C; and the inverting input terminal V of comparator 10 IN (i.e., the negative electrode "-" end of the comparator 10) is connected to an inverting low-order capacitor array 301 and a plurality of inverting high-order split capacitors 302, and the capacitance value of the inverting low-order capacitor array 301 is C Nm =2 m-1 C; a switch selection unit connected to the same phase low-order capacitor array 201, multiple same phase high-order split capacitors 202, the reverse phase low-order capacitor array 301, and multiple reverse phase high-order split capacitors 302, respectively, for adjusting the voltage value on each capacitor (the capacitor includes the same phase low-order capacitor array 201 and the capacitor included in the reverse phase low-order capacitor array 301, multiple same phase high-order split capacitors 202, and multiple reverse phase high-order split capacitors 302); and a gradual approximation logic control circuit 50 connected to the output end of the comparator 10, for controlling the switch selection unit to be connected to the corresponding voltage unit 60. The voltage unit 60 includes a first reference voltage V cm , the second reference voltage V ref And the third reference voltage GND. Among them, V ref =2V cm .

[0054] Among them, C Pm represents the capacitance of the mth column in the in-phase low-order capacitance array 201, C P0 =C, C P0 Indicates the capacitors located before the first column in the in-phase low-order capacitor array 201. The capacitance value of each in-phase high-order split capacitor is 2 n-5 C. C Nm represents the capacitance value corresponding to the capacitor in the mth column of the inverted low-order capacitor array 301, C N0 =C, C N0 Indicates the capacitors located before the first column in the in-phase low-order capacitor array 201. The capacitance value of each inverting high-order split capacitor is 2 n-5 C. m∈[1, n-4], n is greater than or equal to 5, C represents the unit capacitance, and the capacitance value of the unit capacitance can be set according to actual use requirements. The total capacitance value of the analog-to-digital conversion device is 2 n-2 C.

[0055] The switch selection unit is composed of a plurality of in-phase high-order selection switches 401 connected correspondingly to a plurality of in-phase high-order split capacitors 202, a plurality of inverting high-order selection switches 402 connected correspondingly to a plurality of inverting high-order split capacitors 302, a in-phase low-order selection switch 403 connected correspondingly to each capacitor in the in-phase low-order capacitor array 201, and an inverting low-order selection switch 404 connected correspondingly to each capacitor in the inverting low-order capacitor array 301.

[0056] It should be noted that the multiple same-phase high-position selection switches 401 are all connected to the same voltage in the voltage unit 60. For example, the multiple same-phase high-position selection switches 401 are all connected to the first reference voltage V cm Or the second reference voltage V ref or the third reference voltage GND, so that the multiple in-phase high-bit split capacitors 202 are connected in parallel. Similarly, the multiple inverting high-bit selection switches 402 are all connected to the same voltage in the voltage unit 60, for example, the multiple inverting high-bit selection switches 402 are all connected to the first reference voltage V cm Or the second reference voltage V ref Or the third reference voltage GND, so that the multiple inverting high-bit split capacitors 302 are connected in parallel with each other.

[0057] In the analog-to-digital conversion device based on the differential capacitor array according to the embodiment of the present invention, the non-inverting input terminal of the comparator 10 is connected to a capacitor having a capacitance value satisfying 2 m-1 The capacitors of C form a low-order capacitor array 201 with the same phase, and the capacitance value is 2 n-5 C has multiple in-phase high-bit split capacitors 202, and the inverting input terminal of the comparator 10 is connected to a capacitor with a capacitance value satisfying 2 m-1 The inverting low-order capacitor array 301 is composed of capacitors C, and the capacitance value is 2 n-5 C has multiple inverting high-order split capacitors 302. Therefore, it is not difficult to obtain that the total capacitance value of the embodiment of the present invention is 2 n-2 C, for example, in a 5-bit analog-to-digital conversion device, the total capacitance value is 8C, while the total capacitance value of the switch conversion scheme based on the differential capacitance matrix in the prior art is 32C or 16C. Therefore, the total capacitance value in the embodiment of the present invention is greatly reduced, thereby effectively reducing the loss generated by the analog-to-digital conversion process.

[0058] Furthermore, since the multiple in-phase high-bit split capacitors 202 connected to the in-phase input terminal of the comparator 10 are connected in parallel, and the multiple inverting high-bit split capacitors 302 connected to the inverting input terminal are connected in parallel, compared with the solution of the MSB bit capacitor array (i.e., high-bit capacitor array) formed by the capacitor matrix in the prior art, the embodiment of the present invention can greatly reduce the capacitance value of the MSB bit through the in-phase high-bit split capacitors 202 connected in parallel and the inverting high-bit split capacitors 302 connected in parallel, thereby further reducing the power consumption generated by the analog-to-digital conversion.

[0059] In the above-mentioned specific embodiment, the number of the multiple in-phase high-bit split capacitors 202 and the number of the multiple inverted high-bit split capacitors 302 are both two. Thus, the two in-phase high-bit split capacitors are connected in parallel, and the two inverted high-bit split capacitors are connected in parallel. The embodiment of the present invention can effectively reduce the capacitance value of the MSB bit through two in-phase high-bit split capacitors 202 connected in parallel and two inverted high-bit split capacitors 302 connected in parallel, which not only further reduces the power consumption generated by the analog-to-digital conversion, but also alleviates the bandwidth problem caused by the charging of large capacitors because the capacitance of the embodiment of the present invention is greatly reduced. Therefore, the analog-to-digital conversion device based on the differential capacitor array of the embodiment of the present invention has the characteristics of fast data conversion speed, small total capacitance value and low power consumption.

[0060] In a specific embodiment, n=5. Figure 3 As shown, two in-phase high-bit split capacitors (in-phase high-bit split capacitors C 202a And the same phase high split capacitor C 202b ) and two inverting high-bit split capacitors (inverting high-bit split capacitors C 302a and the inverting high split capacitor C 302b ) is described, in an embodiment of the present invention, during the five comparisons, and before each comparison, the voltages on the capacitors in the same-phase high-bit split capacitor 202, the same-phase low-bit capacitor array 201, the reverse-phase high-bit split capacitor 302, and the reverse-phase low-bit capacitor array 301 are adjusted or switched to reduce the accuracy requirements on the switch selection unit, thereby reducing the complexity of the overall circuit and reducing the power consumption generated by the capacitor array (the same-phase low-bit capacitor array and the reverse-phase low-bit capacitor array) during the conversion process.

[0061] Specifically, when n=5, the in-phase low-order capacitor array 201 is composed of capacitors C P1 and capacitor C P0 The inverting low-order capacitor array 301 is composed of capacitor C N1 and capacitor C N0 The capacitance values ​​of the two in-phase high-bit split capacitors are both C, and the capacitance values ​​of the two inverting high-bit split capacitors are both C. N1 =C N0 =C P1 =C P0 =C.

[0062] Before the comparator 10 performs the first comparison, the two same-phase high-position selection switches 401 (i.e., the same-phase high-position selection switches S KP1 And the same phase high position selection switch S KP2 ) and two inverting high position selection switches 402 (inverting high position selection switches S KN1and reverse high position selector switch S KN2 ) are controlled to be connected to the third reference voltage GND, the same phase low position selection switch 403 (the same phase low position selection switch S P1 and the same phase low position selector switch S P2 ) and the inverting low position selection switch 404 (inverting low position selection switch S N1 and reverse low position selector switch S N2 ) are connected to the first reference voltage V cm At this time, the upper plates of the two in-phase high-order split capacitors 202 and the in-phase low-order capacitor array 201 are all connected by controlling the switch K P The upper plates of the two inverting high-order split capacitors 302 and the inverting low-order capacitor array 301 are connected to the non-inverting input terminal of the comparator 10 through the control switch K N Connected to the inverting input terminal of the comparator 10.

[0063] In this way, when the control switch K P , control switch K N When both are closed, the in-phase input terminal and the inverting input terminal of the comparator 10 respectively collect the voltage signals on each capacitor. P , control switch K N can be disconnected to pass through the comparator 10 based on its non-inverting input terminal V IP and the inverting input V IN The collected voltage signal is compared for the first time to obtain the value of the most significant bit MSB. IP The voltage signal is higher than the inverting input terminal V IN If the voltage signal is 1, the MSB is set to 1, otherwise, the MSB is set to 0. Since the voltages on the capacitors are not switched after the voltage signal is collected, no energy is consumed in the first comparison process.

[0064] Before the comparator performs the second comparison, based on the first comparison result, two inverting high-bit selection switches or two in-phase high-bit selection switches are switched to connect to the first reference voltage V cm , and the inverting low-position selection switch or the non-inverting low-position selection switch is switched to connect to the second reference voltage V ref Specifically, when the first comparison result is 1, the two inverting high-bit selection switches are switched to the first reference voltage V cm , the inverting low select switch is connected to the second reference voltage V ref That is, the lower plate of the inverting high-bit split capacitor is switched from the third reference voltage GND to the first reference voltage V cm The voltage connected to the second highest inverting low capacitor array is the first reference voltage V cm Increase to the second reference voltage Vref At this time, the inverting input terminal V IN The voltage value increases by 1 / 2V ref Therefore, the comparator 10 then generates a voltage according to its non-inverting input terminal V IP and the inverting input V IN The voltage signal is compared to get the MSB-1 bit value. IP The voltage signal is greater than the inverting input terminal V IN If the voltage signal is , the MSB-1 position is 1; otherwise, the MSB-1 position is 0.

[0065] When the first comparison result is 0, the two in-phase high-bit selection switches are switched to the first reference voltage V cm , the in-phase low position selection switch is switched to connect to the second reference voltage V ref That is, the lower plate of the in-phase high-bit split capacitor is switched from the third reference voltage GND to the first reference voltage V cm The voltage connected to the lower plate of the capacitor in the second highest in-phase low-order capacitor array is the first reference voltage V cm Increase to the second reference voltage V ref At this time, the non-inverting input terminal V IP The voltage value increases by 1 / 2V ref Therefore, the comparator 10 then generates a voltage according to its non-inverting input terminal V IP and the inverting input V IN The second comparison process is the same as the comparison process when the first comparison result is 1, and will not be described here.

[0066] Before the comparator 10 performs the third comparison, based on the first comparison result and the second comparison result, the two inverted high-bit selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm , two in-phase high-position selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm .

[0067] Specifically, when the first comparison result is 1 and the second comparison result is 1, the two inverting high-bit selection switches are switched to connect to the second reference voltage V ref That is, the voltage connected to the lower plate of the inverting high-bit split capacitor is the first reference voltage V cm Switch connected to the second reference voltage V ref , thus, the inverting input terminal V of the comparator 10 IN The voltage value increases by 1 / 4V ref (i.e., an increase of 1 / 2V cm ).

[0068] When the first comparison result is 1 and the second comparison result is 0, the two in-phase high-bit selection switches are switched to the first reference voltage V cm That is, the voltage connected to the lower plate of the in-phase high-bit split capacitor is switched from the third reference voltage GND to the first reference voltage V cm , thus, the non-inverting input terminal V of the comparator 10 IP The voltage value increases by 1 / 4V ref .

[0069] When the first comparison result is 0 and the second comparison result is 1, the two inverting high-bit selection switches are switched to the first reference voltage V cm That is, the voltage connected to the lower plate of the inverting high-bit split capacitor is switched from the third reference voltage GND to the first reference voltage V cm , thus, the inverting input terminal V of the comparator 10 IN The voltage value increases by 1 / 4V ref .

[0070] When the first comparison result is 0 and the second comparison result is 0, the two in-phase high-bit selection switches are switched to the second reference voltage V ref That is, the voltage connected to the lower plate of the in-phase high-bit split capacitor is the first reference voltage V cm Switch connected to the second reference voltage V ref , thus, the non-inverting input terminal V of the comparator 10 IP The voltage value increases by 1 / 4V ref .

[0071] Thus, the comparator 10 is switched according to the non-inverting input terminal V IP and the inverting input V IN The voltage signal of the third comparison is compared to obtain the MSB-2 bit value. The specific third comparison principle refers to the comparison principle described in the above embodiment, which will not be described in detail here.

[0072] It is not difficult to find that the embodiment of the present invention forms a common-phase high-bit split capacitor and an inverted high-bit split capacitor by two small capacitors (whose capacitance value is a unit capacitance value) connected in parallel with each other. Therefore, since the capacitance value of the unit capacitor is relatively small compared with the capacitance value of the maximum capacitor in the circuit, the matching of the analog-to-digital conversion device is relatively good. In addition, since the lower plates of the common-phase high-bit split capacitor and the inverted high-bit split capacitor are both connected to the third reference voltage GND in the initial sampling stage, after the first sampling is completed, the two ends of the common-phase high-bit split capacitor and the inverted high-bit split capacitor do not perform voltage switching, and the comparator 10 directly compares the voltage signals of its common-phase input terminal and the inverted input terminal for the first time, so no energy is consumed during the first comparison.

[0073] In the second comparison process, in order to reduce the energy consumed in the switching process, the high-bit split capacitor corresponding to the input terminal with a lower voltage after the first comparison (i.e., the same-phase high-bit split capacitor or the opposite-phase high-bit split capacitor) is connected to the first reference voltage V cm , and the first reference voltage V connected to the second highest capacitor array (i.e. the corresponding low capacitor array) cm Switch to the second reference voltage V ref Since the voltages at both ends of the capacitor array with a weight of 1 / 2 are shifted in the same magnitude and direction, that is, the voltage of the capacitor array on the same side (such as the same-phase low-position capacitor array or the opposite-phase low-position capacitor array) is reduced by half, and the voltage of the capacitor array on the other side (such as the opposite-phase low-position capacitor array or the same-phase low-position capacitor array) is increased by half, and the voltage directions of the capacitor arrays on both sides are opposite, the energy consumed by the capacitor arrays on both sides cancel each other out, and the energy consumed in the second conversion process E1 is shown in formula (1). Therefore, no energy is consumed in the second conversion process.

[0074]

[0075] In the third comparison process, the voltage at both ends of the low-order capacitor array is shifted according to the second comparison result. Since the analog-to-digital conversion device of the embodiment of the present invention uses the same-phase high-order split capacitor and the reverse-phase high-order split capacitor, it can make full use of the characteristic that the size of the highest-order capacitor array is equal to half of the total capacitor size. In the third comparison process, only the voltage value connected to the capacitor array is shifted by 1 / 2V. cm The energy consumed in the third comparison process is shown in formula (2). Therefore, the energy consumed in the third comparison process is still 0.

[0076]

[0077] Therefore, in the first three comparison processes, the differential capacitor array in the analog-to-digital conversion device of the embodiment of the present invention does not generate power consumption, thereby greatly reducing the problem of large losses in the analog-to-digital conversion process of the prior art.

[0078] In the i-th comparison stage, where i is greater than or equal to 4 and i is less than n, 8 cases are divided according to the first comparison result, the second comparison result and the (i-1)-th comparison result to switch the voltage signal on each capacitor respectively.

[0079] Assume that i=4. Before the comparator performs the fourth comparison, based on the first comparison result, the second comparison result and the third comparison result, the capacitor C P1The connected in-phase low-position selection switch is switched to the first reference voltage V cm or the third reference voltage GND, or the capacitor C of the inverting low-order capacitor array N1 The connected inverting low select switch is switched to the first reference voltage V cm Or the third reference voltage GND.

[0080] Specifically, combined Figure 3 and Figure 4 To illustrate, when the first comparison result is 1, the second comparison result is 1, and the i-1th (i.e., 3rd) comparison result is 1, the capacitor C of the same phase low-order capacitor array P1 The connected in-phase low-position selection switch is switched to connect to the third reference voltage GND, that is, the capacitor C P1 The lower plate is supplied with a first reference voltage V cm The switch is connected to the third reference voltage GND, the capacitor C P1 The voltage signal on the lower plate decreases V cm , non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0081] Combination Figure 3 and Figure 5 To illustrate, when the first comparison result is 1, the second comparison result is 1, and the i-1th (i.e., 3rd) comparison result is 0, the capacitor C of the inverting low-order capacitor array N1 The connected inverting low select switch is switched to the first reference voltage V cm That is, the capacitance C of the inverted low-order capacitor array N1 The lower plate is supplied with a second reference voltage V ref Switch connected to the first reference voltage V cm Capacitor C N1 The voltage signal on the lower plate decreases V cm , inverting input terminal V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0082] Combination Figure 3 and Figure 6 To illustrate, when the first comparison result is 1, the second comparison result is 0, and the i-1th (i.e., 3rd) comparison result is 1, the capacitor C of the same phase low-order capacitor array P1 The connected in-phase low-position selection switch is switched to the third reference voltage GND, and the capacitor C P1 The lower plate is supplied with a first reference voltage V cmThe switch is connected to the third reference voltage GND, the capacitor C P1 The voltage signal on the lower plate decreases V cm , non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0083] Combination Figure 3 and Figure 7 To illustrate, when the first comparison result is 1, the second comparison result is 0, and the i-1th (i.e., 3rd) comparison result is 0, the capacitor C of the inverting low-order capacitor array N(1) The connected inverting low select switch is switched to the first reference voltage V cm , capacitor C N1 The lower plate is supplied with a second reference voltage V ref Switch connected to the first reference voltage V cm Therefore, the capacitor C N1 The voltage on the lower plate decreases V cm , inverting input terminal V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0084] Combination Figure 3 and Figure 8 To illustrate, when the first comparison result is 0, the second comparison result is 1, and the i-1th (i.e., 3rd) comparison result is 1, the capacitor C of the same phase low-order capacitor array P1 The connected in-phase low-position selection switch is switched to the first reference voltage V cm , capacitor C P1 The lower plate is supplied with a second reference voltage V ref Switch connected to the first reference voltage V cm Therefore, the capacitor C P1 The voltage signal on the lower plate decreases V cm , non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0085] Combination Figure 3 and Fig. 9 To illustrate, when the first comparison result is 0, the second comparison result is 1, and the i-1th (i.e., 3rd) comparison result is 0, the capacitor C of the inverting low-order capacitor array N1 The connected inverting low-bit selection switch is switched to the third reference voltage GND, and the capacitor C N1The lower plate is supplied with a first reference voltage V cm The switch is connected to the third reference voltage GND, the capacitor C N1 The voltage signal on the lower plate decreases V cm , inverting input terminal V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0086] Combination Figure 3 and Fig.10 To illustrate, when the first comparison result is 0, the second comparison result is 0, and the i-1th (i.e., 3rd) comparison result is 1, the capacitor C of the same phase low-order capacitor array P1 The connected in-phase low-position selection switch is switched to the first reference voltage V cm , capacitor C P1 The lower plate is supplied with a second reference voltage V ref Switch connected to the first reference voltage V cm Therefore, the capacitor C P1 The voltage signal on the lower plate decreases V cm , non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0087] Combination Figure 3 and Fig.11 To illustrate, when the first comparison result is 0, the second comparison result is 0, and the i-1th (i.e., 3rd) comparison result is 0, the capacitor C of the inverting low-order capacitor array N1 The connected inverting low-bit selection switch is switched to the third reference voltage GND, and the capacitor C N1 The lower plate is supplied with a first reference voltage V cm The switch is connected to the third reference voltage GND, the capacitor C N1 The voltage signal on the lower plate decreases V cm , inverting input terminal V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 8V ref ).

[0088] Thus, the comparator 10 is switched according to the non-inverting input terminal V IP and the inverting input V IN The voltage signal of the third comparison is compared to obtain the MSB-i-1 (MSB-3) bit value. The specific third comparison principle refers to the comparison principle described in the above embodiment, which will not be described in detail here.

[0089] When i=n=5, before the comparator performs the fifth comparison, based on the first comparison result, the second comparison result, the third comparison result and the fourth comparison result, the capacitance C of the in-phase low-order capacitance array P0 The voltage on the lower board decreases to the first reference voltage V cm Half of C P1 The voltage on the lower board decreases or increases to the first reference voltage V cm Half of the capacitance C of the inverting low-order capacitor array N1 or C N0 The voltage on the lower board decreases to the first reference voltage V cm Half of C N1 The voltage on the lower board decreases or increases to the first reference voltage V cm half.

[0090] Specifically, Figure 4 As shown, when the first comparison result is 1, the second comparison result is 1, the third comparison result is 1, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the in-phase low-order capacitance array P1 The voltage on the lower board increases to the first reference voltage V cm half (i.e., switching from the third reference voltage GND to 1 / 2V cm ), then the non-inverting input terminal V IP The voltage value increases by 1 / 2 i-1 V ref (i.e. increase 1 / 16V ref ).

[0091] When the first comparison result is 1, the second comparison result is 1, the third comparison result is 1, and the i-1th (i.e., 4th) comparison result is 1, the capacitance C of the in-phase low-order capacitance array is P0 The voltage on the lower board decreases to the first reference voltage V cm Half of the first reference voltage V cm Adjust to 1 / 2V cm ), then the non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0092] like Figure 5 As shown, when the first comparison result is 1, the second comparison result is 1, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the inverting low-order capacitance array N1 The voltage on the lower board decreases to the first reference voltage V cm Half of the first reference voltage V cmAdjust to 1 / 2V cm ), then the inverting input terminal V IN The voltage value increases by 1 / 2 i- 1 V ref (i.e. reduce 1 / 16V ref ).

[0093] When the first comparison result is 1, the second comparison result is 1, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 1, the capacitance C of the in-phase low-order capacitance array P0 The voltage on the lower board decreases to the first reference voltage V cm Half of the first reference voltage V cm Adjust to 1 / 2V cm ), then the non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0094] like Figure 6 As shown, when the first comparison result is 1, the second comparison result is 0, the third comparison result is 1, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the in-phase low-order capacitance array P1 The voltage on the lower board increases to the first reference voltage V cm half (i.e., switching from the third reference voltage GND to 1 / 2V cm ), then the non-inverting input terminal V IP The voltage value increases by 1 / 2 i- 1 V ref (i.e. increase 1 / 16V ref ).

[0095] When the first comparison result is 1, the second comparison result is 0, the third comparison result is 1, and the i-1th (i.e., 4th) comparison result is 1, the capacitance C of the in-phase low-order capacitance array is P0 The voltage on the lower board decreases to the first reference voltage V cm Half of the first reference voltage V cm Adjust to 1 / 2V cm ), then the non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0096] like Figure 7As shown, when the first comparison result is 1, the second comparison result is 0, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the inverting low-order capacitance array N1 The voltage on the lower board decreases to the first reference voltage V cm Half of the first reference voltage V cm Adjust to 1 / 2V cm ), then the inverting input terminal V IN The voltage value is reduced by 1 / 2 i- 1 V ref (i.e. reduce 1 / 16V ref ).

[0097] When the first comparison result is 1, the second comparison result is 0, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 1, the capacitance C of the in-phase low-order capacitance array is P0 The voltage on the lower board decreases to the first reference voltage V cm half of the non-inverting input V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0098] like Figure 8 As shown, when the first comparison result is 0, the second comparison result is 1, the third comparison result is 1, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the inverting low-order capacitance array N0 The voltage on the lower board decreases to the first reference voltage V cm half of the inverting input V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0099] When the first comparison result is 0, the second comparison result is 1, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 1, the capacitance C of the in-phase low-order capacitance array P1 The voltage on the lower board decreases to the first reference voltage V cm Half of the first reference voltage V cm Adjust to 1 / 2V cm ), then the non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i-1 V ref (i.e. increase 1 / 16V ref ).

[0100] like Fig. 9As shown, when the first comparison result is 0, the second comparison result is 1, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 1, the capacitance C of the inverting low-order capacitance array N1 The voltage on the lower board increases to the first reference voltage V cm half (i.e., switching from the third reference voltage GND to 1 / 2V cm ), then the inverting input terminal V IN The voltage value increases by 1 / 2 i- 1 V ref (i.e. increase 1 / 16V ref ).

[0101] When the first comparison result is 0, the second comparison result is 1, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the inverting low-order capacitance array is N0 The voltage on the lower board decreases to the first reference voltage V cm half of the inverting input V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0102] like Fig.10 As shown, when the first comparison result is 0, the second comparison result is 0, the third comparison result is 1, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the inverting low-order capacitance array N0 The voltage on the lower board decreases to the first reference voltage V cm half of the inverting input V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0103] like Fig.11 As shown, when the first comparison result is 0, the second comparison result is 0, the third comparison result is 1, and the i-1th (i.e., 4th) comparison result is 1, the capacitance C of the in-phase low-order capacitance array P1 The voltage on the lower board decreases to the first reference voltage V cm Half of the first reference voltage V cm Adjust to 1 / 2V cm ), then the non-inverting input terminal V IP The voltage value is reduced by 1 / 2 i- 1 V ref (i.e. reduce 1 / 16V ref ).

[0104] H: When the first comparison result is 0, the second comparison result is 0, the third comparison result is 0, and the i-1th (i.e. 4th) comparison result is 1, the capacitance C of the inverting low-order capacitance array N1 The voltage on the lower board increases to the first reference voltage V cm half (i.e., switching from the third reference voltage GND to 1 / 2V cm ), then the inverting input terminal V IN The voltage value increases by 1 / 2 i-1 V ref (i.e. increase 1 / 16V ref ).

[0105] When the first comparison result is 0, the second comparison result is 0, the third comparison result is 0, and the i-1th (i.e., 4th) comparison result is 0, the capacitance C of the inverting low-order capacitance array is N0 The voltage on the lower board decreases to the first reference voltage V cm half of the inverting input V IN The voltage value is reduced by 1 / 2 i-1 V ref (i.e. reduce 1 / 16V ref ).

[0106] Thus, the comparator 10 is switched according to the non-inverting input terminal V IP and the inverting input V IN Specifically, if the non-inverting input terminal V IP The voltage at the inverting input terminal V IN If the voltage at the inverting input terminal V IN The voltage at the non-inverting input terminal V IP If the voltage is greater than 0, the LSB position is 0.

[0107] It can be seen that the embodiment of the present invention introduces 1 / 2V only in the last comparison stage (i.e., the fifth comparison stage). cm , thus reducing the accuracy requirements for the switch unit, thereby reducing the complexity of the circuit. As a result, only one end of the capacitor array (the same phase low-position capacitor array or the reverse phase low-position capacitor array) has loss, thereby significantly reducing the power consumption generated by the analog-to-digital conversion device during the data conversion process. In addition, practical studies have shown that the energy utilization rate of the analog-to-digital conversion device of the embodiment of the present invention during the data conversion process reaches 99.48%, which is 0.25-0.35% higher than the solution of the prior art. Therefore, the energy utilization rate of the analog-to-digital conversion device based on the differential capacitor array of the present invention during the data conversion process has been greatly improved.

[0108] like Fig.12As shown, taking a 10-bit SAR ADC as an example, compared with the power consumption distribution of the existing common-mode switching strategy SAR ADC, the power consumption generated by the analog-to-digital conversion device based on the differential capacitor array in the data switching process of the embodiment of the present invention is significantly lower than the power consumption generated by the common-mode switching strategy in the prior art.

[0109] It should be noted that, in the process of comparing the voltage signal collected by the comparator 10, the analog-to-digital conversion device based on the differential capacitor array of the embodiment of the present invention can replace the compared voltage signal with a current signal. The specific implementation process can refer to the implementation principle of voltage signal comparison, which will not be described in detail here. In addition, in the process of comparing the voltage signal collected by the comparator 10, the control process or control algorithm of specifically controlling multiple in-phase high-position selection switches 401, multiple inverted high-position selection switches 402, in-phase low-position selection switches 403, and switching the inverted low-position selection switch 404 to connect to the corresponding voltage in the voltage unit 60 is an implementation algorithm that is already known in the prior art and will not be described in detail here.

[0110] like Fig.13 As shown, an embodiment of the present invention further provides an analog-to-digital conversion method based on a differential capacitor array, comprising:

[0111] Step 1302 : Control the switch selection unit to switch and connect to the corresponding voltage unit 60 .

[0112] Step 1304: Collect signals from the in-phase input terminal and the inverting input terminal of the comparator 10. The in-phase input terminal of the comparator 10 is connected to the in-phase low-order capacitor array 201 and a plurality of in-phase high-order split capacitors 202. The capacitance value of the in-phase low-order capacitor array 201 is C Pm =2 m-1 C, C P0 = C, the size of each common-phase high-bit split capacitor 202 is 2 n-5 C, the inverting input terminal of the comparator 10 is connected to the inverting low-order capacitor array 301 and a plurality of inverting high-order split capacitors 302, and the capacitance value of the inverting low-order capacitor array 301 is C Nm =2 m-1 C, C N0 = C, the size of each inverting high-bit split capacitor 302 is 2 n-5 C. Where m∈[1,n-4], n is greater than or equal to 5.

[0113] Step 1306. Compare the signal at the non-inverting input terminal with the signal at the inverting input terminal by the comparator 10 to output a digital signal corresponding to the signal at the non-inverting input terminal or a digital signal corresponding to the signal at the inverting input terminal.

[0114] The switch selection unit is respectively connected to the in-phase low-order capacitor array 201, multiple in-phase high-order split capacitors 202, the inverted low-order capacitor array 301, and multiple inverted high-order split capacitors 302, so as to adjust the voltage value on each capacitor respectively through the switch selection unit.

[0115] The analog-to-digital conversion method based on the differential capacitor array of the embodiment of the present invention is to switch the switch selection unit to the corresponding voltage unit 60, and then collect the signals of the in-phase input terminal and the inverting input terminal of the comparator 10, and compare the signal of the in-phase input terminal with the signal of the inverting input terminal through the comparator 10 to output a digital signal corresponding to the in-phase input terminal signal or a digital signal corresponding to the inverting input terminal signal. Since the in-phase input terminal of the comparator 10 is connected to the in-phase input terminal of the comparator 10 with a capacitance value satisfying 2 m-1 The capacitors of C form a low-order capacitor array 201 with the same phase, and the capacitance value is 2 n-5 C has multiple in-phase high-bit split capacitors 202, and the inverting input terminal of the comparator 10 is connected to a capacitor with a capacitance value satisfying 2 m-1 The inverting low-order capacitor array 301 is composed of capacitors C, and the capacitance value is 2 n-5 C has multiple inverting high-order split capacitors 302. Therefore, it is not difficult to obtain that the total capacitance value of the embodiment of the present invention is 2 n-2 C, for example, in a 5-bit analog-to-digital conversion device, the total capacitance value is 8C, while the total capacitance value of the switch conversion scheme based on the differential capacitance matrix in the prior art is 32C or 16C. Therefore, the total capacitance value in the embodiment of the present invention is greatly reduced, thereby effectively reducing the loss generated by the analog-to-digital conversion process.

[0116] Furthermore, since the multiple in-phase high-bit split capacitors 202 connected to the in-phase input terminal of the comparator 10 are connected in parallel, and the multiple inverting high-bit split capacitors 302 connected to the inverting input terminal are connected in parallel, compared with the solution of the MSB bit capacitor array (i.e., high-bit capacitor array) formed by the capacitor matrix in the prior art, the embodiment of the present invention can greatly reduce the capacitance value of the MSB bit through the in-phase high-bit split capacitors 202 connected in parallel and the inverting high-bit split capacitors 302 connected in parallel, thereby further reducing the power consumption generated by the analog-to-digital conversion.

[0117] It should be noted that the specific implementation process of the analog-to-digital conversion method based on the differential capacitor array in the embodiment of the present invention is the same as the implementation process of the analog-to-digital conversion device based on the differential capacitor array described in any of the above embodiments. Therefore, the part of the analog-to-digital conversion method based on the differential capacitor array in the embodiment of the present invention that is the same as the specific implementation principle of the analog-to-digital conversion device based on the differential capacitor array can be referred to the analog-to-digital conversion device based on the differential capacitor array described in any of the above embodiments, and will not be described in detail here.

[0118] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

[0119] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0120] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An analog-to-digital conversion device based on a differential capacitor array, characterized in that: include: Comparator; A common-phase low-order capacitor array and a plurality of common-phase high-order split capacitors connected to the common-phase input terminal of the comparator, wherein the capacitance value of the capacitor in the common-phase low-order capacitor array is C Pm =2 m-1 C, the capacitance value of each common-phase high-bit split capacitor is 2 n-5 C; An inverting low-order capacitor array and a plurality of inverting high-order split capacitors connected to the inverting input terminal of the comparator, wherein the capacitance value of the capacitor in the inverting low-order capacitor array is C Nm =2 m-1 C, the capacitance value of each inverting high-bit split capacitor is 2 n-5 C; A switch selection unit connected to the in-phase low-order capacitor array, the multiple in-phase high-order split capacitors, the inverted low-order capacitor array, and the multiple inverted high-order split capacitors, respectively, for adjusting the voltage value on each capacitor; as well as A successive approximation logic control circuit connected to the output terminal of the comparator, used for controlling the switch selection unit to be connected to the corresponding voltage unit; Where m∈[1,n-4], n is greater than or equal to 5, C P0 =C, C N0 =C; the number of the multiple in-phase high-bit split capacitors and the multiple inverted high-bit split capacitors are both two, and the two in-phase high-bit split capacitors are connected in parallel, and the two inverted high-bit split capacitors are connected in parallel; The voltage unit includes a first reference voltage V cm , the second reference voltage V ref and a third reference voltage GND; Before the comparator performs the first comparison, the two in-phase high-bit selection switches and the two inverted high-bit selection switches are connected to the third reference voltage GND, and the in-phase low-bit selection switch and the inverted low-bit selection switch are connected to the first reference voltage V cm ; Before the comparator performs the second comparison, based on the first comparison result, two inverting high-position selection switches or two in-phase high-position selection switches are switched to connect to the first reference voltage V cm , and the inverting low-position selection switch or the non-inverting low-position selection switch is switched to connect to the second reference voltage V ref ; Before the comparator performs the third comparison, based on the first comparison result and the second comparison result, the two inverting high-bit selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm , two in-phase high-position selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm ; Among them, n = 5, the in-phase low-position capacitor array consists of capacitor C P1 and capacitor C P0 The inverting low-order capacitor array consists of capacitor C N1 and capacitor C N0 constitute; The analog-to-digital conversion device is a 10-bit SAR ADC.

2. The analog-to-digital conversion device according to claim 1, characterized in that: The switch selection unit is composed of two same-phase high-order selection switches connected correspondingly to two same-phase high-order split capacitors, two opposite-phase high-order selection switches connected correspondingly to two opposite-phase high-order split capacitors, a same-phase low-order selection switch connected correspondingly to each capacitor in the same-phase low-order capacitor array, and an opposite-phase low-order selection switch connected correspondingly to each capacitor in the opposite-phase low-order capacitor array.

3. The analog-to-digital conversion device according to claim 1, characterized in that: The total capacitance of the analog-to-digital conversion device is 2 n-2 C.

4. The analog-to-digital conversion device according to claim 1, characterized in that: When the first comparison result is 1, the two inverting high-bit selection switches are switched to the first reference voltage V cm , the inverting low select switch is connected to the second reference voltage V ref ; When the first comparison result is 0, the two in-phase high-bit selection switches are switched to the first reference voltage V cm , the in-phase low position selection switch is switched to connect to the second reference voltage V ref .

5. The analog-to-digital conversion device according to claim 1, characterized in that: When the first comparison result is 1 and the second comparison result is 1, the two inverting high-bit selection switches are switched to connect to the second reference voltage V ref ; When the first comparison result is 1 and the second comparison result is 0, the two in-phase high-bit selection switches are switched to the first reference voltage V cm ; When the first comparison result is 0 and the second comparison result is 1, the two inverting high-bit selection switches are switched to the first reference voltage V cm ; When the first comparison result is 0 and the second comparison result is 0, the two same-phase high-bit selection switches are switched to connect to the second reference voltage V ref .

6. The analog-to-digital conversion device according to claim 4 or 5, characterized in that: Before the comparator performs the fourth comparison, based on the first comparison result, the second comparison result and the third comparison result, the capacitance C of the same-phase low-order capacitance array is P1 The connected in-phase low-position selection switch is switched to the first reference voltage V cm or the third reference voltage GND, or the capacitor C of the inverting low-order capacitor array N1 The connected inverting low select switch is switched to the first reference voltage V cm or a third reference voltage GND; Before the comparator performs the fifth comparison, based on the first comparison result, the second comparison result, the third comparison result and the fourth comparison result, the capacitance C of the in-phase low-order capacitance array P0 The voltage on the lower board decreases to the first reference voltage V cm Half of C P1 The voltage on the lower board decreases or increases to the first reference voltage V cm Half of the capacitance C of the inverting low-order capacitor array N1 or C N0 The voltage on the lower board decreases to the first reference voltage V cm Half of C N1 The voltage on the lower board decreases or increases to the first reference voltage V cm half.

7. An analog-to-digital conversion method based on a differential capacitor array, implemented based on the analog-to-digital conversion device according to any one of claims 1 to 6, characterized in that: include: Control the switch selection unit to switch and connect to the corresponding voltage unit; The signals of the in-phase input terminal and the inverting input terminal of the comparator are collected. The in-phase input terminal of the comparator is connected to the in-phase low-order capacitor array and multiple in-phase high-order split capacitors. The capacitance value of the in-phase low-order capacitor array is C Pm =2 m-1 C, m∈[1,n-4], n is greater than or equal to 5, C P0 = C, the size of each common-phase high-bit split capacitor is 2 n-5 C, the inverting input terminal of the comparator is connected to an inverting low-order capacitor array and a plurality of inverting high-order split capacitors, and the capacitance value of the inverting low-order capacitor array is C N(m) =2 m -1 C, C N0 = C, the size of each inverting high-bit split capacitor is 2 n-5 C; Comparing the signal at the in-phase input terminal with the signal at the inverting input terminal by a comparator to output a digital signal corresponding to the signal at the in-phase input terminal or a digital signal corresponding to the signal at the inverting input terminal; The switch selection unit is respectively connected to the in-phase low-order capacitor array, the multiple in-phase high-order split capacitors, the inverted low-order capacitor array, and the multiple inverted high-order split capacitors, so as to adjust the voltage value on each capacitor respectively through the switch selection unit; The number of the multiple in-phase high-bit split capacitors and the number of the multiple inverted high-bit split capacitors are both two, and the two in-phase high-bit split capacitors are connected in parallel, and the two inverted high-bit split capacitors are connected in parallel; The voltage unit includes a first reference voltage V cm , the second reference voltage V ref and a third reference voltage GND; Before the comparator performs the first comparison, the two in-phase high-bit selection switches and the two inverted high-bit selection switches are connected to the third reference voltage GND, and the in-phase low-bit selection switch and the inverted low-bit selection switch are connected to the first reference voltage V cm ; Before the comparator performs the second comparison, based on the first comparison result, two inverting high-position selection switches or two in-phase high-position selection switches are switched to connect to the first reference voltage V cm , and the inverting low-position selection switch or the non-inverting low-position selection switch is switched to connect to the second reference voltage V ref ; Before the comparator performs the third comparison, based on the first comparison result and the second comparison result, the two inverting high-bit selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm , two in-phase high-position selection switches are switched to connect to the second reference voltage V ref Or the first reference voltage V cm ; Among them, n = 5, the in-phase low-position capacitor array consists of capacitor C P1 and capacitor C P0 The inverting low-order capacitor array consists of capacitor C N1 and capacitor C N0 constitute; The analog-to-digital conversion device is a 10-bit SAR ADC.

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