Maintaining correct time when transferring counter values ​​between clock domains

Abstract

To reduce errors in the transfer of time from one clock domain to another, a first free-running counter is incremented using a first clock signal. A free-running second counter is incremented using a second clock signal, the second clock signal being asynchronous with the first clock signal. The first counter is sampled at selected times based on a predetermined phase relationship between the first clock signal and the second clock signal to produce a sampled first counter value. The second counter is corrected based on the sampled first counter value.

Description

Technical Field

[0001] The present disclosure relates to the transmission of accurate time information between different clock domains. Background Art

[0002] Network time is an important resource utilized by many applications, such as location accuracy within a house / office, location accuracy in urban areas, and time-based dispute resolution in financial markets. Standards that control the transmission and use of reference time (including but not limited to IEEE 802.11b, IEEE 1588-2008 standards) have accuracy limits on the errors introduced at each network node. The scaling of the number of nodes in the network using this standard depends on the accuracy with which the reference time can be transmitted. The reference time is usually propagated in the network via data packets. Another clock that is asynchronous with the clock that generates the reference time samples the reference time contained in the data packet. Accurately transmitting the reference time over the data network using asynchronous clocks is the main source of error in time transmission, and limiting (or eliminating) this error is an important requirement for network performance and expansion.

[0003] In systems based on IEEE 1588, for example, the reference clock updates the time in the master counter. Figure 1 , with a period (T m ) of the master clock 101 every T m The time unit updates the main counter 103. When using a clock with a period T s Another clock (slave clock) 105 samples the contents of the master counter 103 and counts every T s When the time unit is copied into the storage element 107, the "time" recorded by the slave clock 105 may be wrong due to the inequality between the master clock cycle and the slave clock cycle.

[0004] Figure 2 Assume that the master counter value 201 is updated every 8 ns by the master clock (T m =8ns), the storage element 107 is updated every 3ns by the slave clock 105. The storage value of the storage element 107 is shown at 203, and it can be seen that there is a dynamic error of 3ns.

[0005] Another source of error is due to the master clock and the slave sampling clock having different periods. The different periods can cause the "phase" difference between the master clock and the slave clock to be variable. Where t is the absolute time, ω m The period is T m The angular clock frequency of the master clock, ω s The period is T s The angular clock frequency of the slave clock, is the constant phase difference between the clocks at time t = 0. The phase difference also causes errors in the transmission of the counter value to the storage element. Figure 3 , if the master counter 103 is updated at the rising edge 301 of the master clock at time t=Tm, then the counter value is copied to the storage element 107 at the rising edge 303 of the clock 105 at time t=Tm+ΔT, where ΔT is the phase difference, which can be positive or negative. Therefore, the time transfer of a counter driven from one (master) clock source using another clock will result in copied time errors, which are caused by the difference in the nominal periods of these clocks and the possible phase difference between these clocks. Summary of the invention

[0006] To reduce errors in the transfer of time from one clock domain to another, in one embodiment, a method includes incrementing a free-running first counter using a first clock signal. Incrementing a free-running second counter using a second clock signal, the second clock signal being asynchronous with the first clock signal. Sampling the first counter at selected times based on a predetermined phase relationship between the first clock signal and the second clock signal to produce a sampled first counter value. Correcting the second counter based on the sampled first counter value.

[0007] In another embodiment, a device includes a first counter that increments a first counter value in response to a first clock signal, the first clock signal having a first frequency. A second counter that increments a second counter value in response to a second clock signal that is asynchronous with the first clock signal, the second clock signal having a second frequency. A sampling circuit samples the first counter value at selected times and generates a sampled first counter value at each selected time, the selected time occurring at a periodic predetermined phase alignment between the first clock signal and the second clock signal. The second counter value is adjusted based on the sampled first counter value.

[0008] In another embodiment, a method includes generating a first counter value in a first counter using a first clock signal to increment the first counter. A second counter generates a second counter value using a second clock signal. The first counter value is sampled at a selected time to generate a sampled first counter value, the selected time occurring at a predetermined phase relationship between the periodically occurring first clock signal and a second clock signal. An error is generated indicating a difference between the sampled first counter value and the sampled second counter value. The second counter value is adjusted according to the error by increasing or decreasing one or more increment values ​​used to generate the second counter value, thereby eliminating the error in the second counter value within one or more clock cycles of the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0010] Figure 1 A system is shown in which a master counter is updated with a reference clock and is sampled by a different clock.

[0011] Figure 2 Shown with Figure 1 The dynamic errors associated with the system.

[0012] Figure 3 Another source of error associated with sampling the master timing reference based on the phase difference between the master clock and the sampling clock is shown.

[0013] Figure 4 A high-level block diagram schematically illustrates an implementation of reducing errors in time transfer from one clock domain to another.

[0014] Figure 5 Some additional details of an embodiment of reducing errors in the transfer of time from one clock domain to another are shown.

[0015] Figure 6 Shown with Figure 5 A timing diagram associated with an implementation scheme of the present invention.

[0016] Figure 7 Graphically shows the Figure 4-6 The illustrated embodiment provides a solution.

[0017] Figure 8 A high-level block diagram schematically illustrates an implementation for transferring time of day (ToD) from a master clock domain to another clock domain clocked by a Synchronous Ethernet (Synce) clock.

[0018] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0019] Embodiments herein address a key source of error in hardware design that limits the accuracy of time information transmitted using various network protocols. Embodiments exploit properties of a reference time counter value and a clock. The time of day count value is monotonic and increments at a constant count rate set by the nominal clock period of the reference time clock. The reference time clock (also referred to herein as the master clock) and the data network clock (also referred to herein as the slave clock) will periodically have a phase difference that is a multiple of 2π. If a faster clock can be used to sample a slower clock, this periodic occurrence can be located. Instead of, for example, Figure 1 The slave clock shown "samples" the master time counter value to the storage element 107, and the embodiment implements the time counter in the slave clock domain. When a periodic event occurs, the master counter value is sampled. Then, by comparing the sampled master counter value with the slave counter value when the periodic event occurs, the error in the slave counter value can be calculated. The error can then be corrected by increasing or decreasing the count increment value in the slave counter (adjusting the slope of the time rise). Therefore, the slave counter can be synchronized with the reference time (or master control) counter, and its error is limited by the fastest clock cycle in the system. For example, the clock derived from the global positioning system (GPS) may be as high as 1GHz in the IEEE-1588 system, so the error can be limited to + / -1ns.

[0020] Figure 4 A high-level block diagram of a clock domain crossing logic block 400 is shown, which conceptually illustrates an embodiment of reducing errors in the transfer of time from one clock domain to another. A master counter 401 is clocked by a master clock (Master CLK) 402 and provides a master count 403 that is updated every TM unit of time, where TM is the period of the master clock. The nominal period values ​​406 and 408 of the master and slave clocks are input to a pulse generator (Pulse Gen) circuit 409. The pulse generator circuit 409 generates a signal for identifying one aspect, necessary but not sufficient to identify a timing event based on the nominal period of the master and slave clocks (the master and slave clocks have a phase difference of a multiple of 2π). Once the timing event is found (using another calibration operation described below), the contents of the storage element 404 are used to update the slave counter 411. In an embodiment, rather than directly loading the slave counter, the value of the slave counter is adjusted when the master count is sampled based on the difference between the sampled master count and the slave count. The slave counter 411 updates its counter value at a predetermined increment every TS time unit, where TS is the period of the slave clock 415. The slave counter 411 provides a slave count output 417. The slave counter 411 is updated by the slave clock on each TS time increment between adjustments to the slave counter value based on the master count.

[0021] As previously noted, there are several sources of error in sampling the master count in the slave clock domain. To account for errors caused by different periods of the master and slave clocks, the pulse generator generates a first calibration pulse every K×LCM{TM,TS}, where K is an integer greater than or equal to 1 and LCM{} is a function that returns the least common multiple of TM and TS. The waiting K×LCM{TM,TS} time units ensures that the nominal phase difference between TM and TS is always a multiple of 2π and accounts for the first source of error in time transfer caused by the master clock period and the master clock period difference. The nominal phase difference between the master and slave clocks repeats every K×LCM time units.

[0022] The use of the nominal phase difference determined by increasing K×LCM using a second calibration routine ensures that the master count is accurately sampled when the phase difference between the slave and master clocks is at a time event where the phase difference of the clocks is a multiple of 2π, thereby eliminating errors caused by phase differences between the clocks due to jitter in one or both of the two clocks. Jitter present in the system may cause the edge of the master clock (or slave clock) to lag or lead the other clock when the first calibration operation has been completed based on K×LCM time units. Remember that one of the clocks (the master clock or the slave clock) is counting the time interval defined by K×LCM. Refer again to Figure 3 , even with the first calibration mechanism and using the nominal value of two clock periods, a phase misalignment ΔT may result due to jitter. This phase error can cause an error when sampling the main count. Therefore, in addition to calibrating the nominal period difference of the clocks, a second calibration routine is performed.

[0023] The operation of the second calibration routine is as follows: After the first calibration routine counts K×LCM time units, the master counter value scaled to reflect the absolute time is compared with the TS counter value scaled to reflect the absolute time. The count of the clock is scaled to time, time = nominal period x count value, where the nominal period is the scale factor for setting the absolute time. The counter value is sampled so that the sampling point solves the jitter that may appear in the clock signal. This is done by the faster clock looking for a specific edge of the slower clock. For example, if the slave clock is a faster clock, the slave clock samples the master clock to find the rising edge. When the rising edge is detected, indicating that both counters reflect the same absolute time, a second calibration signal is generated, which samples and compares the master counter value and the slave counter value. The slave count is then corrected based on the difference between the sampled master counter and slave counter values. As further explained herein, the slave counter value can be adjusted in a variety of ways, including loading the sampled master counter value into the slave counter. After generating the second calibration signal, the pulse generator sends out the next pulse corresponding to the first calibration operation (K×LCM{TM, TS}) time unit. The second calibration operation ensures that the time transfer from the master clock domain to the slave clock domain takes into account the jitter of the master clock signal and the slave clock signal.

[0024] Figure 5 A more detailed high-level block diagram of an embodiment for transferring a master count from one clock domain to another is shown. Figure 6 Shows the description Figure 5 A timing diagram of the operation of an embodiment of the present invention is shown. Figure 5 and Figure 6 , the master clock (MasterCLK) 501 provides a clock to the master counter 503 to increase the master counter by a predetermined increment. Figure 6 In the timing diagram of , the master clock increments the master count by 8 (128, 136, ..., 216). In the example shown, the master clock runs at a frequency of 125MHz (a period of 8ns). The slave clock (Slave CLK) 507 provides a clock to the slave counter 509, and the average increment in the timing diagram is 6.4ns (average frequency of 156.25MHz). Therefore, the increment of the slave counter varies between 6 and 7 to achieve an average increment of 6.4ns. In five slave clock cycles, the slave counter uses three 6ns increments and two 7ns increments to achieve an average increment of 6.4ns. It can be seen that in Figure 6 As can be seen in the timing diagram of , where the slave count is updated between 135 and 173, with an average increment of 6.4ns. As mentioned above, counting K×LCM{TM,TS} time units is used as the first calibration step when determining the correct time to transfer the master count to the slave count. Figure 6In the embodiment shown, LCM{8ns, 6.4ns}=32ns, and K=5. Figure 5 In the example timing diagram, the calibration counter 511 counts the calibration count (CAL COUNT) K×LCM. In the embodiment shown in the timing diagram, K×LCM=160ns. Various values ​​of K×LCM 510 can be loaded into the calibration counter 511 as required by the particular system. In the example timing diagram, the first calibration operation is completed when the calibration counter reaches 25, which in the embodiment shown is 160ns or 25 cycles of the slave clock. This is equivalent to Figure 4 The first calibration pulse associated with this clock. As can be seen from the timing diagram, this occurs when the calibration count (CAL COUNT) changes from 24 to 25. Since the calibration counter 511 starts counting from 0, the 25th 6.4ns cycle will be completed at the end of the 24th count. In the illustrated embodiment, the calibration counter is clocked on the falling edge of the slave clock. Once the calibration count reaches 25, the calibration count will remain at 25 until a second calibration operation ensures that the master clock and the slave clock are aligned as required to account for jitter in the clock signals. The calibration counter issues a first calibration pulse ((First CalPulse)) 515 to indicate that the calibration count has reached K×LCM time units. The calibration counter will maintain a value of 25 until the next calibration operation has determined the time to sample and compare the master count and the slave count, thereby transferring the time from the master clock domain to the slave clock domain.

[0025] When the calibration count reaches K×LCM, it causes the next calibration operation of the master and slave clocks to begin. The faster clock (in this case, the slave clock) samples the slower clock (in this case, the master clock). The time sample register (TIME SAMPLE) 516 uses a two-bit register to track the sampling of the master clock, where the most significant bit in the two-bit register represents the earliest sample. At each falling edge of the slave clock, the master clock is sampled and its value is stored in the time sample register. For example, when the time sample register is "3", it means that the master clock was sampled as a high level in each of the last two samples. The control logic is waiting for a transition from 0 to 1, indicating that the master clock has transitioned from a low level to a high level, thereby ensuring that sampling and comparison operations do not occur in the wrong half cycle. When the calibration count is 25, the control logic samples the master clock at 179ns, resulting in the sampling of the high level master clock (the previous sampled value was 0), indicating that the master clock has transitioned from 0 to 1. This is a further calibration operation, which is required in order to properly align the master and slave clocks to transfer the master count from the master clock domain to the slave clock in the slave clock domain. This results in a second calibration pulse (Second Cal Pulse) 517, which causes the master count and the slave count to be sampled and compared in the sample counter and comparison logic 519. Figure 6 In the timing diagram shown, when the master count and the slave count are sampled and compared, the master count and the slave count are 176 and 173, respectively, or a positive difference of 3. The polarity of the error is reflected in the positive error register (POS ERR REG), which is part of the sampling and comparison logic 519, in Figure 5 , not separately shown in FIG. Then, the calibration operation has reached two calibration standards, and the operation is considered to be completed at the positive edge (rising edge) of the slave clock at 179ns. The calibration completion (CAL DONE) signal indicates the end of the second calibration operation, and the calibration counter 511 restarts the calibration count (CAL COUNT) from 0 at the next negative edge (falling edge) of the slave clock to determine the next occurrence of K×LCM{TM, TS}. In other words, the calibration counter is reset from 25 and starts counting at the negative edge of the slave clock (during the slave count 180).

[0026] The error register (ERROR REG) 521 contains the remaining error to be corrected in the slave counter. Initially, as can be seen from the rising edge of the slave clock 179ns later, the error register 521 is loaded with 3, reflecting the sample difference between the master count and the slave count. To reduce the difference, if the master count is greater than the slave count (positive error), the slave counter increment is adjusted upward in the normal increment plus error logic 523 to effectively speed up the slave count, and if the master count is less than the slave count (negative error), the slave counter increment is adjusted downward to effectively slow down the slave count. Figure 6 In the illustrated embodiment, the slave counter increments by one between 180 and 187, by one between 187 and 194, and by one between 194 and 202, at which point the error register becomes zero, indicating that the error in the slave count has been corrected for that particular K×LCM period. Thus, the difference between the master count and the slave count is corrected every K×LCM time units. The master count is effectively transferred to the slave counter every K×LCM time period.

[0027] Note that Figure 6 In the timing diagram shown, once the calibration count reaches 25, indicating that the calibration operation has begun, the positive error register (POS ERR REG) and the negative error register (NEG ERR REG) begin sampling the error. In other embodiments, the polarity of the error is tracked only during the second calibration operation. Figure 6 , the first negative edge of the slave clock that occurs after the calibration count reaches 25 samples the difference or negative error of 2 between the master count 152 and the slave count 154. Subsequently, the next negative edge of the slave clock shows a difference of 0 (160 vs. 160). After the master clock transitions from 0 to 1, the falling edge of the slave clock shows a difference of 3 (176 vs. 173).

[0028] Note that while the error is adjusted by one LSB of the slave counter in the illustrated embodiment, other embodiments may adjust the increment of the slave counter by other amounts. For example, if the magnitude of the error is high enough, then in an embodiment, the increment of the slave counter is adjusted by 2 or more for each cycle of the slave clock. In other embodiments, the error is corrected within one cycle by adjusting the slave clock increment by the magnitude of the error. Alternatively, the sampled master count may be loaded into the slave counter to achieve the adjustment.

[0029] Note that in an embodiment, if the quantization error is acceptable, the value K×LCM{TM,TS} may be a fractional value. Thus, an embodiment may multiply 8ns by 6.4ns and use the fractional K×LCM value as the lowest common multiple.

[0030] although Figure 6 The operation for correcting positive errors is shown, but the operation for negative errors is the same, except that as described above, correction of the slave counter results in decreasing the increment to slow down the counting of the slave counter.

[0031] Figure 7 Graphically shows the Figure 4-6 The solution provided by the embodiment shown is as follows. Assume that the main counter value 701 is updated every 8ns, that is, T m = 8ns, and the slave counter value 703 is updated every 3ns. Figure 2 , the storage element into which the master counter is copied has a dynamic error of 3ns. The deviation (error) of the slave counter can be significantly reduced to less than 1% of the slave period from the period of the master clock or the slave clock (whichever is smaller), by running the master counter and the slave counter simultaneously and periodically correcting the slave counter based on the difference between the master counter and the slave counter. The source of the error is jitter or random noise of the slave clock relative to the master clock. Note that the slopes of the master counter value and the slave counter values ​​701 and 703 are slightly different, indicating that the rates of tracking time are different. The difference in slope is the error that is being corrected. Periodically, approximately every KxLCM{TS,TM} time units, the slave counter is adjusted to keep the error well below Figure 1 and 2 The dynamic error provided by the method is below.

[0032] Figure 8 is a high-level block diagram that conceptually illustrates an embodiment of a cross-domain crossbar block 800 that reduces errors in transferring a time of day (ToD) time value from one clock domain to another. Figure 8802. The ToD count 801 is available as an input to the clock domain crossing block 800. The pulse generator generates 803 a "high" pulse every "N" system clock cycles. The high pulse indicates the end of the first calibration operation. N depends on the system clock frequency (fsys) and the slave clock frequency, in this case, the synchronous Ethernet (synce) frequency (fsynce). The following table shows examples of N for different clock frequencies, including the system clock (fsys) and the synchronization clock (feth). N is determined based on K×LCM{Tfsys, Tfsynce}.

[0033]

[0034]

[0035] After the N system clocks generate the first pulse, the second calibration operation will ensure that the system clock and the synchronization clock are aligned as required, and the sampling and comparison operations described above are performed. After the sampling and comparison operations incorporated into block 805 are completed, the synchronization counter 807 is adjusted based on the difference between the synchronization counter and the sampled ToD. The synchronization counter provides an 80-bit synchronous system timer output.

[0036] The point in time when the phase difference between the system clock and the synchronization clock is cleared to zero is repeated every N cycles. The accumulation of the time interval error (TIE) due to the synchronization clock frequency error is limited as follows:

[0037] TIE ETH =(Δfsynce / fsynce)*N / fsys, where Δfsynce represents the difference between the nominal fysnce value and the actual fsynce value.

[0038] Assume that the maximum jitter of the synchronous clock is 100 parts per million, N is 80, and fsys is 125MHX.

[0039] TIE ETH_MAX =(Δfsynce / fsynce) max ×(N / fsys) max =100ppm*0.64us=64ps.

[0040] Therefore, in the time period between calibration operations occurring every approximately K×LCM{} time units, it can be seen that the error accumulation is not significant. Figure 8The error of the method shown is at least 2.5ns and up to 8ns. An 8ns error occurs when the sync clock edge (156.25MHz) is just behind the system clock edge (125MHz), so the correct time count of 8ns (the clock period of the system clock) is missed. In the same situation, but when the system clock is 1GHz and the sync clock is 390.625MHz, a 2.5ns error occurs. Another source of error is that the sync clock and the system clock are not synchronized. The sync clock period is not always a fixed number (for example, 6.4ns for 156.25MHz), and the change in period also causes the sync clock to "sample" the wrong count value from the time counter driven by the system clock. Therefore, this method provides a solution that is 35 times higher or even better than existing methods in reducing time transmission errors between different time domains.

[0041] Thus, various aspects related to maintaining accurate time when transferring a reference time between two clock domains have been described. Other variations and modifications may be made to the embodiments disclosed herein based on the descriptions made herein without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method of keeping correct time, include: incrementing a free-running first counter using a first clock signal; incrementing a free-running second counter using a second clock signal, the second clock signal being asynchronous with the first clock signal; generating a sampling pulse at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal, the selected time being determined at least in part by a first time period that has elapsed since a previously selected time multiplied by K, the first time period being a least common multiple of a first period associated with the first clock signal and a second period associated with the second clock signal, wherein K is an integer greater than or equal to 1; sampling the first counter in response to the sampling pulse and generating a sampled first counter value; as well as The second counter is corrected based on the sampled first counter value.

2. The method according to claim 1, further comprising: include: generating an error indicative of a difference between the sampled first counter value and the sampled second counter value; as well as One or more increment values ​​used by the second counter are adjusted during one or more cycles of the second clock signal to adjust the second counter according to the error to correct the second counter based on the sampled first counter value.

3. The method according to claim 2, further comprising: include: responsive to the sampled second counter value being less than the sampled first counter value, increasing the one or more increment values ​​for one or more cycles of the second clock signal to thereby remove the error from the second counter; as well as In response to the sampled second counter value being greater than the sampled first counter value, the one or more increment values ​​for one or more cycles of the second clock signal are reduced to eliminate the error from the second counter.

4. The method according to claim 1, further comprising: include: The selected time is further determined based on further calibration of the first clock signal and the second clock signal after the first time period.

5. The method according to claim 4, in, The further calibration also includes determining when, after the first time period, the valid edge of the slower clock signal is between two valid edges of the faster clock signal, the first clock signal or the second clock signal is the faster clock signal, and the other of the first clock signal and the second clock signal is the slower clock signal.

6. The method according to claim 1, in, Also included is restarting a first time period counter in response to each occurrence of the selected time, the first time period counter being used to count the first time period.

7. The method according to claim 1, further comprising: include: the first counter increments a first counter value by a first average increment of a first number of periods of the first clock signal; and The second counter increases a second counter value by a second average increment over a second number of cycles of the second clock signal.

8. The method according to claim 7, in, The first average increment used to increment the first counter is different from the second average increment used to increment the second counter.

9. A device for keeping correct time, include: a first counter that increments a first counter value in response to a first clock signal, the first clock signal having a first frequency; a second counter that increments a second counter value in response to a second clock signal that is asynchronous with the first clock signal, the second clock signal having a second frequency; and a sampling circuit for generating corresponding sampling pulses to sample the first counter value at selected times and generating a sampled first counter value at each selected time, each selected time being based in part on a nominal phase alignment occurring between the first clock signal and the second clock signal, each selected time is determined at least in part based on an elapsed first time interval associated with a least common multiple of a first period associated with a first frequency and a second period associated with a second frequency multiplied by K, K being an integer greater than or equal to 1, the end of the first time interval indicating a nominal phase alignment between the first clock signal and the second clock signal, The second counter value is adjusted based on the sampled first counter value.

10. The device according to claim 9, in, The first counter and the second counter are free running counters.

11. The device according to claim 9, in, The sampled first counter value is loaded into the second counter, thereby adjusting the second counter value based on the sampled first counter value.

12. The device according to claim 9, further comprising: include: a comparison circuit for comparing the sampled first counter value and the sampled second counter value and generating an error indicative of a difference between the sampled first counter value and the sampled second counter value; as well as for generating one or more increment values ​​for the second counter value, the one or more increment values ​​being adjusted according to the error to remove the error from the second counter value, and adjusting the second counter value based on the sampled first counter value, In response to the second counter value being less than the sampled first counter value, the one or more increment values ​​are increased, and in response to the second counter value being greater than the sampled first counter value, the one or more increment values ​​are decreased.

13. The device according to claim 9, in, The second counter value is adjusted over a plurality of cycles of the second clock signal, the number of cycles being one or more and the number of cycles being based at least in part on a magnitude of a difference between the sampled first counter value and the sampled second counter value.

14. The device according to claim 9, in, The second counter value is adjusted based on a sign and a magnitude of a difference between the sampled first counter value and the sampled second counter value.

15. The device according to claim 9, in, Each selected time is determined according to a further calibration operation of calibrating the first clock signal and the second clock signal after the first time interval.

16. The device according to claim 15, in, The further calibration operation determines when an active edge of the first clock signal occurs between two active edges of the second clock signal after the first time interval has elapsed.

17. A method of keeping correct time, include: generating a first counter value in the first counter using the first clock signal to increment the first counter; generating a second counter value in the second counter using the second clock signal to increment the second counter; generating a sampling pulse at a selected time; determining the selected time for sampling the first counter and the second counter based at least in part on a first time interval that has elapsed since a previously selected time multiplied by K, the first time interval being a least common multiple of a first period associated with the first clock signal and a second period associated with the second clock signal, wherein K is an integer greater than or equal to 1; determining the selected time further based on detecting an edge of a slower clock signal after the first time interval has elapsed, the slower clock signal being the first clock signal or the second clock signal; sampling the first counter in response to the sampling pulse at the selected time and generating a sampled first counter value; sampling the second counter in response to the sampling pulse at the selected time and generating a sampled second counter value; generating an error indicative of a difference between the sampled first counter value and the sampled second counter value; as well as The second counter value is adjusted according to the error by increasing or decreasing one or more increment values ​​used to generate the second counter value, thereby eliminating the error in the second counter value within one or more clock cycles of the second clock signal.

18. The method according to claim 17, in, Detecting the edge includes: A determination is made as to when an active edge of the slower clock signal is between two active edges of a faster clock signal of the first clock signal and the second clock signal.

19. The method according to claim 18, in, Detecting the edge further comprises: After the first time interval has elapsed, it is determined when an active edge of the slower clock signal is between the two active edges.

20. The method of claim 18, further comprising using a time sampling register to determine when an active edge of the slower clock signal is between two active edges of the faster clock signal.

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