Storage device and working method thereof

Abstract

A novel storage device is provided. A first cell array having a plurality of storage cells and a second cell array having a plurality of storage cells are arranged to overlap each other. Two bit lines included in a first bit line pair are electrically connected to a portion of the storage cells included in the first cell array and a portion of the storage cells included in the second cell array, respectively. Two bit lines included in a second bit line pair are electrically connected to a portion of the storage cells included in the first cell array and a portion of the storage cells included in the second cell array, respectively. In the first cell array, one of the two bit lines included in the second bit line pair has an area overlapping with a portion of the first bit line pair, and in the second cell array, the other of the two bit lines included in the second bit line pair has an area overlapping with a portion of the first bit line pair.

Description

Technical Field

[0001] One embodiment of the present invention relates to a storage device, a semiconductor device, or an electronic device using the same. Background Art

[0002] However, one embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the invention disclosed in this specification, etc., relates to a process, machine, product, or composition of matter.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one form of semiconductor devices. In addition, display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices are sometimes said to be semiconductor devices. Or, sometimes, they can be said to include semiconductor devices.

[0004] As semiconductor thin films that can be applied to transistors, silicon-based semiconductor materials are well known. In addition, as other materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, it is known that in addition to unit metal oxides such as indium oxide and zinc oxide, there are also multinary metal oxides. Among multinary metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly hot. Background Art

[0006] Through the study of IGZO, CAAC (c-axis aligned crystalline: c-axis oriented crystal) structure and nc (nanocrystalline: nanocrystalline) structure, which are neither single crystal nor amorphous, were discovered in oxide semiconductors (see non-patent documents 1 to 3). Non-patent documents 1 and 2 disclose a technology for manufacturing transistors using an oxide semiconductor having a CAAC structure. Non-patent documents 4 and 5 disclose an oxide semiconductor having a lower crystallinity than a CAAC structure and a nc structure and also having tiny crystals.

[0007] A transistor using IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (see Non-Patent Documents 7 and 8).

[0008] In addition, DRAM (Dynamic Random Access Memory) is known as one of the storage devices. DRAM includes a cell array in which a plurality of memory cells are arranged in a matrix, a plurality of bit lines, and a plurality of word lines. The memory cell is electrically connected to any one of the plurality of bit lines and any one of the plurality of word lines. The word line is supplied with a selection signal for selecting a memory cell for writing and reading data. Writing data to the memory cell and reading data from the memory cell are both performed through the bit line.

[0009] For example, when data is written to a memory cell X via a bit line A, noise caused by the potential of the bit line A may be transmitted to a bit line B adjacent to the bit line A. When this occurs, the data held in the memory cell Y electrically connected to the bit line B may be unintentionally rewritten. As one method of suppressing the influence of this noise, a twisted bit-line method has been disclosed (see Patent Document 1).

[0010] There are two types of DRAM: a folded bit-line type and an open bit-line type.

[0011] [Prior technical literature]

[0012] [Patent Document]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 2-244485

[0014] [Non-patent document 1] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186

[0015] [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10

[0016] [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p. 151-154

[0017] [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p. Q3012-Q3022

[0018] [Non-patent document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164

[0019] [Non-patent document 6] K.Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7

[0020] [Non-patent document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217

[0021] [Non-patent document 8] S.Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p.626-629 Summary of the invention

[0022] Technical problem to be solved by the invention

[0023] The crossed bit line pair method can be used in a folded bit line method memory device, but cannot be used in an open bit line method memory device with a high density of memory cells. Therefore, it is difficult to achieve high integration of the cell array.

[0024] In the intersecting bit line pair method, an intersecting portion must be provided in at least a portion of a pair of bit lines, but a memory cell cannot be arranged at the intersecting portion.

[0025] One of the purposes of one embodiment of the present invention is to provide a highly integrated storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device that is not easily affected by noise. In addition, one of the purposes of the present invention is to provide a storage device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a novel storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device.

[0026] Note that the recording of these purposes does not prevent the existence of other purposes. Note that one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes are obvious from the description of the specification, drawings, claims, etc., and may be derived from the description.

[0027] Solutions to technical problems

[0028] A first cell array having a plurality of memory cells and a second cell array having a plurality of memory cells are arranged to overlap each other. Two bit lines included in a first bit line pair are electrically connected to a portion of memory cells included in the first cell array and a portion of memory cells included in the second cell array, respectively. Two bit lines included in a second bit line pair are electrically connected to a portion of memory cells included in the first cell array and a portion of memory cells included in the second cell array, respectively. In the first cell array, one of the two bit lines included in the second bit line pair has an area overlapping with a portion of the first bit line pair, and in the second cell array, the other of the two bit lines included in the second bit line pair has an area overlapping with a portion of the first bit line pair.

[0029] One embodiment of the present invention is a memory device, which includes a first cell array, a second cell array, a first bit line pair, and a second bit line pair, the first cell array and the second cell array have a mutually overlapping area, the first cell array includes Aa (Aa is an integer greater than 1) first memory cells, Ba (Ba is an integer greater than 1) first memory cells, Ca (Ca is an integer greater than 1) first memory cells, Da (Da is an integer greater than 1) first memory cells, Ea (Ea is an integer greater than 1) first memory cells, and Fa (Fa is an integer greater than 1) first memory cells, and the second cell array includes Ab (Ab is an integer greater than 1) second memory cells, Bb (Bb is an integer greater than 1) second memory cells, Cb (Cb is an integer greater than 1) second memory cells, Db (Db is an integer greater than 1) second memory cells, and Eb (Eb is an integer greater than 1) second memory cells. unit and Fb (Fb is an integer greater than 1) second memory cells, one bit line in the first bit line pair is electrically connected to Aa first memory cells, Ca first memory cells and Cb second memory cells, another bit line in the first bit line pair is electrically connected to Ba first memory cells, Ab second memory cells and Bb second memory cells, one bit line in the second bit line pair is electrically connected to Da first memory cells, Fa first memory cells and Fb second memory cells, another bit line in the second bit line pair is electrically connected to Ea first memory cells, Db second memory cells and Eb second memory cells, a portion of Da first memory cells are adjacent to Ba first memory cells, another portion of Da first memory cells are adjacent to Ca first memory cells, a portion of Db first memory cells are adjacent to Bb first memory cells, and another portion of Db first memory cells are adjacent to Cb first memory cells.

[0030] In addition, there may be a plurality of first bit line pairs and a plurality of second bit line pairs. The first memory cell may also include a first transistor and a first capacitor, and the second memory cell may also include a second transistor and a second capacitor. The first transistor and the second transistor preferably use an oxide semiconductor in the semiconductor layer in which the channel is formed.

[0031] In addition, another embodiment of the present invention is a storage device, which includes a first cell array, a second cell array, first to fourth BLf bit lines, first to fourth BLs bit lines, first to fourth BLBf bit lines and first to fourth BLBs bit lines, the first cell array and the second cell array have an overlapping area, and the first cell array includes Aa first storage cells, Ba first storage cells, Ca first storage cells, Da first storage cells, Ea first storage cells, Fa first storage cells, Ga (Ga is an integer greater than 1) first storage cells, Ha (Ha is an integer greater than 1) first storage cells, Ia (Ia is an integer greater than 1) first storage cells, and Ja (Ja is an integer greater than 1). 1 or more) first storage units, Ka (Ka is an integer greater than 1) first storage units, and La (La is an integer greater than 1) first storage units, the second unit array includes Ab second storage units, Bb second storage units, Cb second storage units, Db second storage units, Eb second storage units, Fb second storage units, Gb (Gb is an integer greater than 1) second storage units, Hb (Hb is an integer greater than 1) second storage units, Ib (Ib is an integer greater than 1) second storage units, Jb (Jb is an integer greater than 1) second storage units, Kb (Kb is an integer greater than 1) second storage units, and Lb (Lb is an integer greater than 1) second storage units The first BLf bit line is electrically connected to Ba first memory cells and Bb second memory cells, the first BLs bit line is electrically connected to Ab second memory cells, the first BLBf bit line is electrically connected to Ca first memory cells and Cb second memory cells, the first BLBs bit line is electrically connected to Aa first memory cells, the second BLf bit line is electrically connected to Fa first memory cells and Fb second memory cells, the second BLs bit line is electrically connected to Db second memory cells, the second BLBf bit line is electrically connected to Ea first memory cells and Eb second memory cells, the second BLBs bit line is electrically connected to Da first memory cells, the third BLf bit line is electrically connected to Ia first memory cells and Ib second memory cells, and the third BLf bit line is electrically connected to Ia first memory cells and Ib second memory cells. The s bit line is electrically connected to the Gb second memory cells, the third BLBf bit line is electrically connected to the Ha first memory cells and the Hb second memory cells, the third BLBs bit line is electrically connected to the Ga first memory cells, the fourth BLf bit line is electrically connected to the Ka first memory cells and the Kb second memory cells, the fourth BLs bit line is electrically connected to the Jb second memory cells, the fourth BLBf bit line is electrically connected to the La first memory cells and the Lb second memory cells, the fourth BLBs bit line is electrically connected to the Ja first memory cells, the Ba first memory cells and the Ia first memory cells are adjacent to a portion of the Da first memory cells, the Ca first memory cells and the Ha first memory cells are adjacent to another portion of the Da first memory cells,A portion of Ja first storage cells is adjacent to Ia first storage cells, another portion of Ja first storage cells is adjacent to Ha first storage cells, Bb second storage cells and Ib second storage cells are adjacent to a portion of Db second storage cells, Cb second storage cells and Hb second storage cells are adjacent to another portion of Db second storage cells, a portion of Jb second storage cells is adjacent to Ib second storage cells, and another portion of Jb second storage cells is adjacent to Hb second storage cells. ,

[0032] In addition, the above-mentioned storage device also includes a first read-out amplifier and eleventh to fourteenth switches, the first BLf bit line is electrically connected to the first read-out amplifier through the eleventh switch, the first BLs bit line is electrically connected to the first read-out amplifier through the twelfth switch, the first BLBf bit line is electrically connected to the first read-out amplifier through the thirteenth switch, and the first BLBs bit line is electrically connected to the first read-out amplifier through the fourteenth switch.

[0033] In addition, the above-mentioned storage device also includes a second read-out amplifier and twenty-first to twenty-fourth switches, the second BLf bit line is electrically connected to the second read-out amplifier through the twenty-first switch, the second BLs bit line is electrically connected to the second read-out amplifier through the twenty-second switch, the second BLBf bit line is electrically connected to the second read-out amplifier through the twenty-third switch, and the second BLBs bit line is electrically connected to the second read-out amplifier through the twenty-fourth switch.

[0034] In addition, the above-mentioned storage device also includes a third read-out amplifier and thirty-first to thirty-fourth switches, the third BLf bit line is electrically connected to the third read-out amplifier through the thirty-first switch, the third BLs bit line is electrically connected to the third read-out amplifier through the thirty-second switch, the third BLBf bit line is electrically connected to the third read-out amplifier through the thirty-third switch, and the third BLBs bit line is electrically connected to the third read-out amplifier through the thirty-fourth switch.

[0035] In addition, the above-mentioned storage device also includes a fourth read-out amplifier and forty-first to forty-fourth switches, the fourth BLf bit line is electrically connected to the fourth read-out amplifier through the forty-first switch, the fourth BLs bit line is electrically connected to the fourth read-out amplifier through the forty-second switch, the fourth BLBf bit line is electrically connected to the fourth read-out amplifier through the forty-third switch, and the fourth BLBs bit line is electrically connected to the fourth read-out amplifier through the forty-fourth switch.

[0036] Ca is preferably 0.8 times or more and 1.2 times or less of Ba, and more preferably the same number as Ba. Ab is preferably 0.8 times or more and 1.2 times or less of Aa, and more preferably the same number as Aa. The sum of Ba and Ca is preferably 0.8 times or more and 1.2 times or less of Aa, and more preferably the same number as Aa. Ia is preferably 0.8 times or more and 1.2 times or less of Ba, and more preferably the same number as Ba.

[0037] Another embodiment of the present invention is a method for operating a storage device, the storage device comprising a first cell array, a second cell array, a first bit line, a second bit line and a read amplifier, the first storage cell having a first transistor and a first capacitor, the second storage cell having a second transistor and a second capacitor, the first transistor and the second transistor each comprising an oxide semiconductor in its semiconductor layer, the first storage cell being electrically connected to the read amplifier via the first bit line, and the second storage cell being electrically connected to the read amplifier via the second bit line, the method for operating comprising a first operation of supplying a first potential to a gate of the first transistor to supply a charge stored in the first capacitor to the first bit line, and supplying a second potential to a gate of the second transistor during the first operation.

[0038] After the first operation is completed, the third potential may also be supplied to the gate of the first transistor. In addition, a second operation may be included in which the first potential is supplied to the gate of the first transistor to supply the charge of the first bit line to the first capacitor. During the second operation, the second potential is supplied to the gate of the second transistor. After the second operation is completed, the third potential may also be supplied to the gate of the first transistor.

[0039] The first potential is higher than the source potential and the drain potential of the first transistor. The second potential is lower than the source potential and the drain potential of the second transistor. The third potential is lower than the source potential and the drain potential of the first transistor.

[0040] Effects of the Invention

[0041] According to one embodiment of the present invention, the following devices can be provided: a storage device that is not easily affected by noise; a storage device with high integration density; a storage device with high reliability; a storage device with low power consumption; a novel storage device; and a novel semiconductor device.

[0042] Note that the description of these effects does not prevent the existence of other effects. Note that one mode of the present invention does not necessarily have all of the above effects. Effects other than the above effects are obvious from the description of the specification, drawings, claims, etc., and may be derived from the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a diagram showing a configuration example of a storage device;

[0044] Figure 2A and Figure 2B is a diagram showing an example of the structure of a storage block;

[0045] Figure 3 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0046] Figure 4 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0047] Figure 5 is a diagram showing an example of the configuration of a bit line pair;

[0048] FIG. 6A to FIG. 6C is a diagram showing an example of a circuit configuration of a memory cell;

[0049] Fig. 7A and Figure 7B is a diagram showing electrical characteristics of a transistor;

[0050] Figure 8 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0051] Fig. 9 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0052] Fig.10 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0053] Fig.11 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0054] Fig.12 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0055] Fig.13 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0056] Fig.14 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0057] Fig.15A and Fig. 15B is a diagram showing the arrangement of a storage cell group;

[0058] Fig.16 is a diagram showing an example of the configuration of a bit line pair;

[0059] Fig.17 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0060] Fig.18is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0061] Fig.19 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0062] Fig. 20 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0063] Fig.21 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0064] Fig. 22 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0065] Fig.23 is a diagram showing the connection relationship between a sense amplifier and a memory cell;

[0066] Fig.24A and Fig. 24B is a diagram showing the arrangement of a storage cell group;

[0067] Fig.25 is a diagram showing an example of the configuration of a bit line pair;

[0068] Fig.26A and Fig.26B is a diagram for explaining a folded bit line type memory device and an open bit line type memory device;

[0069] Fig.27A1 , Fig.27B1 , Fig.27A2 and Figure 27B2 is a diagram illustrating a bit line and a sense amplifier and a diagram illustrating a potential change of a bit line;

[0070] Fig.28 is a diagram showing an example of a circuit configuration of a sense amplifier;

[0071] Fig.29 is a diagram showing an operation example of a sense amplifier;

[0072] Fig.30 is a diagram showing an operation example of a sense amplifier;

[0073] Fig.31 is a diagram showing an operation example of a sense amplifier;

[0074] Fig.32 is a diagram showing an example of a circuit configuration of a sense amplifier;

[0075] Fig.33 is a diagram showing an operation example of a sense amplifier;

[0076] Fig.34is a diagram showing an operation example of a sense amplifier;

[0077] Fig.35 is a diagram showing an operation example of a sense amplifier;

[0078] Fig.36 is a diagram showing a structural example of a semiconductor device;

[0079] Fig.37 is a diagram showing a structural example of a semiconductor device;

[0080] FIG. 38A to FIG. 38C is a diagram illustrating a structural example of a transistor;

[0081] FIG. 39A to FIG. 39C is a diagram illustrating a structural example of a transistor;

[0082] FIG. 40A to FIG. 40C is a diagram illustrating a structural example of a transistor;

[0083] FIG. 41A to FIG. 41C is a diagram illustrating a structural example of a transistor;

[0084] FIG. 42A to FIG. 42C is a diagram illustrating a structural example of a transistor;

[0085] FIG. 43A to FIG. 43C is a diagram illustrating a structural example of a transistor;

[0086] Fig.44A and Fig.44B is a diagram illustrating a structural example of a transistor;

[0087] FIG. 45A to FIG. 45C is a diagram illustrating a structural example of a transistor;

[0088] FIG. 46A to FIG. 46C is a diagram illustrating a structural example of a transistor;

[0089] FIG. 47A to FIG. 47C is a diagram illustrating a structural example of a transistor;

[0090] FIG. 48A to FIG. 48C is a diagram illustrating a structural example of a transistor;

[0091] FIG. 49A to FIG. 49C is a diagram illustrating a structural example of a transistor;

[0092] FIG. 50A to FIG. 50C is a diagram illustrating a structural example of a transistor;

[0093] Fig.51A and Fig.51B is a diagram illustrating a structural example of a transistor;

[0094] Fig.52 It is a diagram that explains the concept of the product;

[0095] Fig.53A and Fig.53B is a diagram showing an example of an electronic component;

[0096] Fig.54 is a diagram showing an example of an electronic device. DETAILED DESCRIPTION

[0097] The embodiments are described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and a person skilled in the art can easily understand that the method and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that in the structure of the invention described below, the same figure mark is used in different drawings to represent the same part or the part with the same function, and its repeated description is sometimes omitted.

[0098] In addition, in order to facilitate understanding of the invention, the position, size, range, etc. of each structure shown in the drawings, etc. may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally etched due to a process such as etching, but this may not be reflected in the drawings for ease of understanding.

[0099] In addition, in particular, in a top view (also called a plan view) or a perspective view, in order to facilitate understanding of the invention, description of some components may be omitted. In addition, description of some hidden lines may be omitted.

[0100] Ordinal numbers such as "first" and "second" in this specification are used to avoid confusion between constituent elements, and do not indicate an order or sequence such as a process sequence or a stacking sequence. In addition, for terms that are not accompanied by ordinal numbers in this specification, ordinal numbers are sometimes added to the terms in the claims to avoid confusion between constituent elements. Note that for terms that are accompanied by ordinal numbers in this specification, ordinal numbers are sometimes omitted in the claims.

[0101] In addition, in this specification, etc., "electrode" or "wiring" does not limit its constituent elements in terms of function. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wiring" are formed as one.

[0102] In addition, in this specification, etc., "above" or "below" is not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, "electrode B on insulating layer A" does not need to form electrode B on insulating layer A in direct contact, and may also include the case where other components are included between insulating layer A and electrode B.

[0103] In addition, since the functions of the "source" and "drain" are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, it is difficult to define which is the "source" and which is the "drain". Therefore, in this specification, the "source" and "drain" can be interchangeable.

[0104] In addition, in this specification, when it is clearly stated that "X is connected to Y", the following cases are disclosed in this specification, etc.: a case where X is electrically connected to Y; a case where X is functionally connected to Y; and a case where X is directly connected to Y. Therefore, the connection relationship is not limited to the connection relationship shown in the drawings or the text, and the drawings or the text also disclose connection relationships other than the connection relationships shown in the drawings or the text.

[0105] In addition, in this specification, "electrical connection" includes the case of connection via "a substance having a certain electrical function". Here, "a component having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. Therefore, even if it is recorded as "electrical connection", there may be a part in the actual circuit that is not physically connected but just a wiring extension.

[0106] Note that the channel length refers to, for example, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other in the top view of the transistor or the region where the channel is formed. In addition, in a transistor, the channel length does not necessarily have the same value in all regions. In other words, the channel length of a transistor is sometimes not limited to one value. Therefore, in this specification, the channel length is any value, maximum value, minimum value, or average value in the region where the channel is formed.

[0107] The channel width refers to, for example, the length of the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other or the portion where the source and drain are opposite in the region where the channel is formed. In addition, in a transistor, the channel width does not necessarily have the same value in all regions. In other words, the channel width of a transistor is sometimes not limited to one value. Therefore, in this specification, the channel width is any value, maximum value, minimum value or average value in the region where the channel is formed.

[0108] In addition, depending on the structure of the transistor, the actual channel width in the region where the channel is formed (hereinafter, also referred to as the "effective channel width") and the channel width shown in the top view of the transistor (hereinafter, also referred to as the "apparent channel width") are sometimes different. For example, in the case where the gate electrode covers the side of the semiconductor layer, sometimes because the effective channel width is larger than the apparent channel width, its influence cannot be ignored. For example, in a miniature transistor with a gate electrode covering the side of the semiconductor, sometimes the proportion of the channel formed on the side of the semiconductor increases. In this case, the effective channel width is larger than the apparent channel width.

[0109] In this case, it is sometimes difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width based on the design value, it is necessary to presume the shape of the semiconductor. Therefore, when the shape of the semiconductor is not exactly known, it is difficult to accurately measure the effective channel width.

[0110] Therefore, in this specification, the apparent channel width is sometimes referred to as the "surrounded channel width (SCW)". In addition, in this specification, when simply expressing "channel width", it sometimes refers to the surrounded channel width or the apparent channel width. Alternatively, in this specification, when simply expressing "channel width", it sometimes refers to the effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0111] When calculating the field effect mobility of a transistor or the current value per channel width, the calculation may be performed using the actual channel width. In this case, the calculated value may be different from that obtained when the actual channel width is used.

[0112] In addition, the "impurities" of semiconductors are, for example, substances other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. Sometimes, due to the inclusion of impurities, the DOS (Density of States) of the semiconductor becomes higher, the carrier mobility decreases, or the crystallinity decreases. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, there are, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, water sometimes also acts as an impurity. In addition, in the case of an oxide semiconductor, sometimes, for example, oxygen defects are generated due to the mixing of impurities. In addition, when the semiconductor is silicon, as impurities that change the characteristics of the semiconductor, there are, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0113] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged in an angle range of more than -10° and less than 10°. Therefore, the case where the angle is more than -5° and less than 5° is also included. In addition, "approximately parallel" refers to a state in which the angle formed by two straight lines is more than -30° and less than 30°. In addition, "perpendicular" or "orthogonal" refers to a state in which two straight lines are arranged in an angle range of more than 80° and less than 100°. Therefore, the case where the angle is more than 85° and less than 95° is also included. In addition, "approximately perpendicular" refers to a case in which the angle formed by two straight lines is more than 60° and less than 120°.

[0114] In addition, in this specification, unless otherwise stated, when "same", "identical", "equal" or "uniform" (including their synonyms) is mentioned about count values ​​or measurement values, an error of ±20% is included.

[0115] In addition, in this specification and the like, when an etching process is performed after a resist mask is formed by photolithography, unless otherwise specified, the resist mask is removed after the etching process is completed.

[0116] In addition, in this specification, etc., a high power supply potential VDD (also referred to as "VDD" or "H potential") refers to a power supply potential of a potential higher than a low power supply potential VSS. In addition, a low power supply potential VSS (also referred to as "VSS" or "L potential") refers to a power supply potential of a potential lower than a high power supply potential VDD. In addition, a ground potential (also referred to as "GND" or "GND potential") may be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.

[0117] In addition, depending on the situation or state, the "film" and the "layer" may be interchanged. For example, the "conductive layer" may be interchanged with the "conductive film". In addition, the "insulating film" may be interchanged with the "insulating layer".

[0118] In addition, unless otherwise stated, the transistors shown in this specification, etc. are enhancement type (normally closed) field effect transistors. In addition, unless otherwise stated, the transistors shown in this specification, etc. are n-channel transistors. Therefore, unless otherwise stated, their threshold voltage (also referred to as "Vth") is greater than 0V.

[0119] (Implementation Method 1)

[0120] A storage device according to one embodiment of the present invention will be described with reference to the drawings.

[0121] First, a folded bit line type memory device and an open bit line type memory device are described.

[0122] Fig.26A 1 is a block diagram for explaining a memory device 901 of a folded bit line method. The memory device 901 includes a cell array 921 including memory cells 911 arranged in a matrix, a plurality of word lines, a plurality of bit lines, and a plurality of sense amplifiers SA. In the memory device 901, a plurality of bit lines are provided so as to extend in a row direction (or a column direction), and a plurality of word lines are provided so as to extend in a column direction (or a row direction).

[0123] The plurality of word lines each crosses the plurality of bit line pairs. The plurality of bit lines include a plurality of bit lines BL and a plurality of bit lines BLB. Fig.26A Three bit lines BL (bit line BL1 to bit line BL3 ) and three bit lines BLB (bit line BLB1 to bit line BLB3 ) are shown in FIG.

[0124] In the folded bit line storage device 901, the bit lines BL and the bit lines BLB are alternately arranged. In addition, one bit line BL and one bit line BLB constitute one bit line pair. In the storage device 901, a bit line pair consisting of a bit line BL1 and a bit line BLB1, a bit line pair consisting of a bit line BL2 and a bit line BLB2, and a bit line pair consisting of a bit line BL3 and a bit line BLB3 are shown. In addition, one sense amplifier SA is electrically connected to one bit line pair.

[0125] The memory cell 911 is provided near the intersection of the word line and the bit line. However, in one bit line pair, the memory cell 911 electrically connected to the bit line BL and the memory cell 911 electrically connected to the bit line BLB cannot be electrically connected to the same word line. Therefore, in a memory device of the folded bit line method, the memory cell cannot be provided near all the intersections. Therefore, it is difficult to realize high integration of the memory cell.

[0126] Fig.26B 9 is a block diagram for explaining an open bit line memory device 902. In the open bit line memory device 902, bit lines BL are provided in a cell array 921a, and bit lines BLB are provided in a cell array 921b. In addition, each of the cell arrays 921a and 921b is provided with a plurality of word lines.

[0127] In the open bit line memory device 902, the bit lines BL and BLB are provided in different cell arrays and each cell array has a word line, so that memory cells can be provided near all intersections, thereby facilitating high integration of the cell array.

[0128] The sense amplifier SA reads the data stored in the memory cell 911. When the specified memory cell 911 is selected by the word line, the data of the selected memory cell 911 is supplied to the bit line (bit line BL or bit line BLB), and the potential of the bit line changes. The sense amplifier SA amplifies the potential difference between the bit line BL and the bit line BLB and outputs it.

[0129] Fig.27A1 The bit lines and sense amplifier SA of the memory device 901 are shown. Fig.27A2 is a timing chart showing the potential change of the bit line.

[0130] Each bit line is capacitively coupled via parasitic capacitance. For example, a parasitic capacitance CpA exists between bit line BLB1 and bit line BL2. Therefore, when the potential of bit line BLB1 is inverted due to data writing, the potential of the adjacent bit line BL2 may also change.

[0131] Reference Fig.27A2 The malfunction of the memory device 901 is described. During the period T0, the potential of the bit line BL1 and the bit line BLB2 is slightly lower than the H potential, and the potential of the bit line BLB1 and the bit line BL2 is slightly higher than the L potential. During the period T1, when the bit line BLB1 is supplied with the H potential, the potential of the bit line BL2, which is capacitively coupled to the bit line BLB1 through the parasitic capacitance CpA, also rises and sometimes becomes higher than the potential of the bit line BLB2. The sense amplifier SA amplifies the slight potential difference, and the bit line pair including the bit line BL2 reads erroneous data. In other words, the potential change of the bit line BLB1 affects the bit line BL2 in the form of noise.

[0132] The influence of noise can be reduced by intersecting the bit line BL2 and the bit line BLB2. In this specification, etc., the bit lines including the intersection of the bit line BL and the bit line BLB are symmetrically referred to as a "intersecting bit line pair". Fig.27B1 is a diagram showing the bit lines and sense amplifier SA of a memory device 901 including a crossed bit line pair. Figure 27B2 is a timing chart showing the potential change of the intersecting bit line pair.

[0133] exist Fig.27B1 In the embodiment, the bit line pair including the bit line BL2 and the bit line BLB2 is a cross bit line pair. Fig.27B1 The crossing bit line pair shown includes three crossing portions 931. A portion of bit line BL2 and a portion of bit line BLB2 are adjacent to bit line BLB1. Specifically, regions D1 and D2 of bit line BL2 and regions DB1 and DB2 of bit line BLB2 are adjacent to bit line BLB1.

[0134] As described above, there is a parasitic capacitor CpA between the bit line BLB1 and the bit line BL2. Similarly, the parasitic capacitor between the bit line BLB1 and the bit line BLB2 is recorded as a parasitic capacitor CpB. The capacitance value of the parasitic capacitor CpA is proportional to the sum of the length of the region D1 and the length of the region D2. Similarly, the capacitance value of the parasitic capacitor CpB is proportional to the sum of the length of the region DB1 and the length of the region DB2. Preferably, the capacitance value of the parasitic capacitor CpA is the same as the capacitance value of the parasitic capacitor CpB. Therefore, it is preferred that the sum of the lengths of the regions of the bit line BL2 adjacent to the bit line BLB1 (the sum of the lengths of the region D1 and the region D2) is equal to the sum of the lengths of the regions of the bit line BLB2 adjacent to the bit line BLB1 (the sum of the lengths of the region DB1 and the region DB2).

[0135] The capacitance value of the parasitic capacitance CpA is proportional to the sum of the number of memory cells connected to the region D1 and the number of memory cells connected to the region D2. Similarly, the capacitance value of the parasitic capacitance CpB is proportional to the sum of the number of memory cells connected to the region DB1 and the number of memory cells connected to the region DB2. Therefore, it is preferred that the sum of the number of memory cells connected to the region D1 and the number of memory cells connected to the region D2 is equal to the sum of the number of memory cells connected to the region DB1 and the number of memory cells connected to the region DB2.

[0136] Reference Figure 27B2 The potential change of the crossed bit line pair is described. During period T0, the bit line BL1 and the bit line BLB2 are set to a potential slightly lower than the H potential, and the bit line BLB1 and the bit line BL2 are set to a potential slightly higher than the L potential. During period T1, when the bit line BLB1 is supplied with the H potential, the potential of the bit line BL2 capacitively coupled to the bit line BLB1 through the parasitic capacitance CpA rises. In addition, the potential of the bit line BLB2 capacitively coupled to the bit line BLB1 through the parasitic capacitance CpB also rises. Therefore, the potential of the bit line BL2 and the bit line BLB2 in the crossed bit line pair both rise. Therefore, the potential difference between the two hardly changes even if it is affected by noise.

[0137] In a folded bit line storage device, by alternately arranging crossed bit line pairs and non-crossed bit line pairs, malfunctions caused by noise can be prevented, thereby improving the reliability of the storage device. In an open bit line storage device, since the bit line BL and the bit line BLB in a bit line pair are located in different cell arrays on the same plane, crossed bit line pairs cannot be implemented.

[0138] <Storage device 100>

[0139] Figure 1 1 is a block diagram showing a configuration example of a storage device 100 according to one embodiment of the present invention.

[0140] The memory device 100 includes an input / output circuit 111 (IO circuit), a control circuit 112 (controller), an I2C receiver 113 , a setting register 114 , an LVDS circuit 115 , an LVDS circuit 116 , a decoder 117 , and a memory block array 210 .

[0141] In addition, the control circuit 112 has a register 118 (Reg_r) and a register 119 (Reg_w). In addition, the storage block array 210 has n (n is an integer greater than 1) storage blocks 211. In this specification, etc., the first storage block 211 is represented by a storage block 211_1, and the i-th (i is an integer greater than 1 and less than n) storage block 211 is represented by a storage block 211_i.

[0142] The input / output circuit 111 has a function of transmitting signals to and from an external device. The operating conditions of the storage device 100 are determined by the setting parameters stored in the setting register 114. The setting parameters are written into the setting register 114 via the output circuit 111 and the I2C receiver 113. In addition, the I2C receiver 113 may be omitted depending on the purpose or application.

[0143] An example of the setting parameters includes information such as the execution interval of the refresh operation or the operation timing of the circuit operation. The control circuit 112 has a function of processing the setting parameters and the command signal from the outside and determining the operation mode of the storage device 100. The control circuit 112 has a function of generating various control signals to control the operation of the entire storage device 100.

[0144] In addition, a reset signal res, an address signal ADDR[16:0], a row address strobe signal RAS (Row Address Strobe), a column address strobe signal CAS (Column Address Strobe), a write enable signal WE (Write Enable), a data write clock signal clk_t, and write data WDATA[7:0] are input to the control circuit 112 from the outside through the output circuit 111. The data write clock signal clk_t is input to the control circuit 112 through the transmission circuit LVDS_rx.

[0145] In addition, the data read clock signal clk_w and the read data RDATA[7:0] are input to the input / output circuit 111 from the control circuit 112. The data read clock signal clk_w is input to the input / output circuit 111 through the transmission circuit LVDS_tx. The transmission circuit LVDS_rx and the transmission circuit LVDS_tx are transmission circuits that operate according to the low voltage differential signal (LVDS: Low voltage differential signaling) specification. In addition, one or both of the transmission circuit LVDS_rx and the transmission circuit LVDS_tx may be omitted depending on the purpose or use.

[0146] The write data WDATA[7:0] is transmitted in synchronization with the data write clock signal clk_t and is stored in the register 119 in the control circuit 112. The control circuit 112 has a function of supplying the data stored in the register 119 to the memory block array 210.

[0147] The data read from the memory block array 210 is stored as read data RDATA[7:0] in the register 118 in the control circuit 112. The control circuit 112 has a function of transmitting the read data RDATA[7:0] to the input / output circuit 111 in synchronization with the data read clock signal clk_w.

[0148] In addition, the control circuit 112 has the functions of outputting column address signal C_ADDR, column selection enable signal CSEL_EN, data latch signal DLAT, global write enable signal GW_EN, global read enable signal GR_EN, global read amplifier enable signal GSA_EN, global equalization enable signal GEQ_ENB, local read amplifier enable signal LSA_EN, local equalization enable signal LEQ_ENB and word line address selection signal WL_ADDR[7:0].

[0149] The column address signal C_ADDR and the column selection enable signal CSEL_EN are input to the decoder 117 .

[0150] <storage block>

[0151] Figure 2A 211_i is a block diagram showing a structural example of a storage block 211_i. Figure 2B 2 is a three-dimensional block diagram showing a structural example of a local sense amplifier array 214, a cell array 221a, and a cell array 221b included in a memory block 211_i. Figure 2B Arrows indicating the X direction, the Y direction, and the Z direction are shown in the figure. The X direction, the Y direction, and the Z direction are directions perpendicular to each other.

[0152] The memory block 211_i includes a word line driver 212 (WL driver), a local sense amplifier driver 213 (LSA driver), a local sense amplifier array 214, a global sense amplifier 215 (global SA), a read / write selector 216 (R / W selector), a cell array 221a and a cell array 221b.

[0153] The data latch signal DLAT, the global write enable signal GW_EN, and the global read enable signal GR_EN are input to the read / write selector 216. The global sense amplifier enable signal GSA_EN and the global equalization enable signal GEQ_ENB are input to the global sense amplifier 215. The local sense amplifier enable signal LSA_EN and the local equalization enable signal LEQ_ENB are input to the local sense amplifier array 214. The word line address selection signal WL_ADDR[7:0] is input to the word line driver 212.

[0154] The local sense amplifier array 214 includes a plurality of sense amplifiers 127 arranged in a matrix shape of f rows and g columns (f and g are both integers greater than or equal to 1). In this specification, etc., the sense amplifier 127 in the first row and first column is represented by sense amplifier 127[1,1]. In addition, the sense amplifier 127 in the kth row and hth column (k is an integer greater than or equal to 1 and less than or equal to f, and h is an integer greater than or equal to 1 and less than or equal to g) is represented by sense amplifier 127[k,h].

[0155] The cell array 221a is overlapped on the local sense amplifier array 214, and the cell array 221b is overlapped on the cell array 221a. By stacking the cell array 221a and the cell array 221b on the sense amplifier array 214, the wiring length of the bit line can be shortened. In addition, by stacking the cell array 221a and the cell array 221b, the mounting density of the memory cell can be increased.

[0156] The cell array 221a has a plurality of memory cells 10a arranged in a matrix of p rows and q columns (p and q are both integers greater than 1). The cell array 221b has a plurality of memory cells 10b arranged in a matrix of p rows and q columns. In addition, the cell array 221a has p word lines WLa extending in the X direction (row direction) (in the Figure 2B In addition, the cell array 221b has p word lines WLb extending in the X direction (row direction) (in Figure 2B (not shown in the figure). In this specification and the like, word line WLa[j] represents the j-th (j is an integer greater than or equal to 1 and less than or equal to p) word line WLa, and word line WLb[j] represents the j-th word line WLb.

[0157] One memory cell 10 a is electrically connected to any one of the word lines WLa, and one memory cell 10 b is electrically connected to any one of the word lines WLb.

[0158] Figure 3 and Figure 4 1 is a three-dimensional block diagram showing the connection relationship between the sense amplifier 127, the memory cell 10a, and the memory cell 10b. Figure 3 and Figure 4 A portion of the local sense amplifier array 214 , a portion of the cell array 221 a , and a portion of the cell array 221 b included in the memory block 211 are shown. Figure 3 and Figure 4 The sense amplifier 127 shown is a 2-cell wide type sense amplifier. In this specification, etc., a "2-cell wide type sense amplifier" refers to a sense amplifier whose length in the X direction is equivalent to approximately two memory cells.

[0159] Figure 3 Sense amplifier 127[k,h], sense amplifier 127[k-1,h], sense amplifier 127[k+1,h], and memory cell 10a and memory cell 10b electrically connected to these sense amplifiers 127 are shown. Figure 3 10a and 10b are electrically connected to one sense amplifier 127. However, the number of memory cells 10a and 10b electrically connected to one sense amplifier 127 is not limited to this.

[0160] Figure 4 1 is a three-dimensional block diagram showing the connection relationship between the sense amplifier 127, the memory cell 10a, and the memory cell 10b. Figure 4 1 and 2 show a memory cell electrically connected to a sense amplifier 127[k,h] and a memory cell electrically connected to a sense amplifier 127[k+1,h]. Figure 4In FIG. 1 , the description of the word line WLa and the word line WLb is omitted. Figure 5 Sense amplifier 127 [k, h], sense amplifier 127 [k+1, h], and corresponding bit lines BL and BLB are shown.

[0161] One sense amplifier 127 is electrically connected to one bit line pair. Of the bit lines BL and BLB included in the bit line pair, the bit line BL is electrically connected to the node ND of the sense amplifier 127, and the bit line BLB is electrically connected to the node NDB of the sense amplifier 127. The sense amplifier 127 has a function of amplifying the potential difference between the bit lines BL and BLB.

[0162] In this specification, etc., bit line BL[k,h] represents a bit line BL electrically connected to sense amplifier 127[k,h], and bit line BLB[k,h] represents a bit line BLB electrically connected to sense amplifier 127[k,h]. In addition, node ND[k,h] represents a node ND of sense amplifier 127[k,h], and node NDB[k,h] represents a node NDB of sense amplifier 127[k,h].

[0163] One memory cell 10a is electrically connected to any one of the bit lines BL or any one of the bit lines BLB. In addition, one memory cell 10b is electrically connected to any one of the bit lines BL or any one of the bit lines BLB.

[0164] The cell array 221a includes: a storage cell group 51a including A (A is an integer greater than 1) storage cells 10a; a storage cell group 52a including B (B is an integer greater than 1) storage cells 10a; and a storage cell group 53a including C (C is an integer greater than 1) storage cells 10a.

[0165] The cell array 221b includes: a storage cell group 51b including D (D is an integer greater than 1) storage cells 10b; a storage cell group 52b including E (E is an integer greater than 1) storage cells 10b; and a storage cell group 53b including F (F is an integer greater than 1) storage cells 10b.

[0166] The memory cells 10a included in the memory cell group 51a and the memory cell group 53a and the memory cells 10b included in the memory cell group 53b are electrically connected to the bit line BLB.

[0167] The memory cells 10b included in the memory cell group 51b and the memory cell group 52b and the memory cell 10a included in the memory cell group 52a are electrically connected to the bit line BL.

[0168] Thus, the bit line BL has a region electrically connected to the memory cell 10a in the cell array 221a and a region electrically connected to the memory cell 10b in the cell array 221b. Similarly, the bit line BLB has a region electrically connected to the memory cell 10a in the cell array 221a and a region electrically connected to the memory cell 10b in the cell array 221b.

[0169] In this specification, etc., the memory cell group 51a[k,h] refers to the memory cell group 51a electrically connected to the sense amplifier 127[k,h] via the bit line BL[k,h] or the bit line BLB[k,h]. In addition, the memory cell group 52a, the memory cell group 53a, the memory cell group 51b, the memory cell group 52b, and the memory cell group 53b are similarly referred to.

[0170] Furthermore, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k+1,h] has a region overlapping with the memory cell group 52a[k,h] and a region overlapping with the memory cell group 53a[k,h]. That is, when the cell array 221a is viewed from the X direction (row direction), the bit line BLB[k+1,h] has a region overlapping with the bit line BL[k,h] and a region overlapping with the bit line BLB[k,h].

[0171] In addition, when the cell array 221a is viewed from the Z direction, the memory cell group 51a[k+1,h] has a region adjacent to the memory cell group 52a[k,h] and a region adjacent to the memory cell group 53a[k,h]. That is, when the cell array 221a is viewed from the Z direction, the bit line BLB[k+1,h] has a region adjacent to the bit line BL[k,h] and a region adjacent to the bit line BLB[k,h].

[0172] Furthermore, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k+1,h] has a region overlapping with the memory cell group 52b[k,h] and a region overlapping with the memory cell group 53b[k,h]. That is, when the cell array 221b is viewed from the X direction (row direction), the bit line BL[k+1,h] has a region overlapping with the bit line BL[k,h] and a region overlapping with the bit line BLB[k,h].

[0173] In addition, when the cell array 221b is viewed from the Z direction, the memory cell group 51b[k+1,h] has a region adjacent to the memory cell group 52b[k,h] and a region adjacent to the memory cell group 53b[k,h]. That is, when the cell array 221b is viewed from the Z direction, the bit line BL[k+1,h] has a region adjacent to the bit line BL[k,h] and a region adjacent to the bit line BLB[k,h].

[0174] The parasitic capacitance of the bit line BL and the parasitic capacitance of the bit line BLB vary according to the number of memory cells electrically connected to each bit line.

[0175] In addition, in the cell array 221a, the capacitance values ​​of the parasitic capacitance Cpa1 generated between the bit line BL[k,h] and the bit line BLB[k+1,h] and the parasitic capacitance Cpa2 generated between the bit line BLB[k,h] and the bit line BLB[k+1,h] are preferably equal (see Figure 5 ). Specifically, the capacitance value of the parasitic capacitor Cpa1 is preferably 0.8 times or more and 1.2 times or less of the parasitic capacitor Cpa2, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less. By making the capacitance values ​​of the parasitic capacitor Cpa1 and the parasitic capacitor Cpa2 equal or close, it can be less susceptible to noise.

[0176] Therefore, it is preferred that the number B of the storage cells 10a of the storage cell group 52a[k,h] is the same as the number C of the storage cells 10a of the storage cell group 53a[k,h]. Specifically, C is preferably 0.8 times or more and 1.2 times or less of B, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0177] In this case, the parasitic capacitance Cpa1 and parasitic capacitance Cpa2 are equivalent to Fig.27B1 One and the other of the parasitic capacitance CpA and the parasitic capacitance CpB are shown.

[0178] In addition, in the cell array 221b, the capacitance values ​​of the parasitic capacitance Cpb1 generated between the bit line BL[k,h] and the bit line BL[k+1,h] and the parasitic capacitance Cpb2 generated between the bit line BLB[k,h] and the bit line BL[k+1,h] are preferably equal. Specifically, the capacitance value of the parasitic capacitance Cpb1 is preferably greater than 0.8 times and less than 1.2 times the parasitic capacitance Cpb2, more preferably greater than 0.9 times and less than 1.1 times, and further preferably greater than 0.95 times and less than 1.05 times. By making the capacitance values ​​of the parasitic capacitance Cpb1 and the parasitic capacitance Cpb2 equal or close, it can be less susceptible to noise.

[0179] Therefore, it is preferred that the number E of the storage cells 10b of the storage cell group 52b[k,h] is the same as the number F of the storage cells 10a of the storage cell group 53b[k,h]. Specifically, F is preferably 0.8 times or more and 1.2 times or less of E, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0180] In this case, the parasitic capacitance Cpb1 and the parasitic capacitance Cpb2 are equivalent to Fig.27B1 One and the other of the parasitic capacitance CpA and the parasitic capacitance CpB are shown.

[0181] In addition, the bit line BL[k,h] is sometimes affected by noise from the bit line BL[k+1,h] and the bit line BLB[k+1,h]. In this case, the capacitance values ​​of the parasitic capacitor Cpa1 and the parasitic capacitor Cpb1 are preferably equal. Specifically, the capacitance value of the parasitic capacitor Cpa1 is preferably 0.8 times or more and 1.2 times or less of the parasitic capacitor Cpb1, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less. By making the capacitance values ​​of the parasitic capacitor Cpa1 and the parasitic capacitor Cpb1 equal or close, it can be less susceptible to noise.

[0182] Therefore, it is preferred that the number B of the storage cells 10a in the storage cell group 52a[k,h] is the same as the number E of the storage cells 10b in the storage cell group 52b[k,h]. Specifically, E is preferably 0.8 times or more and 1.2 times or less of B, more preferably 0.9 times or more and 1.1 times or less, and even more preferably 0.95 times or more and 1.05 times or less.

[0183] In this case, the parasitic capacitance Cpa1 and parasitic capacitance Cpb1 are equivalent to Fig.27B1 One and the other of the parasitic capacitance CpA and the parasitic capacitance CpB are shown.

[0184] In addition, the bit line BLB[k,h] is sometimes affected by noise from the bit line BL[k+1,h] and the bit line BLB[k+1,h]. In this case, the capacitance values ​​of the parasitic capacitor Cpa2 and the parasitic capacitor Cpb2 are preferably equal. Specifically, the capacitance value of the parasitic capacitor Cpa2 is preferably 0.8 times or more and 1.2 times or less of the parasitic capacitor Cpb2, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less. By making the capacitance values ​​of the parasitic capacitor Cpa2 and the parasitic capacitor Cpb2 equal or close, it can be less susceptible to noise.

[0185] Therefore, it is preferred that the number C of storage cells 10a in storage cell group 53a[k,h] is the same as the number F of storage cells 10b in storage cell group 53b[k,h]. Specifically, F is preferably 0.8 times or more and 1.2 times or less of C, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0186] In this case, the parasitic capacitance Cpa2 and the parasitic capacitance Cpb2 are equivalent to Fig.27B1One and the other of the parasitic capacitance CpA and the parasitic capacitance CpB are shown.

[0187] The number A of the storage cells 10a of the storage cell group 51a[k+1,h] is preferably the same as the sum of the number B of the storage cells 10a of the storage cell group 52a[k,h] and the number C of the storage cells 10a of the storage cell group 53a[k,h]. Specifically, the sum of B and C is preferably 0.8 times or more and 1.2 times or less of A, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0188] In addition, the number B of the storage cells 10a of the storage cell group 52a[k,h] is preferably the same or substantially the same as the number C of the storage cells 10a of the storage cell group 53a[k,h]. Specifically, B is preferably 0.8 times or more and 1.2 times or less of C, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0189] In addition, the number E of the storage cells 10b of the storage cell group 52b[k,h] is preferably the same or substantially the same as the number F of the storage cells 10b of the storage cell group 53b[k,h]. Specifically, E is preferably 0.8 times or more and 1.2 times or less of F, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0190] In addition, the number D of the storage cells 10b of the storage cell group 51b[k+1,h] is preferably the same as the sum of the number E of the storage cells 10b of the storage cell group 52b[k,h] and the number F of the storage cells 10b of the storage cell group 53b[k,h]. Specifically, the sum of E and F is preferably 0.8 times or more and 1.2 times or less of D, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0191] According to one embodiment of the present invention, the same noise reduction effect as the crossing bit line pair method can be obtained without providing a crossing portion generated by the crossing bit line pair method. That is, the reliability of the memory device 100 and the mounting density of the memory cells can be improved.

[0192] [Storage Unit]

[0193] Fig. 6AAn example of a circuit structure that can be used for the memory cell 10a and the memory cell 10b is shown. The memory cell 10a and the memory cell 10b include a transistor M1 and a capacitor element CA. The transistor M1 includes a front gate (sometimes referred to as a gate) and a back gate. The back gate is configured in a manner such that a channel forming region of a semiconductor layer is sandwiched between the back gate and the gate. By changing the potential of the back gate, the threshold voltage of the transistor can be changed. The potential of the back gate can be equal to that of the gate, or can be an arbitrary fixed potential such as the ground potential GND.

[0194] One of the source or drain of transistor M1 is electrically connected to one electrode of capacitor CA, the other of the source or drain of transistor M1 is electrically connected to bit line BL or bit line BLB, the gate of transistor M1 is electrically connected to word line WLa or word line WLb, and the back gate of transistor M1 is electrically connected to wiring BGL. The other electrode of capacitor CA is electrically connected to wiring CAL.

[0195] The wiring CAL is a wiring for applying a predetermined potential to the other electrode of the capacitor element CA. When writing data or reading data, it is preferable to apply a low-level potential (sometimes also referred to as a reference potential) to the wiring CAL.

[0196] The wiring BGL is a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0197] Data is written and read by supplying a potential for turning on transistor M1 to word line WLa and / or word line WLb to turn on transistor M1, thereby electrically connecting bit line BL or bit line BLB to one electrode of capacitor CA.

[0198] Figure 6B The circuit configuration example shown can be used for the memory cell 10a and the memory cell 10b. Figure 6B In the circuit structure example shown, the back gate of the transistor M1 is electrically connected to the word line WLa or the word line WLb but not to the wiring BGL. By adopting this structure, the same potential as the gate of the transistor M1 can be applied to the back gate of the transistor M1, thereby increasing the current (on-state current) flowing between the source and drain of the transistor M1 when the transistor M1 is in the on state.

[0199] In addition, the transistor M1 may also be a transistor with a single gate structure, that is, a transistor without a back gate. Figure 6C A circuit configuration example is shown in which a single-gate transistor is used as the transistor M1. Figure 6C Since the transistor M1 shown does not have a back gate, the manufacturing process of the memory cell can be shortened.

[0200] In addition, as the transistor M1, it is preferable to use a transistor (also referred to as an "OS transistor") using an oxide semiconductor as a semiconductor layer in which a channel is to be formed. For example, as the semiconductor layer in which a channel is to be formed, an oxide semiconductor containing any one of indium, element M (element M is aluminum, gallium, yttrium or tin) and zinc can be used. In particular, it is preferable to use an oxide semiconductor composed of indium, gallium, and zinc as the semiconductor layer of the OS transistor.

[0201] OS transistors using oxide semiconductors containing indium, gallium, and zinc have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, transistor M1 can be used to maintain written data for a long time, thereby reducing the refresh frequency of the memory cell. Alternatively, there is no need to refresh the memory cell. In addition, since the leakage current is very low, multi-value data or analog data can be maintained in the memory cell.

[0202] Here, the temperature dependency of Id-Vg characteristics, which is one of the electrical characteristics of a transistor, will be described. Fig. 7A and Figure 7B An example of Id-Vg characteristics, which are one of the electrical characteristics of a transistor, is shown. The Id-Vg characteristics represent changes in drain current (Id) with respect to changes in gate voltage (Vg). Fig. 7A and Figure 7B The horizontal axis of shows Vg on a linear scale. In addition, Fig. 7A and Figure 7B The vertical axis shows Id in a logarithmic scale.

[0203] Fig. 7A The Id-Vg characteristics of the OS transistor are shown. Figure 7B The Id-Vg characteristics of a transistor using silicon in a semiconductor layer in which a channel is formed (also referred to as a "Si transistor") are shown. Note that Fig. 7A and Figure 7B Both show the Id-Vg characteristics of n-channel transistors.

[0204] OS transistors and Si transistors have the following characteristics: the higher the temperature, the more negative the Vth drifts; the higher the temperature, the larger the subthreshold swing. As a result, the higher the temperature, the larger the Id (also called "off current") when Vg is 0V.

[0205] Even when the OS transistor is operated at high temperature, the off-state current is not likely to increase (refer to Fig. 7A ). In addition, the on-state current of OS transistors increases as the operating temperature rises. On the other hand, the off-state current of Si transistors increases and the on-state current decreases as the temperature rises (refer to Figure 7B ).

[0206] like Fig. 7A As shown, by setting Vg to a negative voltage, the off-state current of the OS transistor at high temperature can be reduced. Therefore, by using the OS transistor as the transistor M1, the power consumption of the entire semiconductor device including the transistor M1 can be reduced even when operating at high temperature.

[0207] In this specification, etc., a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). By using an OS transistor as the transistor M1, a DOSRAM can be configured.

[0208] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0209] (Implementation Method 2)

[0210] In this embodiment, a modification of the memory block 211 described in the above embodiment is described. For parts not described in this embodiment, the above embodiment can be referred to.

[0211] As described above, by stacking the cell array 221a and the cell array 221b, the mounting density of the memory cell can be doubled. However, since the total number of memory cells electrically connected to the sense amplifier 127 is also doubled, the parasitic capacitance generated in the bit line BL and the bit line BLB is also increased. This parasitic capacitance becomes a load of the sense amplifier 127, and the increase in this parasitic capacitance may become one of the causes of unstable operation of the sense amplifier 127 or a decrease in the operating speed of the memory device 100.

[0212] <Structure example>

[0213] In this embodiment, refer to Figure 8 The structure for reducing the parasitic capacitance generated in the bit lines BL and BLB is described. Figure 8 , a portion of the local sense amplifier array 214, a portion of the cell array 221a, and a portion of the cell array 221b are shown.

[0214] exist Figure 8 In the structure shown, first bit line BLf and second bit line BLs are provided instead of bit line BL, and first bit line BLBf and second bit line BLBs are provided instead of bit line BLB. That is, bit line BL is divided into first bit line BLf and second bit line BLs, and bit line BLB is divided into first bit line BLBf and second bit line BLBs.

[0215] In the present embodiment and the like, the first bit line BLf electrically connected to the sense amplifier 127[k,h] is represented by the first bit line BLf[k,h]. The same applies to the second bit line BLs, the first bit line BLBf, and the second bit line BLBs.

[0216] The sense amplifier 127 is provided with switches 231 to 234. In this embodiment and the like, the switch 231 included in the sense amplifier 127[k,h] is represented by a switch 231[k,h]. The switches 232 to 234 are also similar to this.

[0217] The first bit line BLf[k,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k,h] and the memory cell 10b included in the memory cell group 52b[k,h]. In addition, the first bit line BLf[k,h] is electrically connected to the node ND[k,h] via the switch 231[k,h]. Figure 8 The storage unit group is not explicitly shown in the figure. For more information about the storage unit group, please refer to Figure 4 .

[0218] The second bit line BLs[k,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k,h]. In addition, the second bit line BLs[k,h] is electrically connected to the node ND[k,h] via the switch 232[k,h].

[0219] The first bit line BLBf[k,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k,h] and the memory cell 10b included in the memory cell group 53b[k,h]. In addition, the first bit line BLBf[k,h] is electrically connected to the node NDB[k,h] via the switch 233[k,h].

[0220] The second bit line BLBs[k,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k,h]. In addition, the second bit line BLBs[k,h] is electrically connected to the node NDB[k,h] via the switch 234[k,h].

[0221] As the switches 231 to 234, for example, electric switches or mechanical switches can be used. For example, as the switches 231 to 234, for example, transistors or MEMS can be used. When a transistor is used as a switch, there is no particular limitation on the polarity of the transistor.

[0222] A logic circuit in which a plurality of transistors are combined may be used as the switches 231 to 234. For example, a complementary logic circuit (a logic circuit using N-channel transistors and P-channel transistors) may be used as the logic circuit.

[0223] <Working Example>

[0224] For example, when data is written or read from any of the memory cells 10a included in the memory cell group 51a[k,h] and the memory cells 10b included in the memory cell group 51b[k,h], the switches 231[k,h] and 233[k,h] are turned off (non-conducting), and the switches 232[k,h] and 234[k,h] are turned on (conducting) (see Fig. 9 ).

[0225] In other words, when any one of word lines WLa[j-6] to WLa[j-1] and word lines WLb[j-6] to WLb[j-1] is selected, switches 231[k,h] and 233[k,h] are turned off, and switches 232[k,h] and 234[k,h] are turned on.

[0226] Furthermore, for example, when data is written or read from any of the memory cells 10a included in the memory cell group 52a[k,h], the memory cells 10b included in the memory cell group 52b[k,h], the memory cells 10a included in the memory cell group 53a[k,h], and the memory cells 10b included in the memory cell group 53b[k,h], the switches 232[k,h] and 234[k,h] are turned off, and the switches 231[k,h] and 233[k,h] are turned on (see Fig.10 ).

[0227] In other words, when any one of word lines WLa[j] to WLa[j+5] and word lines WLb[j] to WLb[j+5] is selected, switches 232[k,h] and 234[k,h] are turned off, and switches 231[k,h] and 233[k,h] are turned on.

[0228] In addition, since data of all memory cells electrically connected to the selected word line WL (either word line WLa or word line WLb) are actually stored, all sense amplifiers 127 electrically connected to these memory cells need to be operated. In the present embodiment, when any of word lines WLa[j] to WLa[j+5] and word lines WLb[j] to WLb[j+5] are selected, all sense amplifiers 127 arranged in the kth row and all sense amplifiers 127 arranged in the k+1th row need to be operated.

[0229] Fig.11The following shows a case where the sense amplifier 127[k,h] is operated and the sense amplifier 127[k+1,h] is operated when any of the word lines WLa[j] to WLa[j+5] and the word lines WLb[j] to WLb[j+5] are selected. Specifically, the switches 232[k,h] and 234[k,h] included in the sense amplifier 127[k,h] are turned off, the switches 231[k,h] and 233[k,h] are turned on, the switches 231[k+1,h] and 233[k+1,h] included in the sense amplifier 127[k+1,h] are turned off, and the switches 232[k+1,h] and 234[k+1,h] are turned on.

[0230] By dividing the bit line BL and the bit line BLB and controlling the on and off states of the switches 231 to 234 according to the address of the selected word line WL (the word line WLa and the word line WLb), it is possible to reduce the parasitic capacitance that is the load of the sense amplifier 127. In this embodiment, the parasitic capacitance that is the load of the sense amplifier 127 can be reduced by half.

[0231] In addition, the operations of the switches 231 to 234 may be controlled by the local sense amplifier driver 213 .

[0232] According to one embodiment of the present invention, the stability of the operation of the sense amplifier can be improved. Thus, the reliability of the memory device 100 can be improved. In addition, according to one embodiment of the present invention, the operating speed of the sense amplifier 127 can be increased. Thus, the operating speed of the memory device 100 can be increased.

[0233] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0234] (Implementation 3)

[0235] In this embodiment, a connection example of a sense amplifier 127A, which is a 4-cell wide sense amplifier 127, and memory cells 10a and 10b is described as a modification of the memory block 211. In this specification, etc., a "4-cell wide sense amplifier" refers to a sense amplifier whose length in the X direction is equivalent to approximately four memory cells.

[0236] In addition, in order to avoid duplication of description, the following mainly describes the contents different from the above-mentioned embodiment. For the parts not described in this embodiment, the above-mentioned embodiment can be referred to.

[0237] [Structure example]

[0238] Fig.12 and Fig.131 is a three-dimensional block diagram showing the connection relationship between the sense amplifier 127A, the memory cell 10a, and the memory cell 10b. Similar to the sense amplifier 127, the sense amplifier 127A in the kth row and the hth column is represented by sense amplifier 127A[k,h].

[0239] Fig.12 Shown are sense amplifier 127A[k-2,h], sense amplifier 127A[k-1,h], sense amplifier 127A[k,h], sense amplifier 127A[k+1,h], sense amplifier 127A[k+2,h], sense amplifier 127A[k+3,h], and a memory cell electrically connected to any of these sense amplifiers 127A.

[0240] exist Fig.12 10a and 10b are electrically connected to one sense amplifier 127A, but the number of memory cells 10a and 10b electrically connected to one sense amplifier 127A is not limited thereto.

[0241] Fig.13 1 is a three-dimensional block diagram showing the connection relationship between the sense amplifier 127A, the memory cell 10a, and the memory cell 10b. Fig.13 1 and 2 show memory cells electrically connected to any one of the sense amplifiers 127A[k,h] to 127A[k+3,h]. Fig.13 , description of the word line WLa and the word line WLb is omitted. Fig.14 yes Fig.13 An enlarged view of portion 281 is shown.

[0242] Fig.15A and Fig. 15B This is a diagram showing a portion of the unit array 221b as viewed from the Z direction. Fig.16 Sense amplifiers 127A[k,h] to 127A[k+3,h] and corresponding bit lines BL and BLB are shown.

[0243] One sense amplifier 127A is electrically connected to one bit line pair. Of the bit lines BL and BLB included in the bit line pair, the bit line BL is electrically connected to the node ND of the sense amplifier 127A, and the bit line BLB is electrically connected to the node NDB of the sense amplifier 127A. The sense amplifier 127A has a function of amplifying the potential difference between the sense bit line BL and the bit line BLB.

[0244] As in the above embodiment, in this embodiment, the memory cell group 51a[k,h] represents the memory cell group 51a electrically connected to the sense amplifier 127A[k,h] via the bit line BL[k,h] or the bit line BLB[k,h]. In addition, the memory cell group 52a, the memory cell group 53a, the memory cell group 51b, the memory cell group 52b, and the memory cell group 53b are also represented.

[0245] In addition, Fig.13 and Fig.14 In the embodiment, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k+2,h] has a region overlapping with the memory cell group 52a[k,h] and a region overlapping with the memory cell group 53a[k,h]. That is, when the cell array 221a is viewed from the X direction (row direction), the bit line BLB[k+2,h] has a region overlapping with the bit line BL[k,h] and a region overlapping with the bit line BLB[k,h].

[0246] Furthermore, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k+3,h] has a region overlapping with the memory cell group 52a[k+1,h] and a region overlapping with the memory cell group 53a[k+1,h]. That is, when the cell array 221a is viewed from the X direction (row direction), the bit line BLB[k+3,h] has a region overlapping with the bit line BL[k+1,h] and a region overlapping with the bit line BLB[k+1,h].

[0247] In addition, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k+2,h] has an area overlapping with the memory cell group 52a[k,h] and the memory cell group 52a[k+1,h] and an area overlapping with the memory cell group 53a[k,h] and the memory cell group 53a[k+1,h].

[0248] In addition, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k+3,h] has an area overlapping with the memory cell group 52a[k,h] and the memory cell group 52a[k+1,h] and an area overlapping with the memory cell group 53a[k,h] and the memory cell group 53a[k+1,h].

[0249] In addition, when the cell array 221a is viewed from the Z direction, the memory cell group 51a[k+2,h] has a region adjacent to the memory cell group 52a[k,h] and a region adjacent to the memory cell group 53a[k,h]. That is, when the cell array 221a is viewed from the Z direction, the bit line BLB[k+2,h] has a region adjacent to the bit line BL[k,h] and a region adjacent to the bit line BLB[k,h].

[0250] In addition, when the cell array 221a is viewed from the Z direction, the memory cell group 51a[k+3,h] has a region adjacent to the memory cell group 52a[k+1,h] and a region adjacent to the memory cell group 53a[k+1,h]. In other words, when the cell array 221a is viewed from the Z direction, the bit line BLB[k+3,h] has a region adjacent to the bit line BL[k+1,h] and a region adjacent to the bit line BLB[k+1,h].

[0251] When the cell array 221a is viewed from the Z direction, the memory cell group 52a[k+1,h] is adjacent to the memory cell group 52a[k,h] via the memory cell group 51a[k+2,h]. The memory cell group 53a[k+1,h] is adjacent to the memory cell group 53a[k,h] via the memory cell group 51a[k+2,h].

[0252] In addition, Fig.13 and Fig.14 In the example, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k+2,h] has a region overlapping with the memory cell group 52b[k,h] and a region overlapping with the memory cell group 53b[k,h]. That is, when the cell array 221b is viewed from the X direction (row direction), the bit line BLB[k+2,h] has a region overlapping with the bit line BL[k,h] and a region overlapping with the bit line BLB[k,h].

[0253] Furthermore, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k+3,h] has a region overlapping with the memory cell group 52b[k+1,h] and a region overlapping with the memory cell group 53b[k+1,h]. That is, when the cell array 221b is viewed from the X direction (row direction), the bit line BL[k+3,h] has a region overlapping with the bit line BL[k+1,h] and a region overlapping with the bit line BLB[k+1,h].

[0254] In addition, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k+2,h] has an area overlapping with the memory cell group 52b[k,h] and the memory cell group 52b[k+1,h] and an area overlapping with the memory cell group 53b[k,h] and the memory cell group 53b[k+1,h].

[0255] In addition, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k+3,h] has an area overlapping with the memory cell group 52b[k,h] and the memory cell group 52b[k+1,h] and an area overlapping with the memory cell group 53b[k,h] and the memory cell group 53b[k+1,h].

[0256] In addition, when the cell array 221b is viewed from the Z direction, the memory cell group 51b[k+2,h] has a region adjacent to the memory cell group 52b[k,h] and a region adjacent to the memory cell group 53b[k,h]. That is, when the cell array 221b is viewed from the Z direction, the bit line BL[k+2,h] has a region adjacent to the bit line BL[k,h] and a region adjacent to the bit line BLB[k,h].

[0257] In addition, when the cell array 221b is viewed from the Z direction, the memory cell group 51b[k+3,h] has a region adjacent to the memory cell group 52b[k+1,h] and a region adjacent to the memory cell group 53b[k+1,h]. In other words, when the cell array 221b is viewed from the Z direction, the bit line BL[k+3,h] has a region adjacent to the bit line BL[k+1,h] and a region adjacent to the bit line BLB[k+1,h].

[0258] When the cell array 221b is viewed from the Z direction, the memory cell group 52b[k+1,h] is adjacent to the memory cell group 52b[k,h] via the memory cell group 51b[k+2,h]. The memory cell group 53b[k+1,h] is adjacent to the memory cell group 53b[k,h] via the memory cell group 51b[k+2,h].

[0259] Fig.15A and Fig. 15B This is a diagram showing a portion of the unit array 221 b as viewed from the Z direction. Fig.15A The storage cell group 51b[k+2,h], the storage cell group 52b[k+2,h], the storage cell group 53b[k+2,h], the storage cell group 51b[k+3,h], the storage cell group 52b[k+3,h], and the storage cell group 53b[k+3,h] are shown. Fig. 15B The storage cell group 51b[k,h], the storage cell group 52b[k,h], the storage cell group 53b[k,h], the storage cell group 51b[k+1,h], the storage cell group 52b[k+1,h], and the storage cell group 53b[k+1,h] are shown. In addition, other storage cells 10b are shown by dotted lines.

[0260] In this embodiment, the storage cell group 51b, the storage cell group 52b, and the storage cell group 53b are all arranged in the same direction along the X direction. Fig.15A and Fig. 15B , the storage cell group 51b, the storage cell group 52b, and the storage cell group 53b are arranged in order from the left with the X direction as the horizontal axis. Although not shown, the storage cell group 51a, the storage cell group 52a, and the storage cell group 53a are arranged in the same manner.

[0261] The parasitic capacitance of the bit line BL and the parasitic capacitance of the bit line BLB vary according to the number of memory cells electrically connected to each bit line. As described in the above embodiment, the parasitic capacitance of the bit line BL and the parasitic capacitance of the bit line BLB are preferably equal. By setting their capacitance values ​​to be equal or close, the influence of noise can be further reduced. For a detailed description thereof, reference can be made to the above embodiment.

[0262] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0263] (Implementation 4)

[0264] In this embodiment, a modification of the memory block 211 described in Embodiment 3 is described. For parts not described in this embodiment, refer to the above embodiment.

[0265] As described in the above embodiment, by stacking the cell array 221a and the cell array 221b, the mounting density of the memory cell can be doubled. However, since the total number of memory cells electrically connected to the sense amplifier 127A is also doubled, the parasitic capacitance generated in the bit line BL and the bit line BLB is also increased. This parasitic capacitance becomes a load of the sense amplifier 127A, and the increase in this parasitic capacitance may become one of the causes of unstable operation of the sense amplifier 127A or a decrease in the operating speed of the memory device 100.

[0266] <Structure example>

[0267] In this embodiment, refer to Fig.17 and Fig.18 The structure for reducing the parasitic capacitance generated in the bit lines BL and BLB is described. Fig.17 , a portion of the local sense amplifier array 214, a portion of the cell array 221a, and a portion of the cell array 221b are shown. Fig.18 yes Fig.17 An enlarged view of portion 282 is shown.

[0268] like Fig.17 As shown, first bit line BLf and second bit line BLs are provided instead of bit line BL, and first bit line BLBf and second bit line BLBs are provided instead of bit line BLB. That is, bit line BL is divided into first bit line BLf and second bit line BLs, and bit line BLB is divided into first bit line BLBf and second bit line BLBs.

[0269] As in the above embodiment, in this embodiment, the first bit line BLf[k,h] represents the first bit line BLf electrically connected to the sense amplifier 127A[k,h]. The same applies to the second bit line BLs, the first bit line BLBf, and the second bit line BLBs.

[0270] The sense amplifier 127A is provided with switches 231 to 234. As in the above embodiment, the switch 231 included in the sense amplifier 127A[k,h] is represented by switch 231[k,h]. The switches 232 to 234 are also the same.

[0271] The first bit line BLf[k,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k,h] and the memory cell 10b included in the memory cell group 52b[k,h]. In addition, the first bit line BLf[k,h] is electrically connected to the node ND[k,h] via the switch 231[k,h]. Fig.17 and Fig.18 The storage unit group is not explicitly shown in the figure, but the storage unit group can be referred to Fig.13 and Fig.14 .

[0272] The second bit line BLs[k,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k,h]. In addition, the second bit line BLs[k,h] is electrically connected to the node ND[k,h] via the switch 232[k,h].

[0273] The first bit line BLBf[k,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k,h] and the memory cell 10b included in the memory cell group 53b[k,h]. In addition, the first bit line BLBf[k,h] is electrically connected to the node NDB[k,h] via the switch 233[k,h]. Fig.17 and Fig.18 In the embodiment, the switch 233[k,h] is provided in the sense amplifier 127A[k+1,h], but may be provided in the sense amplifier 127A[k,h].

[0274] The second bit line BLBs[k,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k,h]. In addition, the second bit line BLBs[k,h] is electrically connected to the node NDB[k,h] via the switch 234[k,h].

[0275] In addition, the first bit line BLf[k+1,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k+1,h] and the memory cell 10b included in the memory cell group 52b[k+1,h]. In addition, the first bit line BLf[k+1,h] is electrically connected to the node ND[k+1,h] via the switch 231[k+1,h].

[0276] The second bit line BLs[k+1,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k+1,h]. In addition, the second bit line BLs[k+1,h] is electrically connected to the node ND[k+1,h] via the switch 232[k+1,h].

[0277] The first bit line BLBf[k+1,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k+1,h] and the memory cell 10b included in the memory cell group 53b[k+1,h]. In addition, the first bit line BLBf[k+1,h] is electrically connected to the node NDB[k+1,h] via the switch 233[k+1,h].

[0278] The second bit line BLBs[k+1,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k+1,h]. In addition, the second bit line BLBs[k+1,h] is electrically connected to the node NDB[k+1,h] via the switch 234[k+1,h].

[0279] The first bit line BLf[k+2,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k+2,h] and the memory cell 10b included in the memory cell group 52b[k+2,h]. In addition, the first bit line BLf[k+2,h] is electrically connected to the node ND[k+2,h] via the switch 231[k+2,h].

[0280] The second bit line BLs[k+2,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k+2,h]. In addition, the second bit line BLs[k+2,h] is electrically connected to the node ND[k+2,h] via the switch 232[k+2,h].

[0281] The first bit line BLBf[k+2,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k+2,h] and the memory cell 10b included in the memory cell group 53b[k+2,h]. In addition, the first bit line BLBf[k+2,h] is electrically connected to the node NDB[k+2,h] via the switch 233[k+2,h]. Fig.17 and Fig.18 In the embodiment, although the switch 233[k+2,h] is provided in the sense amplifier 127A[k+3,h], it may be provided in the sense amplifier 127A[k+2,h].

[0282] In addition, the first bit line BLf[k+3,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k+3,h] and the memory cell 10b included in the memory cell group 52b[k+3,h]. In addition, the first bit line BLf[k+3,h] is electrically connected to the node ND[k+3,h] via the switch 231[k+3,h].

[0283] The second bit line BLs[k+3,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k+3,h]. In addition, the second bit line BLs[k+3,h] is electrically connected to the node ND[k+3,h] via the switch 232[k+3,h].

[0284] The first bit line BLBf[k+3,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k+3,h] and the memory cell 10b included in the memory cell group 53b[k+3,h]. In addition, the first bit line BLBf[k+3,h] is electrically connected to the node NDB[k+3,h] via the switch 233[k+3,h].

[0285] The second bit line BLBs[k+3,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k+3,h]. In addition, the second bit line BLBs[k+3,h] is electrically connected to the node NDB[k+3,h] via the switch 234[k+3,h]. Fig.17 In the embodiment, although the switch 234[k+3,h] is provided in the sense amplifier 127A[k+2,h], it may be provided in the sense amplifier 127A[k+3,h].

[0286] As the switches 231 to 234, for example, electric switches or mechanical switches can be used. For example, as the switches 231 to 234, for example, transistors or MEMS can be used. When a transistor is used as a switch, there is no particular limitation on the polarity of the transistor.

[0287] A logic circuit in which a plurality of transistors are combined may be used as the switches 231 to 234. For example, a complementary logic circuit (a logic circuit using N-channel transistors and P-channel transistors) may be used as the logic circuit.

[0288] In order to understand the memory cell selection operation for writing or reading data, reference may be made to Embodiment Mode 2. Therefore, detailed description will be omitted in this embodiment mode.

[0289] By dividing the bit line BL and the bit line BLB and controlling the on and off states of the switches 231 to 234 according to the address of the selected word line WL (the word line WLa and the word line WLb), it is possible to reduce the parasitic capacitance that is the load of the sense amplifier 127. In this embodiment, the parasitic capacitance that is the load of the sense amplifier 127 can be reduced by half.

[0290] According to one embodiment of the present invention, the stability of the operation of the sense amplifier can be improved. Thus, the reliability of the memory device 100 can be improved. In addition, according to one embodiment of the present invention, the operating speed of the sense amplifier 127 can be increased. Thus, the operating speed of the memory device 100 can be increased.

[0291] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0292] (Implementation 5)

[0293] In this embodiment, a modification of the memory block 211 described in Embodiment 4 is described. For parts not described in this embodiment, refer to the above embodiment.

[0294] <Structure example>

[0295] exist Fig.19 , a portion of the local sense amplifier array 214, a portion of the cell array 221a, and a portion of the cell array 221b are shown. Fig. 20 yes Fig.19 An enlarged view of portion 283 is shown. In addition, Fig.21 yes Fig.19 An enlarged view of portion 284 is shown.

[0296] also, Fig. 22 1 is a three-dimensional block diagram showing the connection relationship between the sense amplifier 127A, the memory cell 10a, and the memory cell 10b. Fig. 22 In, omitted Fig.19 The word lines WLa and WLb are recorded in FIG. Fig.23 yes Fig. 22 An enlarged view of portion 285 is shown. In addition, Fig.24A and Fig. 24B This is a diagram showing a portion of the unit array 221b as viewed from the Z direction. Fig.25 Sense amplifiers 127A[k-1,h] to 127A[k+3,h] and corresponding bit lines BL and BLB are shown.

[0297] The first bit line BLf[k,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k,h] and the memory cell 10b included in the memory cell group 52b[k,h]. In addition, the first bit line BLf[k,h] is electrically connected to the node ND[k,h] via the switch 231[k,h]. Fig.19 , Fig. 20 as well as Fig.21 The storage unit group is not explicitly shown in the figure, but the storage unit group can be referred to Fig. 22 and Fig.23 .

[0298] The second bit line BLs[k,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k,h]. In addition, the second bit line BLs[k,h] is electrically connected to the node ND[k,h] via the switch 232[k,h].

[0299] The first bit line BLBf[k,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k,h] and the memory cell 10b included in the memory cell group 53b[k,h]. In addition, the first bit line BLBf[k,h] is electrically connected to the node NDB[k,h] via the switch 233[k,h]. Fig.19 and Fig. 20 In the embodiment, the switch 233[k,h] is provided in the sense amplifier 127A[k+1,h], but may be provided in the sense amplifier 127A[k,h].

[0300] The second bit line BLBs[k,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k,h]. In addition, the second bit line BLBs[k,h] is electrically connected to the node NDB[k,h] via the switch 234[k,h].

[0301] In addition, the first bit line BLf[k+1,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k+1,h] and the memory cell 10b included in the memory cell group 53b[k+1,h]. In addition, the first bit line BLf[k+1,h] is electrically connected to the node ND[k+1,h] via the switch 231[k+1,h]. Fig.19 and Fig. 20 In the embodiment, the switch 231[k+1,h] is provided in the sense amplifier 127A[k,h], but may be provided in the sense amplifier 127A[k+1,h].

[0302] The second bit line BLs[k+1,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k+1,h]. In addition, the second bit line BLs[k+1,h] is electrically connected to the node ND[k+1,h] via the switch 232[k+1,h].

[0303] The first bit line BLBf[k+1,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k+1,h] and the memory cell 10b included in the memory cell group 52b[k+1,h]. In addition, the first bit line BLBf[k+1,h] is electrically connected to the node NDB[k+1,h] via the switch 233[k+1,h].

[0304] The second bit line BLBs[k+1,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k+1,h]. In addition, the second bit line BLBs[k+1,h] is electrically connected to the node NDB[k+1,h] via the switch 234[k+1,h].

[0305] The first bit line BLf[k-1,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k-1,h] and the memory cell 10b included in the memory cell group 52b[k-1,h]. In addition, the first bit line BLf[k-1,h] is electrically connected to the node ND[k-1,h] via the switch 231[k-1,h].

[0306] The second bit line BLs[k-1,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k-1,h]. In addition, the second bit line BLs[k-1,h] is electrically connected to the node ND[k-1,h] via the switch 232[k-1,h].

[0307] The first bit line BLBf[k-1,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k-1,h] and the memory cell 10b included in the memory cell group 53b[k-1,h]. In addition, the first bit line BLBf[k-1,h] is electrically connected to the node NDB[k-1,h] via the switch 233[k-1,h]. Fig.19 and Fig.21 In the embodiment, the switch 233[k-1,h] is provided in the sense amplifier 127A[k-2,h], but may be provided in the sense amplifier 127A[k-1,h].

[0308] The second bit line BLBs[k-1,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k-1,h]. In addition, the second bit line BLBs[k-1,h] is electrically connected to the node NDB[k-1,h] via the switch 234[k-1,h].

[0309] In addition, the first bit line BLf[k+2,h] is electrically connected to the memory cell 10a included in the memory cell group 53a[k+2,h] and the memory cell 10b included in the memory cell group 53b[k+2,h]. In addition, the first bit line BLf[k+2,h] is electrically connected to the node ND[k+2,h] via the switch 231[k+2,h]. Fig.19 In the embodiment, although the switch 231[k+2,h] is provided in the sense amplifier 127A[k+3,h], it may be provided in the sense amplifier 127A[k+2,h].

[0310] The second bit line BLs[k+2,h] is electrically connected to the memory cell 10b included in the memory cell group 51b[k+2,h]. In addition, the second bit line BLs[k+2,h] is electrically connected to the node ND[k+2,h] via the switch 232[k+2,h].

[0311] The first bit line BLBf[k+2,h] is electrically connected to the memory cell 10a included in the memory cell group 52a[k+2,h] and the memory cell 10b included in the memory cell group 52b[k+2,h]. In addition, the first bit line BLBf[k+2,h] is electrically connected to the node NDB[k+2,h] via the switch 233[k+2,h].

[0312] The second bit line BLBs[k+2,h] is electrically connected to the memory cell 10a included in the memory cell group 51a[k+2,h]. In addition, the second bit line BLBs[k+2,h] is electrically connected to the node NDB[k+2,h] via the switch 234[k+2,h].

[0313] In addition, Fig. 22 and Fig.23 In the embodiment, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k+2,h] has a region overlapping with the memory cell group 52a[k,h] and a region overlapping with the memory cell group 53a[k,h]. That is, when the cell array 221a is viewed from the X direction (row direction), the bit line BLBs[k+2,h] has a region overlapping with the bit line BLf[k,h] and a region overlapping with the bit line BLBf[k,h].

[0314] Furthermore, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k-1,h] has a region overlapping with the memory cell group 52a[k+1,h] and a region overlapping with the memory cell group 53a[k+1,h]. That is, when the cell array 221a is viewed from the X direction (row direction), the bit line BLBs[k-1,h] has a region overlapping with the bit line BLBf[k+1,h] and a region overlapping with the bit line BLf[k+1,h].

[0315] In addition, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k+2,h] has an area overlapping with the memory cell group 52a[k,h] and the memory cell group 53a[k+1,h] and an area overlapping with the memory cell group 53a[k,h] and the memory cell group 52a[k+1,h].

[0316] In addition, when the cell array 221a is viewed from the X direction (row direction), the memory cell group 51a[k-1,h] has an area overlapping with the memory cell group 52a[k,h] and the memory cell group 53a[k+1,h] and an area overlapping with the memory cell group 53a[k,h] and the memory cell group 52a[k+1,h].

[0317] In addition, when the cell array 221a is viewed from the Z direction, the memory cell group 51a[k+2,h] has a region adjacent to the memory cell group 52a[k,h] and a region adjacent to the memory cell group 53a[k,h]. That is, when the cell array 221a is viewed from the Z direction, the bit line BLBs[k+2,h] has a region adjacent to the bit line BLf[k,h] and a region adjacent to the bit line BLBf[k,h].

[0318] In addition, when the cell array 221a is viewed from the Z direction, the memory cell group 51a[k-1,h] has a region adjacent to the memory cell group 53a[k+1,h] and a region adjacent to the memory cell group 52a[k+1,h]. That is, when the cell array 221a is viewed from the Z direction, the bit line BLBs[k-1,h] has a region adjacent to the bit line BLf[k+1,h] and a region adjacent to the bit line BLBf[k+1,h].

[0319] When the cell array 221a is viewed from the Z direction, the memory cell group 53a[k+1,h] and the memory cell group 52a[k,h] are adjacent to each other via the memory cell group 51a[k+2,h]. The memory cell group 52a[k+1,h] and the memory cell group 53a[k,h] are adjacent to each other via the memory cell group 51a[k+2,h].

[0320] In addition, Fig. 22 and Fig.23In the embodiment, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k+2,h] has a region overlapping with the memory cell group 52b[k,h] and a region overlapping with the memory cell group 53b[k,h]. That is, when the cell array 221b is viewed from the X direction (row direction), the bit line BLs[k+2,h] has a region overlapping with the bit line BLf[k,h] and a region overlapping with the bit line BLBf[k,h].

[0321] Furthermore, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k-1,h] has a region overlapping with the memory cell group 52b[k+1,h] and a region overlapping with the memory cell group 53b[k+1,h]. That is, when the cell array 221b is viewed from the X direction (row direction), the bit line BLs[k-1,h] has a region overlapping with the bit line BLf[k+1,h] and a region overlapping with the bit line BLBf[k+1,h].

[0322] In addition, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k+2,h] has an area overlapping with the memory cell group 52b[k,h] and the memory cell group 53b[k+1,h] and an area overlapping with the memory cell group 53b[k,h] and the memory cell group 52b[k+1,h].

[0323] In addition, when the cell array 221b is viewed from the X direction (row direction), the memory cell group 51b[k-1,h] has an area overlapping with the memory cell group 52b[k,h] and the memory cell group 53b[k+1,h] and an area overlapping with the memory cell group 53b[k,h] and the memory cell group 52b[k+1,h].

[0324] In addition, when the cell array 221b is viewed from the Z direction, the memory cell group 51b[k+2,h] has a region adjacent to the memory cell group 52b[k,h] and a region adjacent to the memory cell group 53b[k,h]. That is, when the cell array 221b is viewed from the Z direction, the bit line BLs[k+2,h] has a region adjacent to the bit line BLf[k,h] and a region adjacent to the bit line BLBf[k,h].

[0325] In addition, when the cell array 221b is viewed from the Z direction, the memory cell group 51b[k-1,h] has a region adjacent to the memory cell group 53b[k+1,h] and a region adjacent to the memory cell group 52b[k+1,h]. That is, when the cell array 221b is viewed from the Z direction, the bit line BLs[k-1,h] has a region adjacent to the bit line BLf[k+1,h] and a region adjacent to the bit line BLBf[k+1,h].

[0326] When the cell array 221b is viewed from the Z direction, the memory cell group 53b[k+1,h] is adjacent to the memory cell group 52b[k,h] via the memory cell group 51b[k+2,h]. The memory cell group 52b[k+1,h] is adjacent to the memory cell group 53b[k,h] via the memory cell group 51b[k+2,h].

[0327] Fig.24A and Fig. 24B This is a diagram showing a portion of the unit array 221 b as viewed from the Z direction. Fig.24A The storage cell group 51b[k+2,h], the storage cell group 52b[k+2,h], the storage cell group 53b[k+2,h], the storage cell group 51b[k-1,h], the storage cell group 52b[k-1,h], and the storage cell group 53b[k-1,h] are shown. Fig. 24B The storage cell group 51b[k,h], the storage cell group 52b[k,h], the storage cell group 53b[k,h], the storage cell group 51b[k+1,h], the storage cell group 52b[k+1,h], and the storage cell group 53b[k+1,h] are shown. In addition, other storage cells 10b are shown by dotted lines.

[0328] In this embodiment, the memory cell group electrically connected to the read amplifier 127A[k,h] (memory cell group 51b[k,h], memory cell group 52b[k,h], and memory cell group 53b[k,h]) and the memory cell group electrically connected to the read amplifier 127A[k+2,h] (memory cell group 51b[k+2,h], memory cell group 52b[k+2,h], and memory cell group 53b[k+2,h]) are arranged in the same direction.

[0329] Specifically, in Fig.24A and Fig. 24B In the figure, the storage cell group 51b[k,h], the storage cell group 52b[k,h] and the storage cell group 53b[k,h] are arranged in order from the left with the X direction as the horizontal axis. Similarly, the storage cell group 51b[k+2,h], the storage cell group 52b[k+2,h] and the storage cell group 53b[k+2,h] are arranged in order from the left.

[0330] In addition, the memory cell group electrically connected to the read amplifier 127A[k+1,h] (memory cell group 51b[k+1,h], memory cell group 52b[k+1,h], and memory cell group 53b[k+1,h]) and the memory cell group electrically connected to the read amplifier 127A[k-1,h] (memory cell group 51b[k-1,h], memory cell group 52b[k-1,h], and memory cell group 53b[k-1,h]) are arranged in the same direction.

[0331] Specifically, in Fig.24A and Fig. 24B In the figure, the storage cell group 51b[k+1,h], the storage cell group 52b[k+1,h] and the storage cell group 53b[k+1,h] are arranged in order from the right with the X direction as the horizontal axis. Similarly, the storage cell group 51b[k-1,h], the storage cell group 52b[k-1,h] and the storage cell group 53b[k-1,h] are arranged in order from the right.

[0332] Thus, the arrangement direction of the memory cell groups is different between the memory cell group electrically connected to the sense amplifier 127A[k,h] and the memory cell group electrically connected to the sense amplifier 127A[k+2,h] and the memory cell group electrically connected to the sense amplifier 127A[k+1,h] and the memory cell group electrically connected to the sense amplifier 127A[k-1,h]. Although not shown, the memory cell group 51a, the memory cell group 52a, and the memory cell group 53a are arranged in the same manner.

[0333] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0334] (Implementation method 6)

[0335] In this embodiment mode, a circuit configuration example of the sense amplifier 127 included in the local sense amplifier array 214 and an operation example of the memory device 100 are described with reference to the drawings.

[0336] <Circuit Configuration Example>

[0337] Fig.28 A circuit configuration example of the sense amplifier 127[k,h] is shown. Fig.28 The sense amplifier 127[k,h] shown includes a precharge circuit 132, an amplifier circuit 133, and an input-output circuit 134. In this embodiment and the like, the precharge circuit 132[k,h], the amplifier circuit 133[k,h], and the input-output circuit 134[k,h] represent the precharge circuit 132[k,h], the amplifier circuit 133[k,h], and the input-output circuit 134[k,h] included in the sense amplifier 127[k,h].

[0338] also, Fig.28 1 and 2 show a memory cell 10a electrically connected to a sense amplifier 127[k,h] via a wiring BLf[k,h] and a memory cell 10a electrically connected to a sense amplifier 127[k,h] via a wiring BLBf[k,h]. Fig.28 In the example, the use of Figure 6C The memory cell is shown as an example of the memory cell 10a.

[0339] [Precharge circuit 132]

[0340] The precharge circuit 132 [k, h] includes n-channel transistors Tr21 to Tr23. Alternatively, the transistors Tr21 to Tr23 may be p-channel transistors.

[0341] One of the source and drain of the transistor Tr21 is electrically connected to the wiring BLf[k,h], and the other of the source and drain is electrically connected to the wiring PRE. A node between one of the source and drain of the transistor Tr21 and the wiring BLf[k,h] is a node ND[k,h].

[0342] One of the source and drain of the transistor Tr22 is electrically connected to the wiring BLBf[k,h], and the other of the source and drain is electrically connected to the wiring PRE. A node between one of the source and drain of the transistor Tr22 and the wiring BLBf[k,h] is a node NDB[k,h].

[0343] One of the source and drain of the transistor Tr23 is electrically connected to the wiring BLf[k,h] through the node ND[k,h], and the other of the source and drain is electrically connected to the wiring BLBf[k,h] through the node NDB[k,h]. The gate of the transistor Tr21, the gate of the transistor Tr22, and the gate of the transistor Tr23 are electrically connected to the wiring PL.

[0344] The precharge circuit 132[k,h] has a function of initializing the potential of the wiring BLf[k,h] and the wiring BLBf[k,h].

[0345] [Amplifier circuit 133]

[0346] The amplifier circuit 133 [k, h] includes p-channel transistors Tr31 and Tr32 and n-channel transistors Tr33 and Tr34 .

[0347] One of the source and the drain of the transistor Tr31 is electrically connected to the wiring SP, and the other of the source and the drain is electrically connected to the gate of the transistor Tr32 , the gate of the transistor Tr34 , the node ND[k,h], and the wiring BLf[k,h].

[0348] One of the source and the drain of the transistor Tr33 is electrically connected to the gate of the transistor Tr32 , the gate of the transistor Tr34 , the node NDB[k,h], and the wiring BLf[k,h], and the other of the source and the drain is electrically connected to the wiring SN.

[0349] One of the source and the drain of the transistor Tr32 is electrically connected to the wiring SP, and the other of the source and the drain is electrically connected to the gate of the transistor Tr31, the gate of the transistor Tr33, the node NDB[k,h], and the wiring BLBf[k,h].

[0350] One of the source and the drain of the transistor Tr34 is electrically connected to the gate of the transistor Tr31 , the gate of the transistor Tr33 , the node NDB[k,h], and the wiring BLBf[k,h], and the other of the source and the drain is electrically connected to the wiring SN.

[0351] The amplifier circuit 133[k,h] has a function of amplifying the potential of the wiring BLf[k,h] and the wiring BLBf[k,h]. The amplifier circuit 133[k,h] is used as a latch-type sense amplifier.

[0352] [Input-output circuit 134]

[0353] The input / output circuit 134[k,h] includes an n-channel transistor Tr41 and a transistor Tr42. Alternatively, the transistor Tr41 and the transistor Tr42 may be p-channel transistors.

[0354] One of the source and drain of the transistor Tr41 is electrically connected to the node ND[k,h] and the wiring BLf[k,h], and the other of the source and drain thereof is electrically connected to the wiring SALa[k]. One of the source and drain of the transistor Tr42 is electrically connected to the node NDB[k,h] and the wiring BLBf[k,h], and the other of the source and drain thereof is electrically connected to the wiring SALb[k]. The gate of the transistor Tr41 and the gate of the transistor Tr42 are electrically connected to the wiring CSEL.

[0355] The input / output circuit 134[k,h] has a function of controlling the conduction state between the wiring BLf[k,h] and the wiring SALa[k] and the conduction state between the wiring BLBf[k,h] and the wiring SALb[k] according to the potential supplied to the wiring CSEL. In other words, the input / output circuit 134[k,h] can select whether to output a potential to the wiring SALa[k] and the wiring SALb[k].

[0356] The wiring SP, wiring SN, wiring CSEL, wiring PRE, and wiring PL have the function of transmitting signals for controlling the operation of the precharge circuit 132, the amplifier circuit 133, and the input / output circuit 134. The wiring SP, wiring SN, wiring CSEL, wiring PRE, and wiring PL are electrically connected to Figure 1 The control circuit 112 shown in FIG. The control circuit 112 has a function of supplying a control signal to the wiring SP, the wiring SN, the wiring CSEL, the wiring PRE, and the wiring PL.

[0357] <Working Example>

[0358] Next, an operation example of the storage device 100 will be described. Fig.28 The operation example of the sense amplifier 127 and the memory cell 10a is shown. In this embodiment, four operation modes (read mode, write mode, refresh mode, and hold mode) are described. The memory cell 10a and the memory cell 10b are both storage elements capable of storing 1 bit of information.

[0359] [Read Mode]

[0360] The read mode refers to an operation mode when reading out the information stored in the memory cell 10a or the memory cell 10b. Fig.29 The timing chart shown in the figure explains an operation example of the read mode. As an example, the operation of reading out information stored in the memory cell 10a electrically connected to the wiring BLf[k,h] and the word line WLa[j] is explained.

[0361] [Period T11]

[0362] During period T11, the precharge circuit 132[k,h] is operated so that the potential of the wiring BLf[k,h] and the wiring BLBf[k,h] is initialized. Specifically, the potential of the wiring PL is VDD, so that the transistors Tr21 to Tr23 are turned on. Thus, the potential Vpre (also called "Vpre") of the wiring PRE is supplied to the wiring BLf[k,h] and the wiring BLBf[k,h]. Note that the potential Vpre is a potential that exceeds VSS and is lower than VDD. In this embodiment, the potential Vpre is set to (VDD+VSS) / 2. In this embodiment, VDD is set to 1.5V, VSS is set to 0V, and Vpre is set to 0.75V.

[0363] In the period T11, the potential of the wiring CSEL is VSS, and in the input / output circuit 134[k,h], the transistor Tr41 and the transistor Tr42 are in the off state. In the period T11, the potential of the wiring CSEL may be set to a potential VNN described later.

[0364] In addition, the potential of the word line WLa[j] is the potential VNN, and the transistor M1 of the memory cell 10a is in the off state. In the present embodiment, the memory cell 10a is a 1-bit storage element, and thus the memory cell 10a stores VDD or VSS. The potential VNN (also referred to as "VNN") is a potential that turns the transistor M1 off. Therefore, VNN is preferably a potential below VSS. In addition, VNN is more preferably a potential lower than VSS.

[0365] When VSS is a standard potential (0V), a potential lower than VSS is sometimes referred to as a "negative potential", "negative voltage" or "negative bias". As described above, VNN is preferably a negative potential. In other words, VNN is preferably a potential lower than the source potential and the drain potential of the transistor M1. In this embodiment, VNN is -0.5V.

[0366] By setting VNN supplied to the word line WLa[j] to a negative potential, the transistor M1 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0367] Similar to the word line WLa[j], the potential of the word line WLa[j+5] is VNN, and the transistor M1 included in the memory cell 10a electrically connected to the word line WLa[j+5] is in the off state.

[0368] In addition, the potential of the wiring SP and the wiring SN is the potential Vpre, and the amplifier circuit 133 [k, h] is in a stopped state.

[0369] [Period T12]

[0370] During period T12, the potential of wiring PL is set to VSS or VNN, so that transistors Tr21 to Tr23 are turned off. In this case, VNN is preferably a potential lower than the source potential and drain potential of transistors Tr21 to Tr23. In other words, VNN is preferably a negative potential.

[0371] Furthermore, during the period T12, the word line WLa[j] is placed in a selected state. Specifically, the potential of the word line WLa[j] is set to the potential VPP, so that the transistor M1 included in the memory cell 10a is turned on.

[0372] The potential VPP (also referred to as "VPP") is a potential at which the transistor M1 is turned on, and thus VPP is preferably a potential higher than VDD. In addition, VPP is more preferably a potential higher than VDD. In particular, VPP is further preferably a potential higher than VDD by more than the Vth of the transistor M1. In the present embodiment, VPP is 3.0V.

[0373] Thus, in the memory cell 10a electrically connected to the word line WLa[j], the wiring BLf[k,h] and the capacitor CA are turned on by the transistor M1, so that the potential of the wiring BLf[k,h] changes according to the amount of charge held in the capacitor CA.

[0374] exist Fig.29, the case where the memory cell 10a stores data "1" and the amount of charge stored in the capacitor CA is large. When the amount of charge stored in the capacitor CA is large, the charge is released from the capacitor CA to the wiring BLf[k,h], causing the potential of the wiring BLf[k,h] to rise by △V1 from the potential Vpre. On the other hand, when the memory cell 10a stores data "0" and the amount of charge stored in the capacitor CA is small, the charge flows from the wiring BLf[k,h] into the capacitor CA, causing the potential of the wiring BLf[k,h] to drop by △V2 (not shown).

[0375] In addition, during period T12, the potential of wiring CSEL is VSS or VNN, and transistors Tr41 and Tr42 in input / output circuit 134[k,h] are in an off state. In this case, VNN is preferably a potential lower than the source potential and drain potential of transistors Tr41 and Tr42. In other words, VNN is preferably a negative potential.

[0376] In addition, the potentials of the wirings SP and SN are at the potential Vpre. The amplifier circuit 133 [k, h] maintains the stopped state.

[0377] [Period T13]

[0378] During period T13, the potential of wiring SP is changed to VDD, and the potential of wiring SN is changed to VSS. Then, the amplifier circuit 133[k,h] is in operation. The amplifier circuit 133[k,h] has a potential difference (at Fig.29 The function is equivalent to △V1).

[0379] When the amplifier circuit 133[k,h] is in the operating state, the potential of the wiring BLf[k,h] changes from Vpre+ΔV1 to VDD. Also, the potential of the wiring BLBf[k,h] changes from Vpre to VSS.

[0380] When the potential of wiring BLf[k,h] is Vpre-ΔV2 at the beginning of period T13, the potential of wiring BLf[k,h] changes from Vpre-ΔV2 to VSS by operating amplifier circuit 133[k,h]. Also, the potential of wiring BLBf[k,h] changes from Vpre to VDD.

[0381] Furthermore, in the period T13 , the potential of the wiring PL is VSS or VNN, and the transistors Tr21 to Tr23 are turned off in the precharge circuit 132 [k, h].

[0382] In addition, the potential of the wiring CSEL is VSS or VNN, and the transistor Tr41 and the transistor Tr42 are turned off in the input-output circuit 134[k,h]. In addition, the potential of the word line WLa[j] is VPP, and the transistor M1 of the memory cell 10a electrically connected to the word line WLa[j] is turned on. As a result, in the memory cell 10a, the amount of charge corresponding to the potential (VDD) of the wiring BLf[k,h] is stored in the capacitor element CA.

[0383] [Period T14]

[0384] During period T14, the potential of the wiring CSEL is controlled to turn on the input / output circuit 134[k,h]. Specifically, the potential of the wiring CSEL is set to VDD or VPP, so that the transistor Tr41 and the transistor Tr42 are turned on. As a result, the potential of the wiring BLf[k,h] is supplied to the wiring SALa[k], and the potential of the wiring BLBf[k,h] is supplied to the wiring SALb[k].

[0385] In addition, during period T14, the potential of wiring PL is VSS or VNN, and transistors Tr21 to Tr23 are turned off in precharge circuit 132[k,h]. In addition, the potential of word line WLa[j] is VPP, and transistor M1 of memory cell 10a is turned on. In addition, the potential of wiring SP is VDD, the potential of wiring SN is VSS, and amplifier circuit 133[k,h] is in operation. Thus, in memory cell 10a electrically connected to word line WLa[j], a charge corresponding to the potential (VDD) of wiring BLf[k,h] is supplied through wiring BLf[k,h] and stored in capacitor element CA.

[0386] [Period T15]

[0387] In the period T15, the potential of the wiring CSEL is controlled to turn off the input / output circuit 134[k,h]. Specifically, the potential of the wiring CSEL is set to VSS or VNN to turn off the transistor Tr41 and the transistor Tr42.

[0388] In addition, during period T15, the word line WLa[j] is placed in a non-selected state. Specifically, the potential of the word line WLa[j] is VNN. As a result, the transistor of the memory cell 10a electrically connected to the word line WLa[j] is turned off. As a result, the charge corresponding to VDD is stored in the capacitor element CA of the memory cell 10a. Therefore, even after the data is read, the data is retained in the memory cell 10a.

[0389] By setting VNN supplied to the word line WLa[j] to a negative potential, the transistor M1 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0390] Furthermore, during period T15, even if the input / output circuit 134[k,h] is in the off state, as long as the amplifier circuit 133[k,h] is in the operating state, the potential of the wiring BLf[k,h] and the wiring BLBf[k,h] is maintained by the amplifier circuit AC. Thus, the sense amplifier 127[k,h] has the function of temporarily maintaining the information read from the memory cell 10a.

[0391] By performing the above operation, information can be read from the memory cell 10a. The read data is supplied to the control circuit 112 (see Figure 1 ). Note that data can also be read from other memory cells in the same manner as the memory cell 10a.

[0392] [Write Mode]

[0393] The write mode refers to the operation mode when the stored information is written into the storage unit 10a or the storage unit 10b. Fig.30 The timing chart shown in the figure explains an example of the operation in the write mode. As an example, the operation of writing information into the memory cell 10a electrically connected to the wiring BLf[k,h] and the word line WLa[j] is explained.

[0394] [Period T21]

[0395] In period T21, the same operation as in period T11 is performed to initialize the potentials of wiring BLf[k,h] and wiring BLBf[k,h]. Specifically, the potential of wiring PL is set to VDD, and the potential of wiring BLf[k,h] and wiring BLBf[k,h] is set to Vpre.

[0396] [Period T22]

[0397] During period T22, the potential of wiring PL is set to VSS or VNN, so that transistors Tr21 to Tr23 are turned off. In addition, the word line WLa[j] electrically connected to the memory cell 10a to which data is written is selected. Specifically, the potential of word line WLa[j] is set to VPP, so that the transistor M1 of the memory cell 10a is turned on. As a result, in the memory cell 10a, wiring BLf[k,h] and capacitor element CA are turned on through transistor M1.

[0398] At this time, when data “1” is stored in the memory cell 10 a , charge is discharged from the capacitor CA to the wiring BLf[k,h], so that the potential of the wiring BLf[k,h] rises from the potential Vpre by ΔV1 .

[0399] [Period T23]

[0400] In the period T23 , the potential of the wiring SP is set to VDD, and the potential of the wiring SN is set to VSS, so that the amplifier circuit 133 [k, h] is in an operating state.

[0401] [Period T24]

[0402] In period T24, the potential of the wiring CSEL is controlled to turn off the input / output circuit 134[k,h]. As a result, the wiring BLf[k,h] and the wiring SALa[k] are in conduction. In addition, the wiring BLBf[k,h] and the wiring SALb[k] are in conduction.

[0403] The data signal WDATA is supplied to the input-output circuit 134[k,h] through the wiring SALa[k] and the wiring SALb[k]. By supplying a write potential corresponding to the data signal WDATA to the wiring SALa[k] and the wiring SALb[k], the write potential is supplied to the wiring BLf[k,h] and the wiring BLBf[k,h] through the input-output circuit 134[k,h]. For example, when data "0" is stored in the memory cell 10a, VSS is supplied to the wiring SALa[k], and VDD is supplied to the wiring SALb[k].

[0404] Then, the switching states of transistors Tr31 to Tr34 of the amplifier circuit 133[k,h] are reversed, and the potential (VSS) of the wiring SN is supplied to the wiring BLf[k,h], and the potential (VDD) of the wiring SP is supplied to the wiring BLBf[k,h]. Thus, the charge corresponding to the potential (VSS) representing the data "0" is supplied to the capacitor CA through the wiring BLf[k,h] and stored. By performing the above operation, data can be written to the memory cell 10a.

[0405] [Period T25]

[0406] In the period T25, VNN is supplied to the word line WLa[j], so that the word line WLa[j] is in a non-selected state, thereby retaining the charge written in the memory cell 10a.

[0407] Furthermore, by setting the potential of the wiring CSEL to VSS or VNN, the transistor Tr41 and the transistor Tr42 are turned off.

[0408] Furthermore, even if the transistors Tr41 and Tr42 in the input / output circuit 134[k,h] are turned off after the potential of the wiring SALa[k] is supplied to the wiring BLf[k,h], the potential of the wiring BLf[k,h] and the wiring BLBf[k,h] can be maintained by the amplifier circuit 133[k,h] as long as the amplifier circuit 133[k,h] is in operation. Thus, the timing at which the transistors Tr41 and Tr42 are turned off from the on state can be either before or after the word line WLa[j] is selected.

[0409] By performing the above operation, data can be written to the memory cell 10a. Note that data can also be written to other memory cells in the same manner as the memory cell 10a.

[0410] By setting VNN supplied to the word line WLa[j] to a negative potential, the transistor M1 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0411] [Refresh Mode]

[0412] The refresh mode is an operation mode in which a refresh operation (rewrite operation) is performed at regular intervals to maintain the data written in the memory cell 10a. Fig.31 The timing chart shown illustrates the operation of the refresh mode. As an example, the operation of rewriting the information stored in the memory cell 10a electrically connected to the wiring BLf[k,h] and the word line WLa[j] is described. Note that the refresh operation can be performed based on the same principle as the above-mentioned operation mode.

[0413] [Period T31]

[0414] In period T31, the same operation as in period T11 is performed to initialize the potentials of wiring BLf[k,h] and wiring BLBf[k,h]. Specifically, the potential of wiring PL is set to VDD, and the potential of wiring BLf[k,h] and wiring BLBf[k,h] is set to Vpre.

[0415] [Period T32]

[0416] During period T32, the potential of wiring PL is set to VSS or VNN, so that transistors Tr21 to Tr23 are turned off. In addition, the word line WLa[j] electrically connected to the memory cell 10a to which data is written is selected. Specifically, the potential of word line WLa[j] is set to VPP, so that the transistor M1 of the memory cell 10a is turned on. As a result, in the memory cell 10a, wiring BLf[k,h] and capacitor CA are turned on through transistor M1.

[0417] At this time, when data “1” is stored in the memory cell 10 a , charge is discharged from the capacitor CA to the wiring BLf[k,h], so that the potential of the wiring BLf[k,h] rises from the potential Vpre by ΔV1 .

[0418] [Period T33]

[0419] During the period T33, the potential of the wiring SP is set to VDD, and the potential of the wiring SN is set to VSS, so that the amplifier circuit 133[k,h] is in an operating state. By making the amplifier circuit 133[k,h] in an operating state, the potential of the wiring BLf[k,h] changes from Vpre+ΔV1 to the potential of the wiring SP (VDD). In addition, the potential of the wiring BLBf[k,h] changes from Vpre to the potential of the wiring SN (VSS).

[0420] [Period T34]

[0421] In period T34, VNN is supplied to word line WLa[j], so that word line WLa[j] becomes unselected. Thus, a charge corresponding to the potential (VDD) of wiring BLf[k,h] is supplied to capacitor CA of memory cell 10a through wiring BLf[k,h] and stored.

[0422] By setting VNN supplied to the word line WLa[j] to a negative potential, the transistor M1 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0423] In the refresh mode, since data is not read or written, the input / output circuit 134[k,h] can be kept in the off state. Therefore, the refresh mode can be performed in a shorter time than the read mode and the write mode. Note that the refresh mode of other memory cells can also be performed in the same manner as the memory cell 10a.

[0424] In addition, the transistor M1 is preferably an OS transistor. As described in the above embodiment, the OS transistor is a transistor with very little off-state current. By using an OS transistor as the transistor M1, the number of refresh operations per fixed time can be reduced. Alternatively, the refresh operation may not be performed.

[0425] [HOLD MODE]

[0426] The hold mode is an operation mode for holding data written in the memory cell 10a. A memory cell that is not associated with any of the read mode, write mode, and refresh mode can also be said to operate in the hold mode.

[0427] For example, in the above operation description, while the memory device 100 operates the memory cell 10a electrically connected to the word line WLa[j] in any of the read mode, write mode, or refresh mode, the memory cell 10a electrically connected to the word line WLa[j+5] operates in the hold mode (see Figure 29 to Figure 31 ).

[0428] More specifically, during the period when the memory device 100 operates the memory cell 10a electrically connected to the word line WLa[j] in any of the read mode, write mode, or refresh mode, the potential of the word line WLa[j+5] is VNN. As a result, the transistor M1 included in the memory cell 10a electrically connected to the word line WLa[j+5] remains in the off state. That is, during the operation period of the hold mode, the information stored in the memory cell 10a is retained.

[0429] In order to more reliably turn off the transistor M1, VNN is preferably a negative potential. By setting VNN to a negative potential, it is less likely to cause erroneous writing or reading. By setting VNN to a negative potential, the reliability of the memory device 100 can be improved.

[0430] <Modification>

[0431] then, Fig.32 Show Fig.28 A modification of the circuit configuration shown. Fig.32 Show use Fig. 6A The memory cell shown is an example of a circuit configuration when the memory cell 10a is used. Fig.32 The memory cell 10a shown includes a transistor M1 having a back gate. The back gate of the transistor M1 is electrically connected to the wiring BGLa.

[0432] The wiring BGLa extends in the X direction (row direction) in the cell array 221a, and p wirings BGLa (not shown) are provided. In addition, the cell array 221b includes p wirings BGLb (not shown) extending in the X direction (row direction). In this specification, etc., the wiring BGLa[j] represents the j-th (j is an integer greater than 1 and less than p) wiring BGLa, and the wiring BGLb[j] represents the j-th wiring BGLb. In addition, the wiring BGLa[j] is parallel to the word line WLa[j], and the wiring BGLb[j] is parallel to the word line WLb[j].

[0433] exist Fig.32 In FIG. 1 , the memory cell 10a electrically connected to the word line WLa[j] is electrically connected to the wiring BGLa[j]. The wiring BGLa[j] is electrically connected to the back gate of the transistor M1 included in the memory cell 10a. The circuit structure other than the memory cell 10a is the same as Fig.28 same.

[0434] Next, refer to Figure 33 to Figure 35 illustrate Fig.32 The circuit structure shown in FIG. Fig.28 The circuit structure shown in the figure can also operate in four operating modes (read mode, write mode, refresh mode, and hold mode). In order to reduce repeated explanations, the differences from the above operating modes are mainly explained. Figure 33 to Figure 35 In the figure, the description of the potential changes of the wiring CSEL, the wiring SALa[k], and the wiring SALb[k] is omitted.

[0435] [Read Mode]

[0436] The following reference Fig.33 The timing chart shown explains the operation of reading out information stored in the memory cell 10a electrically connected to the wiring BLf[k,h] and the word line WLa[j].

[0437] [Period T11]

[0438] During period T11, the precharge circuit 132[k,h] is operated so that the potential of the wiring BLf[k,h] and the wiring BLBf[k,h] is initialized. In addition, the potential of the wiring BGLa[j] is set to the potential VBL (also referred to as "VBL"). VBL is a potential lower than VSS. Thus, VBL is a negative potential. The size of VBL also changes with the thickness of the gate insulating layer on the back gate electrode side. When the thickness of the gate insulating layer on the back gate electrode side is thicker than the gate insulating layer on the front gate electrode side, VBL is sometimes greater than VNN. In this embodiment, VBL is -3V.

[0439] In addition, it is also possible to supply only a negative potential to the wiring BGLa[j] to turn off the transistor M1. However, it is preferred to supply a negative potential to both the word line WLa[j] and the wiring BGLa[j]. In particular, when the thickness of the gate insulating layer on the back gate electrode side is thicker than the gate insulating layer on the front gate electrode side, by supplying a negative potential to both the word line WLa[j] and the wiring BGLa[j], the same effect can be achieved with a VBL that is less than the case where only the wiring BGLa[j] is supplied with a negative potential. In other words, the electric field strength applied to the transistor M1 can be reduced. As a result, the reliability of the transistor M1 can be improved. Furthermore, the power consumption of the transistor M1 can be reduced. As a result, the reliability of the storage device 100 can be improved and the power consumption can be reduced.

[0440] [Period T12]

[0441] During period T12, the word line WLa[j] is set to a selected state. Specifically, the potential of the word line WLa[j] is set to a potential VPP, so that the transistor M1 of the memory cell 10a is turned on. In addition, the potential of the wiring BGLa[j] is set to a potential greater than the potential VSS. In this embodiment, the potential of the wiring BGLa[j] is the potential VSS (0V), but it may be higher than the potential VSS. For example, the potential of the wiring BGLa[j] may also be the potential VPP.

[0442] [Period T13, Period T14]

[0443] During the period T13 and the period T14, the information stored in the memory cell 10a is read out.

[0444] [Period T15]

[0445] In period T15, word line WLa[j] is set to a non-selected state. Specifically, the potential of word line WLa[j] is set to VNN. Also, at the timing when the potential of word line WLa[j] becomes VNN, the potential of wiring BGLa[j] is set to VBL.

[0446] Furthermore, during operation in the read mode, the potential of the wiring BGLa[j] may be kept constant. For example, by supplying a negative potential to the wiring BGLa[j], the Vth of the transistor M1 may be shifted to the positive direction. This may reduce the off-state current.

[0447] On the other hand, by increasing the potential of the wiring BGLa[j] as the potential of the word line WLa[j] increases, the operating speed of the transistor M1 can be increased. This can shorten the time required for the read operation. In other words, the operating speed of the memory device 100 can be increased.

[0448] In addition, by raising the potential of both the word line WLa[j] and the wiring BGLa[j], the same operating speed can be achieved with less potential rise than when only one of the potentials is raised. As a result, the electric field strength applied to the transistor M1 can be reduced, thereby improving the reliability of the transistor M1. Furthermore, the power consumption of the transistor M1 can be reduced. In other words, the reliability of the memory device 100 can be improved and the power consumption can be reduced.

[0449] [Write Mode]

[0450] The following reference Fig.34 The timing chart shown explains the operation of writing information into the memory cell 10a electrically connected to the wiring BLf[k,h] and the word line WLa[j].

[0451] [Period T21]

[0452] In the period T21, the precharge circuit 132[k,h] is operated to initialize the potentials of the wirings BLf[k,h] and BLBf[k,h]. In addition, the potential of the wiring BGLa[j] is set to the potential VBL.

[0453] [Period T22]

[0454] In period T22, the word line WLa[j] is selected. Specifically, the potential of the word line WLa[j] is set to the potential VPP, so that the transistor M1 included in the memory cell 10a is turned on. In addition, the potential of the wiring BGLa[j] is set to a potential VSS or higher.

[0455] [Period T23, Period T24]

[0456] During the period T23 and the period T24, information is written into the memory cell 10a.

[0457] [Period T25]

[0458] In period T25, word line WLa[j] is set to a non-selected state. Specifically, the potential of word line WLa[j] is set to VNN. Also, at the timing when the potential of word line WLa[j] becomes VNN, the potential of wiring BGLa[j] is set to VBL.

[0459] In addition, during operation in write mode, the potential of wiring BGLa[j] may also be kept fixed and unchanged. For example, by setting wiring BGLa[j] to a negative potential, the Vth of transistor M1 may be shifted to a positive direction, thereby reducing the cutoff current. On the other hand, by increasing the potential of wiring BGLa[j] along with the potential increase of word line WLa[j], the operating speed of transistor M1 may be increased. Thus, the time required for the write operation may be shortened. In other words, the operating speed of storage device 100 may be increased.

[0460] [Refresh Mode]

[0461] The following reference Fig.35 The timing chart shown explains the operation of rewriting the information stored in the memory cell 10a electrically connected to the wiring BLf[k,h] and the word line WLa[j].

[0462] [Period T31]

[0463] In the period T31, the precharge circuit 132[k,h] is operated to initialize the potentials of the wirings BLf[k,h] and BLBf[k,h]. In addition, the potential of the wiring BGLa[j] is set to the potential VBL.

[0464] [Period T32]

[0465] In period T32, the word line WLa[j] is selected. Specifically, the potential of the word line WLa[j] is set to the potential VPP, so that the transistor M1 included in the memory cell 10a is turned on. In addition, the potential of the wiring BGLa[j] is set to a potential VSS or higher.

[0466] [Period T33]

[0467] During the period T33, the information stored in the memory cell 10a is written again.

[0468] [Period T34]

[0469] In period T34, the word line WLa[j] is set to a non-selected state. Specifically, the potential of the word line WLa[j] is set to VNN. In addition, the potential of the wiring BGLa[j] is set to VBL.

[0470] In addition, during the operation in the refresh mode, the potential of the wiring BGLa[j] can also be kept fixed and unchanged. For example, by setting the wiring BGLa[j] to a negative potential, the Vth of the transistor M1 can be shifted to the positive direction, thereby reducing the cut-off current. On the other hand, by increasing the potential of the wiring BGLa[j] along with the potential increase of the word line WLa[j], the operating speed of the transistor M1 can be increased. As a result, the time required for the refresh operation can be shortened. In other words, the operating speed of the storage device 100 can be increased.

[0471] [HOLD MODE]

[0472] As described above, the hold mode is an operation mode for holding data written in the memory cell 10a. A memory cell that is not associated with any of the read mode, write mode, and refresh mode can also be said to operate in the hold mode.

[0473] For example, in the above operation description, while the memory device 100 operates the memory cell 10a electrically connected to the word line WLa[j] in any of the read mode, write mode, or refresh mode, the memory cell 10a electrically connected to the word line WLa[j+5] operates in the hold mode (see Figure 33 to Figure 35 ).

[0474] More specifically, during the period when the memory device 100 operates the memory cell 10a electrically connected to the word line WLa[j] in any of the read mode, write mode, or refresh mode, the potential of the word line WLa[j+5] is VNN, and the potential of the wiring BGLa[j+5] is VBL. As a result, the transistor M1 included in the memory cell 10a electrically connected to the word line WLa[j+5] remains in the off state. That is, during the operation period of the hold mode, the information stored in the memory cell 10a is retained.

[0475] In addition, it is also possible to supply only the wiring BGLa[j+5] with a negative potential so that the transistor M1 is in a closed state. However, it is preferred to supply a negative potential to both the word line WLa[j+5] and the wiring BGLa[j+5]. In particular, when the thickness of the gate insulating layer on the back gate electrode side is thicker than the gate insulating layer on the front gate electrode side, by supplying a negative potential to both the word line WLa[j+5] and the wiring BGLa[j+5], the same effect can be achieved with a VBL that is less than the case where only the wiring BGLa[j+5] is supplied with a negative potential. In other words, the electric field strength applied to the transistor M1 can be reduced. Thus, the reliability of the transistor M1 can be improved. Furthermore, the power consumption of the transistor M1 can be reduced. Thus, the reliability of the storage device 100 can be improved and the power consumption can be reduced.

[0476] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0477] (Implementation 7)

[0478] In this embodiment, a cross-sectional structure example of the storage device 100 is described with reference to the drawings.

[0479] <Configuration Example of Storage Device>

[0480] Fig.36 A cross section of a portion of the storage device 100 is shown. Fig.36 The memory device 100 shown in the figure has a local sense amplifier array 214, a cell array 221a, and a cell array 221b stacked on a substrate 291. Circuits other than the cell array 221a and the cell array 221b are provided on the substrate 291 in the same manner as the local sense amplifier array 214. Fig.36 2 shows a case where a single crystal semiconductor substrate (for example, a single crystal silicon substrate) is used as the substrate 291. The source, drain, and channel of the transistor in the local sense amplifier array 214 are formed in a portion of the substrate 291. In addition, the cell array 221a and the cell array 221b include thin film transistors (for example, OS transistors).

[0481] [Local sense amplifier array 214]

[0482] exist Fig.36 In FIG. 2 , the local sense amplifier array 214 includes a transistor 233a, a transistor 233b, and a transistor 233c on a substrate 291. Fig.36 , a cross section of the transistor 233a, the transistor 233b, and the transistor 233c in the channel length direction is shown.

[0483] Channels of the transistor 233a, the transistor 233b, and the transistor 233c are formed in a portion of the substrate 291. When the integrated circuit is required to operate at high speed, a single crystal semiconductor substrate is preferably used as the substrate 291.

[0484] The transistor 233a, the transistor 233b, and the transistor 233c are electrically isolated from each other by the element isolation layer 292. The element isolation layer can be formed by a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

[0485] In addition, insulating layers 293, 235, and 237 are provided over the transistors 233a, 233b, and 233c, and an electrode 238 is buried in the insulating layer 237. The electrode 238 is electrically connected to a source or a drain of the transistor 233a through a contact plug 236.

[0486] In addition, insulating layers 239 , 240 , and 241 are provided on the electrode 238 and the insulating layer 237 , and an electrode 242 is buried in the insulating layers 239 , 240 , and 241 . The electrode 242 is electrically connected to the electrode 238 .

[0487] In addition, insulating layers 243 and 244 are provided on the electrode 242 and the insulating layer 241 , and an electrode 245 is buried in the insulating layers 243 and 244 . The electrode 245 is electrically connected to the electrode 242 .

[0488] In addition, insulating layers 246 and 247 are provided on the electrode 245 and the insulating layer 244 , and an electrode 249 is buried in the insulating layers 246 and 247 . The electrode 249 is electrically connected to the electrode 245 .

[0489] In addition, insulating layers 248 and 250 are provided on the electrode 249 and the insulating layer 247 , and an electrode 251 is buried in the insulating layers 248 and 250 . The electrode 251 is electrically connected to the electrode 249 .

[0490] [Cell array 221a]

[0491] The cell array 221a is disposed on the local sense amplifier array 214. Fig.36 In FIG. 2 , the cell array 221 a includes a transistor 368 a , a transistor 368 b , a capacitor 369 a , and a capacitor 369 b . Fig.36 A cross section of the transistor 368a and the transistor 368b in the channel length direction is shown. The transistor 368a and the transistor 368b are transistors having a back gate.

[0492] The semiconductor layers of the transistors 368a and 368b are preferably formed using an oxide semiconductor which is a type of metal oxide. That is, the transistors 368a and 368b are preferably formed using OS transistors.

[0493] The transistor 368a and the transistor 368b are provided on the insulating layer 361 and the insulating layer 362. In addition, the insulating layer 363 and the insulating layer 364 are provided on the insulating layer 362. The back gates of the transistor 368a and the transistor 368b are buried in the insulating layer 363 and the insulating layer 364. The insulating layer 365 and the insulating layer 366 are provided on the insulating layer 364. In addition, the electrode 367 is buried in the insulating layer 361 to the insulating layer 366. The electrode 367 is electrically connected to the electrode 251.

[0494] Furthermore, insulating layers 371 , 372 , and 373 are formed over the transistors 368 a , 368 b , and the capacitors 369 a , 369 b , and an electrode 375 is formed over the insulating layer 373 . The electrode 375 is electrically connected to the electrode 367 through a contact plug 374 .

[0495] In addition, insulating layers 376, 377, 378, and 379 are provided on the electrode 375. In addition, an electrode 380 is buried in the insulating layers 376 to 379. The electrode 380 and the electrode 375 are electrically connected.

[0496] In addition, insulating layers 381 and 382 are provided on the electrode 380 and the insulating layer 379 , and an electrode 383 is buried in the insulating layers 381 and 382 . The electrode 383 is electrically connected to the electrode 380 .

[0497] [Cell array 221b]

[0498] The cell array 221b is disposed on the cell array 221a. Fig.36 In FIG. 2 , the cell array 221 b includes a transistor 538 a , a transistor 538 b , a capacitor 539 a , and a capacitor 539 b . Fig.36 A cross section of the transistor 538a and the transistor 538b in the channel length direction is shown. The transistor 538a and the transistor 538b are transistors having a back gate.

[0499] The semiconductor layers of the transistor 538a and the transistor 538b are preferably formed using an oxide semiconductor which is a type of metal oxide. That is, the transistor 538a and the transistor 538b are preferably formed using an OS transistor.

[0500] The transistor 538a and the transistor 538b are provided on the insulating layer 563 and the insulating layer 532. In addition, the insulating layer 533 and the insulating layer 534 are provided on the insulating layer 532. The back gates of the transistor 538a and the transistor 538b are buried in the insulating layer 533 and the insulating layer 534. The insulating layer 535 and the insulating layer 536 are provided on the insulating layer 534. In addition, the electrode 537 is buried in the insulating layer 563 to the insulating layer 536. The electrode 537 is electrically connected to the electrode 383.

[0501] Furthermore, insulating layers 541, 562, and 543 are formed over the transistors 538a, 538b, the capacitors 539a, and 539b, and an electrode 545 is formed over the insulating layer 543. The electrode 545 is electrically connected to the electrode 537 through a contact plug 564.

[0502] In addition, insulating layers 566, 567, and 548 are provided on the electrode 545. In addition, an electrode 549 is buried in the insulating layers 566 to 548. The electrode 549 is electrically connected to the contact plug 564 through the electrode 545.

[0503] In addition, an insulating layer 550 and an insulating layer 561 are provided over the electrode 549 and the insulating layer 548. An insulating layer 553 is provided over the insulating layer 561.

[0504] <Modification>

[0505] Fig.37 A cross section of a portion of a memory device 100A is shown. The memory device 100A is a modified example of the memory device 100. The memory device 100A includes a local sense amplifier array 214A, a cell array 221a, and a cell array 221b. The local sense amplifier array 214A, the cell array 221a, and the cell array 221b are sequentially stacked on a substrate 291. In the memory device 100A, the substrate 291 uses an insulating substrate (e.g., a glass substrate).

[0506] The local sense amplifier array 214A includes a transistor 268a, a transistor 268b, a capacitor 269a, and a capacitor 269b. The transistors in the local sense amplifier array 214A are thin film transistors (eg, OS transistors). The cell arrays 221a and 221b are manufactured in the same manner as described above.

[0507] By making all transistors in the local sense amplifier array 214A OS transistors, the local sense amplifier array 214A can be made into a unipolar integrated circuit. By making all transistors in the memory device 100A OS transistors, the memory device 100A can be made into a unipolar memory device.

[0508] <Constitution Materials>

[0509] [Substrate]

[0510] Although there are no major restrictions on the materials that can be used for the substrate, the substrate must have at least a sufficiently high heat resistance to withstand the subsequent heat treatment. For example, as a substrate, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, etc., etc. can be used. In addition, an SOI substrate or a substrate having semiconductor elements such as strained transistors or FIN-type transistors arranged on a semiconductor substrate can also be used. In addition, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, etc. that can be used for high electron mobility transistors (HEMT: High Electron Mobility Transistor) can also be used. In other words, the substrate is not only a supporting substrate, but also a substrate on which other devices such as transistors are formed.

[0511] In addition, as a substrate, a glass substrate such as barium borosilicate glass and aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. In addition, a flexible substrate can be used as a substrate. When using a flexible substrate, transistors and capacitors can be directly manufactured on the flexible substrate, and transistors and capacitors can be manufactured on other manufacturing substrates, and then peeled off and transferred to the flexible substrate. In addition, in order to peel off transistors and capacitors from the manufacturing substrate and transfer them to the flexible substrate, it is preferred to set a peeling layer between the manufacturing substrate and the transistors and capacitors.

[0512] As the flexible substrate, for example, metal, alloy, resin or glass, or fibers thereof can be used. The lower the linear expansion coefficient of the flexible substrate used as the substrate, the more deformation caused by the environment is suppressed, so it is preferred. For example, a flexible substrate with a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less or 1×10 -5 / K or less. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable for flexible substrates.

[0513] [Insulation layer]

[0514] The insulating layer is a single layer or a stack of the following materials, and the material is selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In addition, a material mixed with multiple materials of oxide materials, nitride materials, oxynitride materials, and oxynitride materials can also be used.

[0515] In this specification, etc., nitrogen oxide refers to a compound in which the nitrogen content is greater than the oxygen content. In addition, oxynitride refers to a compound in which the oxygen content is greater than the nitrogen content. In addition, for example, the content of each element can be measured using Rutherford backscattering spectroscopy (RBS: Rutherford Backscattering Spectrometry) or the like.

[0516] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, in order to prevent the hydrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the hydrogen concentration in the insulating layer. Specifically, the hydrogen concentration in the insulating layer measured by secondary ion mass spectrometry (SIMS) is 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

[0517] In order to prevent the nitrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer measured by SIMS is 5×10 19 atoms / cm 3 Below, preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0518] The insulating layer preferably has fewer defects in at least the region in contact with the semiconductor layer, and typically the signal observed by the electron spin resonance method (ESR) is preferably smaller. For example, as the above signal, an E' center observed when the g value is 2.001 can be cited. The E' center is caused by a dangling bond of silicon. For example, when a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, a spin density of 3×10 17 spins / cm 3 Below, preferably 5×10 16 spins / cm 3The following silicon oxide layer or silicon oxynitride layer.

[0519] Sometimes, in addition to the above signals, a signal caused by nitrogen dioxide (NO2) is observed. This signal is split into three signals due to the nuclear spin of N, each with a g value of 2.037 or more and 2.039 or less (first signal), a g value of 2.001 or more and 2.003 or less (second signal), and a g value of 1.964 or more and 1.966 or less (third signal).

[0520] For example, it is preferable to use a signal derived from nitrogen dioxide (NO2) with a spin density of 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 insulation layer.

[0521] Nitrogen dioxide (NO2) and other nitrogen oxides (NO x ) forms an energy level in the insulating layer. This energy level is located in the energy gap of the oxide semiconductor layer. x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, sometimes this energy level captures electrons on the insulating layer side. As a result, the captured electrons remain near the interface between the insulating layer and the oxide semiconductor layer, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, by using a film with a low content of oxynitride as the insulating layer, the drift of the threshold voltage of the transistor can be reduced.

[0522] As nitrogen oxides (NO x For example, an insulating layer with a low release amount of ammonia can be a silicon oxynitride layer. The silicon oxynitride layer has a lower release amount of ammonia than nitrogen oxides (NO x ) release, typically 1×10 18 Pieces / cm 3 Above and 5×10 19 Pieces / cm 3 Note that the above-mentioned ammonia release amount is the total amount in the range of the heat treatment temperature in TDS being 50° C. to 650° C. or 50° C. to 550° C.

[0523] Since nitrogen oxides (NO x ) reacts with ammonia and oxygen, so by using an insulating layer that releases a lot of ammonia, nitrogen oxides (NO x ).

[0524] At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer that releases oxygen by heating. Specifically, it is preferable to use an insulating layer whose oxygen release amount converted to oxygen atoms when TDS analysis is performed (wherein the layer surface temperature is heated to 100° C. to 700° C., preferably 100° C. to 500° C.) is 1.0×10 18 atoms / cm 3 Above, 1.0×10 19 atoms / cm 3 Above, or 1.0×10 20 atoms / cm 3 Note that oxygen released by heating is also referred to as "excess oxygen" in this specification and the like.

[0525] The insulating layer containing excess oxygen can also be formed by adding oxygen to the insulating layer. As the oxygen addition treatment, heat treatment in an oxygen atmosphere, plasma treatment, etc. can be used. Alternatively, oxygen addition can be performed by ion implantation, ion doping, plasma immersion ion implantation, etc. Examples of the gas used for the oxygen addition treatment include 16 O2 or 18 Oxygen gas such as O2, nitrous oxide gas, ozone gas, etc. Oxygen-containing gas. In this specification, the process of adding oxygen is also referred to as "oxygen doping process." The oxygen doping process can also be performed while heating the substrate.

[0526] As the insulating layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. can be used. In addition to the above-mentioned organic materials, low-k materials, siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, the insulating layer can also be formed by stacking a plurality of insulating layers formed of these materials.

[0527] Siloxane resins are equivalent to resins containing Si-O-Si bonds formed using siloxane materials as starting materials. Siloxane resins may also use organic groups (such as alkyl groups or aryl groups) or fluorine groups as substituents. In addition, the organic groups may also include fluorine groups.

[0528] There is no particular limitation on the method for forming the insulating layer. Note that a baking step may be required depending on the material used for the insulating layer. In this case, the baking step of the insulating layer can be combined with other heat treatment steps to efficiently manufacture the transistor.

[0529] [electrode]

[0530] As the conductive material for forming the electrode, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc. can be used. In addition, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus, a silicide such as nickel silicide, etc. can also be used.

[0531] In addition, a conductive material containing the above-mentioned metal element and oxygen can also be used. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, indium tin oxide (ITO: Indium Tin Oxide), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium gallium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used.

[0532] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked for use. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. In addition, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. In addition, a laminated structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen. In addition, a laminated structure may be formed by combining a conductive material containing nitrogen and a conductive material containing oxygen.

[0533] In addition, when an oxide semiconductor is used as the semiconductor layer and a stacked structure of a material containing the above-mentioned metal element and a conductive material containing oxygen is used as the gate electrode, it is preferable to provide a conductive material containing oxygen on one side of the semiconductor layer. By providing a conductive material containing oxygen on one side of the semiconductor layer, oxygen released from the conductive material can be easily supplied to the semiconductor layer.

[0534] In addition, as an electrode, for example, a highly embedded conductive material such as tungsten or polysilicon can be used. In addition, a combination of a highly embedded conductive material and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer can also be used. Sometimes the electrode is called a "contact plug".

[0535] In particular, it is preferable to use a conductive material that does not easily allow impurities to pass through as an electrode in contact with the gate insulating layer. As an example of a conductive material that does not easily allow impurities to pass through, tantalum nitride can be mentioned.

[0536] By using an insulating material that is not easily permeable to impurities as an insulating layer and a conductive material that is not easily permeable to impurities as an electrode, it is possible to further suppress the diffusion of impurities into the transistor. As a result, the reliability of the transistor can be further improved. In other words, the reliability of the storage device can be further improved.

[0537] [Semiconductor layer]

[0538] As the semiconductor layer, one or more of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor can be used. As the semiconductor material, for example, silicon or germanium can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, or organic semiconductors can also be used.

[0539] When an organic semiconductor is used as the semiconductor layer, a low molecular weight organic material having an aromatic ring or a π-electron conjugated conductive polymer can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene, etc. can be used.

[0540] The semiconductor layer may also adopt a stacked structure. When the semiconductor layer adopts a stacked structure, semiconductors with different crystal states or different semiconductor materials may be used.

[0541] In addition, since the band gap of oxide semiconductors is above 2 eV, when oxide semiconductors are used as semiconductor layers, transistors with extremely small off-state currents can be realized. Specifically, the off-state current per 1 μm channel width can be less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24 A. That is, the on-off ratio can be more than 20 digits. In addition, in a transistor using an oxide semiconductor as a semiconductor layer, the insulation withstand voltage between the source and the drain is high. Thus, a transistor with good reliability can be provided. In addition, a transistor with a large output voltage and a high withstand voltage can be provided. In addition, a storage device with good reliability can be provided. In addition, a storage device with a large output voltage and a high withstand voltage can be provided.

[0542] In this specification and the like, a transistor using crystalline silicon in a semiconductor layer forming a channel is referred to as a "crystalline Si transistor".

[0543] Compared with OS transistors, crystalline Si transistors can easily obtain higher mobility. On the other hand, it is difficult for crystalline Si transistors to achieve an extremely small off-state current like OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to the purpose or use. For example, a combination of OS transistors and crystalline Si transistors, etc., can be used according to the purpose or use.

[0544] When an oxide semiconductor layer is used as a semiconductor layer, it is preferred to form the oxide semiconductor layer by a sputtering method. When the oxide semiconductor layer is formed by a sputtering method, the density of the oxide semiconductor layer can be increased, so it is preferred. In the case of forming the oxide semiconductor layer by a sputtering method, as a sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen can be used. In addition, the sputtering gas needs to be highly purified. For example, as an oxygen gas or a rare gas used as a sputtering gas, a high-purity gas with a dew point of less than -60°C, preferably less than -100°C, is used. By using a high-purity sputtering gas to form a thin film, it is possible to prevent moisture and the like from mixing into the oxide semiconductor layer as much as possible.

[0545] When the oxide semiconductor layer is formed by sputtering, it is preferable to remove as much water as possible from the film forming chamber of the sputtering device. For example, it is preferable to use an adsorption vacuum pump such as a cryopump to evacuate the film forming chamber to a high vacuum (to 5×10 -7 Pa to 1×10 -4 In particular, when the sputtering device is on standby, the partial pressure of the gas molecules corresponding to H2O (the gas molecules corresponding to m / z=18) in the film forming processing chamber is preferably 1×10 -4 Pa or less, more preferably 5×10 -5 Below Pa.

[0546] [Metal oxides]

[0547] The oxide semiconductor as one of the metal oxides preferably contains at least indium or zinc. Indium and zinc are particularly preferably contained. In addition, it is preferred that aluminum, gallium, yttrium or tin are contained in addition to these. In addition, it may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0548] Here, the case where the oxide semiconductor includes indium, element M, and zinc is considered. Note that element M is aluminum, gallium, yttrium, or tin. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium in addition to the above elements. Note that as element M, a plurality of the above elements may be combined.

[0549] In addition, in this specification and the like, a metal oxide containing nitrogen may be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0550] [Composition of Metal Oxides]

[0551] Hereinafter, the configuration of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described.

[0552] In this specification, etc., it may be described as CAAC (c-axis aligned crystal) or CAC (Cloud-Aligned Composite). Note that CAAC is an example of a crystal structure, and CAC is an example of a function or a material configuration.

[0553] CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in another part of the material, and has a semiconductor function as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC-metal oxide can have a switching function (a function of controlling on / off). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0554] In addition, CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated at a nanoparticle level. In addition, the conductive region and the insulating region are sometimes unevenly distributed in the material. In addition, sometimes the conductive region whose edge is fuzzy and connected in a cloud shape is observed.

[0555] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0556] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, carriers mainly flow through the component with a narrow gap. In addition, the component with a narrow gap interacts with the component with a narrow gap through a complementary effect with the component with a wide gap, so that carriers flow through the component with a wide gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on-state of the transistor.

[0557] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).

[0558] [Structure of Metal Oxide]

[0559] Oxide semiconductors (metal oxides) are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0560] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has distortion. Note that distortion refers to the part where the lattice arrangement direction changes between the region where the multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0561] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, in the distortion, there is sometimes a lattice arrangement such as a pentagon or a heptagon. In addition, in CAAC-OS, no clear grain boundary is observed even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bonding distance between atoms caused by the substitution of metal elements.

[0562] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. In the case where element M in the (M, Zn) layer is replaced by indium, the layer can also be represented as an (In, M, Zn) layer. In addition, in the case where indium in the In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0563] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. In addition, the crystallinity of metal oxides is sometimes reduced due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is a metal oxide with few impurities or defects (oxygen vacancies, etc.). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

[0564] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0565] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductor. a-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0566] Oxide semiconductors (metal oxides) have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0567] [Transistor with metal oxide]

[0568] Next, a case where the above-mentioned metal oxide is used for a channel formation region of a transistor will be described.

[0569] By using the above-mentioned metal oxide in the channel formation region of the transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0570] In addition, metal oxides with low carrier density are preferably used for transistors. In the case of reducing the carrier density of a metal oxide film, the impurity concentration in the metal oxide film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in the metal oxide can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and is 1×10 -9 / cm 3 above.

[0571] Furthermore, high purity intrinsic or substantially high purity intrinsic metal oxide films have a lower defect state density and thus sometimes have a lower trap state density.

[0572] Furthermore, it takes a long time for the charges trapped in the trap states of the metal oxide to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region in a metal oxide with a high trap state density may be unstable.

[0573] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0574] [Impurities]

[0575] Here, the influence of each impurity in the metal oxide is described.

[0576] When the metal oxide contains silicon or carbon, which is one of the elements of Group 14, a defect level is formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide or near the interface of the metal oxide (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0577] In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level is sometimes formed to form a carrier. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0578] When the metal oxide contains nitrogen, electrons as carriers are easily generated, which increases the carrier density and turns into n-type. As a result, a transistor using a metal oxide containing nitrogen in a channel formation region tends to have a normally-on characteristic. Therefore, in the metal oxide, it is preferable to reduce the nitrogen in the channel formation region as much as possible. For example, the nitrogen concentration in the metal oxide measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0579] Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to generate water, thus sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, a transistor using a metal oxide containing hydrogen as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferable to reduce the hydrogen in the metal oxide as much as possible. Specifically, in the metal oxide, the hydrogen concentration measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0580] By using a metal oxide whose impurity concentration is sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0581] <Film Formation Method>

[0582] The insulating material, the conductive material for forming the electrode or the semiconductor material for forming the semiconductor layer can be formed by sputtering, spin coating, chemical vapor deposition (CVD: Chemical Vapor Deposition) method (including thermal CVD method, metal organic CVD (MOCVD: Metal Organic Chemical Vapor Deposition) method, plasma enhanced CVD (PECVD: Plasma Enhanced CVD) method, high-density plasma CVD (HDPCVD: High density plasmaCVD) method, reduced pressure CVD (LPCVD: low pressure CVD) method, atmospheric pressure CVD (APCVD: atmospheric pressure CVD) method, etc.), atomic layer deposition (ALD: Atomic Layer Deposition) method or molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method, dip coating, spraying, droplet jetting method (inkjet method, etc.), printing method (screen printing, offset printing, etc.).

[0583] The plasma CVD method can obtain a high-quality film at a relatively low temperature. In the case of a film forming method that does not use plasma, such as the MOCVD method, the ALD method, or the thermal CVD method, damage is not easily generated on the formed surface. For example, the wiring, electrodes, elements (transistors, capacitors, etc.) included in the storage device sometimes generate charge accumulation (charge up) due to receiving charges from plasma. At this time, the wiring, electrodes, elements, etc. included in the storage device are sometimes damaged due to the accumulated charges. On the other hand, in the case of a film forming method that does not use plasma, since such plasma damage does not occur, the yield of the storage device can be improved. In addition, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.

[0584] Unlike the film-forming method of depositing particles released from a target material, the CVD method and the ALD method are film-forming methods that form a film due to a reaction on the surface of the object to be processed. Therefore, the film formed by the CVD method and the ALD method is not easily affected by the shape of the object to be processed, and has good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the film-forming speed of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other film-forming methods such as the CVD method with a fast film-forming speed.

[0585] The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow ratio of the source gases. For example, when the CVD method and the ALD method are used, a film of any composition can be formed by adjusting the flow ratio of the source gases. In addition, for example, when the CVD method and the ALD method are used, a film whose composition continuously changes can be formed by changing the flow ratio of the source gases while forming the film. When the film is formed while changing the flow ratio of the source gases, the time required for conveying and adjusting the pressure can be omitted, so the time required for film formation can be shortened compared to the case where the film is formed using multiple film forming chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0586] Note that when the film is formed by the ALD method, it is preferable to use a gas that does not contain chlorine as a material gas.

[0587] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0588] (Implementation 8)

[0589] In this embodiment, a structural example of a transistor which can be applied to the memory device or the like described in the above embodiment will be described.

[0590] <Transistor Structure Example 1>

[0591] Reference Fig.38A , Fig.38B and Fig.38C A structural example of the transistor 510A is described. Fig.38A is a top view of transistor 510A. Fig.38B is Fig.38A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.38C is Fig.38A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.38A In the top view, for the sake of clarity, part of the components are omitted and shown.

[0592] exist Fig.38A , Fig.38B and Fig.38C 5 shows a transistor 510A, an insulating layer 511 used as an interlayer film, an insulating layer 512, an insulating layer 514, an insulating layer 516, an insulating layer 580, an insulating layer 582, and an insulating layer 584. In addition, a conductive layer 546 (a conductive layer 546a and a conductive layer 546b) which is electrically connected to the transistor 510A and used as a contact plug, and a conductive layer 503 used as a wiring are shown.

[0593] The transistor 510A includes: a conductive layer 560 (conductive layer 560a and conductive layer 560b) used as a first gate electrode; a conductive layer 505 (conductive layer 505a and conductive layer 505b) used as a second gate electrode; an insulating layer 550 used as a first gate insulating layer; insulating layers 521, 522, and 524 used as second gate insulating layers; an oxide 530 (oxide 530a, oxide 530b, and oxide 530c) including an area forming a channel; a conductive layer 542a used as one of a source and a drain; a conductive layer 542b used as the other of a source and a drain; and an insulating layer 574.

[0594] In addition, FIG. 38A to FIG. 38C In the transistor 510A shown in the figure, an oxide 530c, an insulating layer 550, and a conductive layer 560 are provided in an opening provided in an insulating layer 580 via an insulating layer 574. In addition, the oxide 530c, the insulating layer 550, and the conductive layer 560 are provided between the conductive layer 542a and the conductive layer 542b.

[0595] The insulating layer 511 and the insulating layer 512 serve as an interlayer film.

[0596] As the interlayer film, a single layer or a stack of insulating layers such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide can be added to these insulating layers. In addition, these insulating layers can also be nitrided. Silicon oxide, silicon oxynitride or silicon nitride can also be stacked on the above-mentioned insulating layer.

[0597] For example, the insulating layer 511 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, as the insulating layer 511, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In addition, for example, it is preferable to use aluminum oxide or silicon nitride as the insulating layer 511. By adopting this structure, it is possible to suppress impurities such as hydrogen and water from diffusing from the side closer to the substrate than the insulating layer 511 to the side of the transistor 510A.

[0598] For example, the dielectric constant of the insulating layer 512 is preferably lower than that of the insulating layer 511. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0599] The conductive layer 503 is formed in a manner embedded in the insulating layer 512. Here, the height of the top surface of the conductive layer 503 and the height of the top surface of the insulating layer 512 may be substantially the same. The conductive layer 503 has a single-layer structure, but the present invention is not limited thereto. For example, the conductive layer 503 may also have a multilayer film structure of more than two layers. As the conductive layer 503, a highly conductive conductive material having tungsten, copper or aluminum as a main component is preferably used.

[0600] In transistor 510A, conductive layer 560 is sometimes used as a first gate (also referred to as a top gate) electrode. Conductive layer 505 is sometimes used as a second gate (also referred to as a bottom gate) electrode. In this case, by independently changing the potential supplied to conductive layer 505 without interlocking it with the potential supplied to conductive layer 560, the threshold voltage of transistor 510A can be controlled. In particular, by supplying a negative potential to conductive layer 505, the threshold voltage of transistor 510A can be made greater than 0V and the off-state current can be reduced. Therefore, compared to when a negative potential is not applied to conductive layer 505, when a negative potential is applied to conductive layer 505, the drain current when the potential supplied to conductive layer 560 is 0V can be reduced.

[0601] In addition, for example, by overlapping the conductive layer 505 with the conductive layer 560 , when a potential is supplied to the conductive layer 560 and the conductive layer 505 , the electric field generated from the conductive layer 560 and the electric field generated from the conductive layer 505 are connected, so that the channel formation region formed in the oxide 530 can be covered.

[0602] That is, the channel formation region can be electrically surrounded by the electric field of the conductive layer 560 used as the first gate electrode and the electric field of the conductive layer 505 used as the second gate electrode. In this specification, the structure of the transistor in which the channel formation region is electrically surrounded by the electric field of the first gate electrode and the electric field of the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0603] The insulating layer 514 and the insulating layer 516 are used as interlayer films, similarly to the insulating layer 511 and the insulating layer 512. For example, the insulating layer 514 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. By adopting this structure, impurities such as hydrogen and water can be suppressed from diffusing from the side closer to the substrate than the insulating layer 514 to the transistor 510A side. For example, the dielectric constant of the insulating layer 516 is preferably lower than that of the insulating layer 514. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0604] In the conductive layer 505 used as the second gate, a conductive layer 505a is formed in contact with the inner wall of the opening of the insulating layer 514 and the insulating layer 516, and a conductive layer 505b is formed inside. Here, the height of the top surface of the conductive layer 505a and the conductive layer 505b may be substantially the same as the height of the top surface of the insulating layer 516. In addition, in the transistor 510A, the conductive layer 505a and the conductive layer 505b are stacked, but the present invention is not limited to this. For example, the conductive layer 505 may have a single-layer structure or a stacked structure of three or more layers.

[0605] Here, as the conductive layer 505a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In this specification, "the function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0606] For example, by providing the conductive layer 505a with a function of suppressing diffusion of oxygen, a decrease in conductivity due to oxidation of the conductive layer 505b can be suppressed.

[0607] In addition, when the conductive layer 505 also has a wiring function, it is preferable to use a highly conductive conductive material with tungsten, copper or aluminum as a main component as the conductive layer 505b. In this case, it is not necessary to provide the conductive layer 503. In the drawings, the conductive layer 505b has a single-layer structure, but it may also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials may be used.

[0608] The insulating layer 521 , the insulating layer 522 , and the insulating layer 524 function as a second gate insulating layer.

[0609] The insulating layer 522 preferably has a barrier property. When the insulating layer 522 has a barrier property, the insulating layer 522 serves as a layer for suppressing impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A.

[0610] As the insulating layer 522, for example, a single layer or a stack of insulating layers of so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) are preferably used. When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin filming of the gate insulating layer. By using a high-k material as an insulating layer used as a gate insulating layer, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0611] For example, the insulating layer 521 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulating layer of a high-k material with silicon oxide or silicon oxynitride, an insulating layer 521 having a stacked structure with thermal stability and a high relative dielectric constant can be formed.

[0612] Note that FIG. 38A to FIG. 38C In the embodiment, the second gate insulating layer has a three-layer stacked structure, but may also have a single-layer structure or a stacked structure of two or more layers. In this case, the stacked structure is not limited to being made of the same material, but may also be a stacked structure formed of different materials.

[0613] The oxide 530 including the region used as the channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. When the oxide 530a is provided below the oxide 530b, impurities can be prevented from diffusing from the structure formed below the oxide 530a to the oxide 530b. When the oxide 530c is provided above the oxide 530b, impurities can be prevented from diffusing from the structure formed above the oxide 530c to the oxide 530b. As the oxide 530, an oxide semiconductor of one of the metal oxides described in the above embodiment can be used.

[0614] The oxide 530c is preferably provided in the opening provided in the insulating layer 580 via the insulating layer 574. When the insulating layer 574 has a barrier property, diffusion of impurities from the insulating layer 580 into the oxide 530 can be suppressed.

[0615] One of the conductive layers 542 serves as a source electrode, and the other serves as a drain electrode.

[0616] Conductive layer 542a, conductive layer 542b can be made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum or tungsten, or an alloy containing these elements as main components. In particular, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen and oxygen and have high oxidation resistance.

[0617] In addition, although FIG. 38A to FIG. 38C Although a single-layer structure is shown in the figure, a stacked structure of two or more layers may be adopted. For example, a tantalum nitride film and a tungsten film are preferably stacked. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure of stacking an aluminum film on a tungsten film, a two-layer structure of stacking a copper film on a copper-magnesium-aluminum alloy film, a two-layer structure of stacking a copper film on a titanium film, and a two-layer structure of stacking a copper film on a tungsten film may also be adopted.

[0618] In addition, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, or an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0619] Alternatively, a barrier layer may be provided over the conductive layer 542. The barrier layer is preferably made of a substance that has a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductive layer 542 can be suppressed when the insulating layer 574 is formed.

[0620] The barrier layer may be made of, for example, a metal oxide. In particular, it is preferable to use an insulating film having barrier properties to oxygen or hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide. Alternatively, silicon nitride formed by CVD may be used.

[0621] By including the barrier layer, the range of choices for the material of the conductive layer 542 can be expanded. For example, a material with low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used for the conductive layer 542. In addition, for example, a conductor that is easy to deposit or process can be used.

[0622] The insulating layer 550 is used as a first gate insulating layer. The insulating layer 550 is preferably provided in the opening provided in the insulating layer 580 via the oxide 530 c and the insulating layer 574 .

[0623] When miniaturization and high integration of transistors are performed, leakage current and other problems may occur due to the thin film of the gate insulating layer. In this case, the insulating layer 550 may also have a laminated structure, similar to the second gate insulating layer. By making the insulating layer used as the gate insulating layer have a laminated structure of a high-k material and a thermally stable material, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a laminated structure with thermal stability and a high relative dielectric constant can be achieved.

[0624] The conductive layer 560 used as the first gate electrode includes a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. As with the conductive layer 505a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used as the conductive layer 560a. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0625] When the conductive layer 560a has a function of suppressing diffusion of oxygen, the selectivity of the material of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, and a decrease in conductivity can be prevented.

[0626] As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, as the conductive layer 560a, an oxide semiconductor that can be used for the oxide 530 can be used. In this case, by forming the conductive layer 560b by sputtering, the resistivity of the conductive layer 560a can be reduced to make it a conductor. The conductor can be called an OC (Oxide Conductor) electrode.

[0627] As the conductive layer 560b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. Since the conductive layer 560 is used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductive layer 560b can also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials can be used.

[0628] An insulating layer 574 is disposed between the insulating layer 580 and the transistor 510A. An insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used as the insulating layer 574. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0629] By including the insulating layer 574, impurities such as water and hydrogen contained in the insulating layer 580 can be prevented from diffusing into the oxide 530b through the oxide 530c and the insulating layer 550. In addition, oxidation of the conductive layer 560 by excess oxygen contained in the insulating layer 580 can be prevented.

[0630] The insulating layer 580 , the insulating layer 582 , and the insulating layer 584 serve as an interlayer film.

[0631] Similar to the insulating layer 514, the insulating layer 582 is preferably used as a block insulating film for preventing impurities such as water and hydrogen from entering the transistor 510A from the outside.

[0632] By setting the resistivity to 1×10 10 Ωcm or more and 1×10 15 An insulating material with a resistivity of 1×10 14 Ωcm or less, preferably 1×10 13 In addition, this is not limited to the insulating layer 582, and other insulating layers may also use silicon nitride with a resistivity of 1×10 10 Ωcm or more and 1×10 15 For example, as the insulating layer 584, the insulating layer 580, the insulating layer 524, and / or the insulating layer 516, an insulating material with a resistivity of 1×10 14 Ωcm or less, preferably 1×10 13 Silicon nitride below Ωcm.

[0633] As with the insulating layer 516, the insulating layer 580 and the insulating layer 584 preferably have a lower dielectric constant than the insulating layer 582. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0634] In addition, the transistor 510A may be electrically connected to other structures through plugs or wiring such as the conductive layer 546 embedded in the insulating layer 580 , the insulating layer 582 , and the insulating layer 584 .

[0635] In addition, as with the conductive layer 505, as the material of the conductive layer 546, a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. For example, a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity is preferably used. Alternatively, a low resistance conductive material such as aluminum or copper is preferably used. By using a low resistance conductive material, wiring resistance can be reduced.

[0636] For example, by using a stacked-layer structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity, as the conductive layer 546, diffusion of impurities from the outside can be suppressed while maintaining the conductivity of the wiring.

[0637] By having the above structure, a semiconductor device having a transistor including an oxide semiconductor with a large on-state current can be provided. Alternatively, a semiconductor device having a transistor including an oxide semiconductor with a small off-state current can be provided. Alternatively, a semiconductor device having improved reliability while suppressing variations in electrical characteristics and having stable electrical characteristics can be provided.

[0638] Note that the conductive layer 505 which functions as a back gate electrode and the conductive layer 503 which functions as a wiring can be omitted as necessary. FIG. 45A to FIG. 45C The transistor 510Aa shown has the components of the transistor 510A except for the conductive layer 505 and the conductive layer 503 .

[0639] Fig.45A is a top view of transistor 510Aa. Fig.45B is Fig.45A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.45C is Fig.45A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.45A In the top view, part of the components are omitted for clarity.

[0640] <Transistor Structure Example 2>

[0641] Reference Fig.39A , Fig.39B and Fig.39C A structural example of the transistor 510B is described. Fig.39A is a top view of transistor 510B. Fig.39B is Fig.39A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.39C is Fig.39A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.39A In the top view, part of the components are omitted for clarity.

[0642] The transistor 510B is a modified example of the above-described transistor. Therefore, in order to avoid duplication of descriptions, the differences from the above-described transistor will be mainly described.

[0643] exist FIG. 39A to FIG. 39CIn the embodiment, a portion of the surface of the exposed oxide 530b includes regions 531a and 531b without providing the conductive layer 542 (conductive layer 542a and conductive layer 542b). One of the regions 531a and 531b is used as a source region, and the other is used as a drain region. In addition, an insulating layer 573 is included between the oxide 530b and the insulating layer 574.

[0644] FIG. 39A to FIG. 39C The region 531 (region 531a and region 531b) shown is a region in which the above-mentioned elements are added to the oxide 530b. The region 531 can be formed by using a dummy gate, for example.

[0645] Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask to add an element that makes the oxide 530b low in resistance. That is, the element is added to the region of the oxide 530 that does not overlap with the dummy gate, thereby forming a region 531. As a method for adding the element, an ion implantation method in which the ionized source gas is mass-separated and added; an ion doping method in which the ionized source gas is not mass-separated and added; and a plasma immersion ion implantation method, etc. can be used.

[0646] In addition, as an element that reduces the resistance of the oxide 530, boron or phosphorus is typical. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. can also be used. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. The concentration of the element can be measured by secondary ion mass spectrometry (SIMS) or the like.

[0647] In particular, boron and phosphorus are preferred because they can be produced using equipment in amorphous silicon or low-temperature polysilicon production lines. Existing equipment can be used, thereby reducing equipment investment.

[0648] Next, an insulating film to be an insulating layer 573 and an insulating film to be an insulating layer 574 may be formed over the oxide 530b and the dummy gate. By stacking the insulating film to be the insulating layer 573 and the insulating layer 574, a region where the region 531 overlaps with the oxide 530c and the insulating layer 550 can be provided.

[0649] Specifically, an insulating film that becomes the insulating layer 580 is provided on the insulating film that becomes the insulating layer 574, and then the insulating film that becomes the insulating layer 580 is subjected to a CMP (Chemical Mechanical Polishing) process to remove a portion of the insulating film that becomes the insulating layer 580, thereby exposing the dummy gate. Next, when removing the dummy gate, it is preferable to also remove a portion of the insulating layer 573 that is in contact with the dummy gate. As a result, the insulating layer 574 and the insulating layer 573 are exposed on the side of the opening provided in the insulating layer 580, and a portion of the region 531 provided in the oxide 530b is exposed on the bottom surface of the opening. Next, an oxide film that becomes the oxide 530c, an insulating film that becomes the insulating layer 550, and a conductive film that becomes the conductive layer 560 are sequentially formed in the opening, and then a portion of the oxide film that becomes the oxide 530c, the insulating film that becomes the insulating layer 550, and the conductive film that becomes the conductive layer 560 are removed by CMP treatment or the like until the insulating layer 580 is exposed, thereby forming FIG. 39A to FIG. 39C The transistor shown.

[0650] Note that the insulating layer 573 and the insulating layer 574 are not necessarily provided and may be appropriately designed depending on required transistor characteristics.

[0651] FIG. 39A to FIG. 39C The transistor shown can utilize existing equipment and does not include the conductive layer 542 , thereby reducing costs.

[0652] Note that the conductive layer 505 which functions as a back gate electrode and the conductive layer 503 which functions as a wiring can be omitted as necessary. FIG. 46A to FIG. 46C The transistor 510Ba shown has the components of the transistor 510B except for the conductive layer 505 and the conductive layer 503 .

[0653] Fig.46A is a top view of the transistor 510Ba. Fig.46B is Fig.46A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.46C is Fig.46A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.46A In the top view, part of the components are omitted for clarity.

[0654] <Transistor structure example 3>

[0655] Reference Fig.40A , Fig.40B and Fig.40C A structural example of the transistor 510C is described. Fig.40A is a top view of transistor 510C. Fig.40B is Fig.40AA cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.40C is Fig.40A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.40A In the top view, part of the components are omitted for clarity.

[0656] The transistor 510C is a modified example of the above-described transistor, and thus, in order to avoid duplication of descriptions, the description will be mainly focused on the differences from the transistor 510A.

[0657] The transistor 510C includes a region where the conductive layer 542 (the conductive layer 542a and the conductive layer 542b) overlaps with the oxide 530c, the insulating layer 550, the oxide 551, and the conductive layer 560. With this structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

[0658] The conductive layer 560 used as the first gate electrode includes a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. As with the conductive layer 505a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used as the conductive layer 560a. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0659] When the conductive layer 560a has a function of suppressing diffusion of oxygen, the selectivity of the material of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, and a decrease in conductivity can be prevented.

[0660] In addition, the material used for the conductive layer 560a can also be determined according to the work function to adjust the Vth of the transistor. For example, the conductive layer 560a can be formed using titanium nitride and the conductive layer 560b can be formed using tungsten. The conductive layer 560a and the conductive layer 560b can be formed using a known film forming method such as a sputtering method, a CVD method, or an AFM method. In addition, the film forming temperature when the titanium nitride film is formed using the CVD method is preferably 380° C. to 500° C., and more preferably 400° C. to 450° C.

[0661] The oxide 551 can be formed using the same material as other insulating layers. In addition, as the oxide 551, a metal oxide such as In-M-Zn oxide containing excess oxygen (the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium) can be used. For example, as the oxide 551, In-Ga-Zn oxide can be formed using a sputtering method. Specifically, for example, In-Ga-Zn oxide is formed using a target having an atomic ratio of In:Ga:Zn=1:3:4 and a sputtering gas containing oxygen. When the oxide 551 is formed using a sputtering method, the flow ratio of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and further preferably 100%.

[0662] By using a gas containing oxygen as the sputtering gas, oxygen can be supplied not only to the oxide 551 but also to the insulating layer 550 on which the oxide 551 is formed. In addition, by increasing the flow rate ratio of oxygen contained in the sputtering gas, the amount of oxygen supplied to the insulating layer 550 can be increased.

[0663] In addition, since the oxide 551 is provided over the insulating layer 550, excess oxygen contained in the insulating layer 550 is less likely to diffuse into the conductive layer 560. Thus, reliability of the transistor can be improved. In addition, the oxide 551 may be omitted depending on the purpose or the like.

[0664] In addition, it is preferable to provide an insulating layer 574 so as to cover the top surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the oxide 530c. As the insulating layer 574, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0665] By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. In addition, by including the insulating layer 574, diffusion of impurities such as water and hydrogen contained in the insulating layer 580 into the transistor 510C can be suppressed.

[0666] Alternatively, an insulating layer 576 (insulating layer 576a and insulating layer 576b) having a barrier property may be provided between the conductive layer 546 and the insulating layer 580. Providing the insulating layer 576 can prevent oxidation of the conductive layer 546 due to reaction of oxygen in the insulating layer 580 with the conductive layer 546.

[0667] Furthermore, by providing the insulating layer 576 having a barrier property, the range of choices for the material of the conductor used for the plug or the wiring can be expanded. For example, as the conductive layer 546, a metal material having a property of absorbing oxygen and having high conductivity can be used.

[0668] Note that the conductive layer 505 which functions as a back gate electrode and the conductive layer 503 which functions as a wiring can be omitted as necessary. FIG. 47A to FIG. 47C The transistor 510Ca shown has the components of the transistor 510C except for the conductive layer 505 and the conductive layer 503 .

[0669] Fig.47A is a top view of transistor 510Ca. Fig.47B is Fig.47A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.47C is Fig.47A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.47A In the top view, part of the components are omitted for clarity.

[0670] <Transistor Structure Example 4>

[0671] Reference Fig.41A , Fig.41B and Fig.41C A structural example of the transistor 510D is described. Fig.41A is a top view of transistor 510D. Fig.41B is Fig.41A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.41C is Fig.41A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.41A In the top view, part of the components are omitted for clarity.

[0672] The transistor 510D is a modified example of the above-described transistor, and thus, in order to avoid duplication of descriptions, the description will be mainly focused on the differences from the transistor 510A.

[0673] FIG. 41A to FIG. 41C The transistor 510D shown has a conductive layer 547a disposed between the conductive layer 542a and the oxide 530b, and a conductive layer 547b disposed between the conductive layer 542b and the oxide 530b. Here, the conductive layer 542a (conductive layer 542b) has a region extending beyond the top surface of the conductive layer 547a (conductive layer 547b) and the side surface on one side of the conductive layer 560 and in contact with the top surface of the oxide 530b. Here, as the conductive layer 547, a conductor that can be used for the conductive layer 542 can be used. In addition, the thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 542.

[0674] because FIG. 41A to FIG. 41C The transistor 510D shown has the above structure, and compared with the transistor 510A, the conductive layer 542 can be closer to the conductive layer 560. Alternatively, the end of the conductive layer 542a and the end of the conductive layer 542b can overlap with the conductive layer 560. Thus, the substantial channel length of the transistor 510D can be reduced, and the on-state current and frequency characteristics can be improved.

[0675] In addition, the conductive layer 547a (conductive layer 547b) preferably overlaps the conductive layer 542a (conductive layer 542b). With this structure, when etching is performed to form an opening to fill the conductive layer 546a (conductive layer 546b), the conductive layer 547a (conductive layer 547b) is used as an etching stopper to prevent overetching of the oxide 530b.

[0676] In addition, FIG. 41A to FIG. 41C In the transistor 510D shown in the figure, an insulating layer 565 may be provided in contact with the insulating layer 544. The insulating layer 544 is preferably used as a blocking insulating film for suppressing impurities such as water or hydrogen or excess oxygen from entering the transistor 510D from the insulating layer 580 side. As the insulating layer 565, an insulating layer that can be used for the insulating layer 544 can be used. In addition, for example, the insulating layer 544 can be formed using a nitride insulating material such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon oxynitride.

[0677] In addition, FIG. 41A to FIG. 41C The transistor 510D shown in FIG. FIG. 38A to FIG. 38C Unlike the transistor 510A shown, the conductive layer 505 may also have a single-layer structure. In this case, an insulating film to become the insulating layer 516 may be formed on the conductive layer 505 that has been formed into a pattern, and the top of the insulating film may be removed by using a CMP method or the like until the top surface of the conductive layer 505 is exposed. Here, it is preferred to improve the flatness of the top surface of the conductive layer 505. For example, the average surface roughness (Ra) of the top surface of the conductive layer 505 may be less than 1 nm, preferably less than 0.5 nm, and more preferably less than 0.3 nm. Thus, the flatness of the insulating layer formed on the conductive layer 505 can be improved, and the crystallinity of the oxide 530b and the oxide 530c can be improved.

[0678] Furthermore, the conductive layer 505 may be omitted as necessary. FIG. 48A to FIG. 48C The transistor 510Da shown has the components of the transistor 510D except for the conductive layer 505 and the conductive layer 503 .

[0679] Fig.48A is a top view of the transistor 510Da. Fig.48B is Fig.48A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.48C is Fig.48A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.48A In the top view, part of the components are omitted for clarity.

[0680] <Transistor Structure Example 5>

[0681] Reference Fig.42A , Fig.42B and Fig.42C A structural example of the transistor 510E is described. Fig.42A is a top view of transistor 510E. Fig.42B is Fig.42A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.42C is Fig.42A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.42A In the top view, part of the components are omitted for clarity.

[0682] The transistor 510E is a modified example of the above-described transistor. Therefore, in order to avoid duplication of descriptions, the differences from the above-described transistor will be mainly described.

[0683] exist FIG. 42A to FIG. 42C In the embodiment, the conductive layer 505 having the function of the second gate is also used as a wiring without providing the conductive layer 503. In addition, an insulating layer 550 is included on the oxide 530c, and a metal oxide 552 is included on the insulating layer 550. In addition, a conductive layer 560 is included on the metal oxide 552, and an insulating layer 570 is included on the conductive layer 560. In addition, an insulating layer 571 is included on the insulating layer 570.

[0684] The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 that suppresses oxygen diffusion between the insulating layer 550 and the conductive layer 560, oxygen diffusion to the conductive layer 560 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductive layer 560 due to oxygen can be suppressed.

[0685] In addition, the metal oxide 552 may be used as a part of the first gate. For example, an oxide semiconductor that can be used as the oxide 530 may be used as the metal oxide 552. In this case, by forming the conductive layer 560 by sputtering, the resistance value of the metal oxide 552 may be reduced to make it a conductive layer. This may be referred to as an OC (Oxide Conductor) electrode.

[0686] In addition, the metal oxide 552 is sometimes used as a part of the gate insulating layer. Therefore, when silicon oxide or silicon oxynitride is used for the insulating layer 550, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide 552. By adopting this stacked structure, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0687] Although the metal oxide 552 in the transistor 510E is shown to have a single-layer structure, a stacked structure of two or more layers may be employed. For example, a metal oxide used as part of a gate electrode and a metal oxide used as part of a gate insulating layer may be stacked.

[0688] When the metal oxide 552 is used as a gate electrode, the on-state current of the transistor 510E can be increased without weakening the influence of the electric field from the conductive layer 560. In addition, when the metal oxide 552 is used as a gate insulating layer, the leakage current between the conductive layer 560 and the oxide 530 can be suppressed by maintaining the distance between the conductive layer 560 and the oxide 530 using the physical thickness of the insulating layer 550 and the metal oxide 552. Thus, by providing a stacked structure of the insulating layer 550 and the metal oxide 552, the physical distance between the conductive layer 560 and the oxide 530 and the electric field strength applied from the conductive layer 560 to the oxide 530 can be easily adjusted.

[0689] Specifically, an oxide semiconductor that can be used for the oxide 530 can be used as the metal oxide 552 by reducing its resistance. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0690] In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as an insulating layer containing an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. Note that the metal oxide 552 is not an essential component and can be appropriately designed according to the desired transistor characteristics.

[0691] An insulating material having a function of inhibiting the permeation of impurities such as water or hydrogen and oxygen is preferably used as the insulating layer 570. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxidation of the conductive layer 560 due to oxygen from above the insulating layer 570 can be prevented. In addition, impurities such as water or hydrogen from above the insulating layer 570 can be inhibited from entering the oxide 230 through the conductive layer 560 and the insulating layer 550.

[0692] The insulating layer 571 is used as a hard mask. By providing the insulating layer 571, the conductive layer 560 can be processed in such a way that the side surface of the conductive layer 560 is approximately perpendicular to the substrate surface. Specifically, the angle formed by the side surface of the conductive layer 560 and the substrate surface can be made greater than 75 degrees and less than 100 degrees, preferably greater than 80 degrees and less than 95 degrees.

[0693] Alternatively, the insulating layer 571 may also function as a barrier layer by using an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. In this case, the insulating layer 570 may not be provided.

[0694] By using the insulating layer 571 as a hard mask, the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and part of the oxide 530c are selectively removed, so that their side surfaces can be roughly aligned and part of the surface of the oxide 530b can be exposed.

[0695] In addition, the transistor 510E has a region 531a and a region 531b in a portion of the surface of the exposed oxide 530b. One of the region 531a and the region 531b is used as a source region, and the other is used as a drain region.

[0696] For example, the regions 531a and 531b can be formed by introducing an impurity element such as phosphorus or boron into the surface of the exposed oxide 530b by ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. Note that in this embodiment mode, "impurity element" refers to an element other than a main component element.

[0697] Alternatively, after a portion of the surface of the oxide 530 b is exposed, a metal film may be formed, and then heat treatment may be performed to diffuse elements included in the metal film into the oxide 530 b , thereby forming the regions 531 a and 531 b .

[0698] The resistivity of the region into which the impurity element is introduced in the oxide 530b decreases. Therefore, the region 531a and the region 531b are sometimes referred to as “impurity regions” or “low resistance regions”.

[0699] By using the insulating layer 571 and / or the conductive layer 560 as a mask, the region 531a and the region 531b can be formed in a self-aligned manner. Therefore, the region 531a and / or the region 531b do not overlap with the conductive layer 560, and the parasitic capacitance can be reduced. In addition, the bias region is not formed between the channel formation region and the source and drain region (region 531a or region 531b). By forming the region 531a and the region 531b in a self-aligned manner, an increase in on-state current, a decrease in threshold voltage, an increase in operating frequency, etc. can be achieved.

[0700] In addition, in order to further reduce the off-state current, a bias region may be provided between the channel formation region and the source / drain region. The bias region is a region with high resistivity and is a region where the above-mentioned impurity elements are not introduced. The bias region can be formed by introducing the above-mentioned impurity elements after forming the insulating layer 575. In this case, the insulating layer 575 is also used as a mask as in the case of the insulating layer 571. Therefore, the region of the oxide 530b overlapping with the insulating layer 575 is not introduced with impurity elements, thereby maintaining the resistivity of the region high.

[0701] The transistor 510E includes an insulating layer 575 on the side of the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and the oxide 530c. The insulating layer 575 is preferably an insulating layer having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin is preferably used. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide with pores is used for the insulating layer 575, it is preferred because an excess oxygen region can be easily formed in the insulating layer 575 in the subsequent process. In addition, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In addition, the insulating layer 575 preferably has a function of diffusing oxygen.

[0702] The transistor 510E includes an insulating layer 574 over the insulating layer 575 and the oxide 530. The insulating layer 574 is preferably formed by a sputtering method. By using a sputtering method, an insulating layer with less impurities such as water and hydrogen can be formed. For example, aluminum oxide is preferably used as the insulating layer 574.

[0703] An oxide film formed by sputtering may extract hydrogen from a structure. Therefore, the insulating layer 574 extracts hydrogen and water from the oxide 230 and the insulating layer 575 to reduce the hydrogen concentration of the oxide 230 and the insulating layer 575.

[0704] Furthermore, the conductive layer 505 may be omitted as necessary. FIG. 49A to FIG. 49C The transistor 510Ea shown has components of the transistor 510E except for the conductive layer 505 and the conductive layer 503 .

[0705] Fig.49A is a top view of transistor 510Ea. Fig.49B is Fig.49A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.49C is Fig.49A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.49A In the top view, part of the components are omitted for clarity.

[0706] <Transistor Structure Example 6>

[0707] Reference Fig.43A , Fig.43B and Fig.43C A structural example of the transistor 510F is described. Fig.43A is a top view of transistor 510F. Fig.43B is Fig.43A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.43C is Fig.43A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.43A In the top view, part of the components are omitted for clarity.

[0708] The transistor 510F is a modified example of the above-described transistor. Therefore, in order to avoid duplication of descriptions, the differences from the above-described transistor will be mainly described.

[0709] The transistor 510F has a structure in which the transistor 510C_1 and the transistor 510C_2 are connected in parallel. Specifically, one of the source or drain of the transistor 510C_1 is electrically connected to one of the source or drain of the transistor 510C_2 through one of the conductive layers 546a or 546b. In addition, the other of the source or drain of the transistor 510C_1 is electrically connected to the other of the source or drain of the transistor 510C_2 through the other of the conductive layers 546a or 546b. In addition, the conductive layer 560 is used as the gate electrode of the transistor 510C_1 and the transistor 510C_2.

[0710] Both transistor 510C_1 and transistor 510C_2 have the same structure as transistor 510C. Thus, transistor 510F is a transistor in which two transistors 510C are connected in parallel. In addition, the number of transistors connected in parallel is not limited to two, but may be three or more. For example, in the case where transistor 510F is used as a transistor constituting a memory cell, the number of transistors connected in parallel may be determined according to the cell size. In addition, the structure of transistors connected in parallel is not limited to transistor 510C.

[0711] The conductive layer 505_1 included in the transistor 510C_1 is used as a back gate electrode. The conductive layer 505_2 included in the transistor 510C_2 is used as a back gate electrode. The conductive layer 505_1 and the conductive layer 505_2 can be formed using the same material and method as the conductive layer 505.

[0712] When the channel width is increased to increase the on-state current, the S value (subthreshold swing value) is likely to increase and the normally-on state is likely to occur. In particular, transistors with short channel lengths show this tendency significantly. The S value is one of the parameters that show the electrical characteristics of the transistor, and the smaller the value, the better. By dividing the channel width into multiple pieces, the on-state current can be increased without increasing the S value. In addition, the on-state current can be increased without normally-on state.

[0713] In addition, in the case of a transistor having an S-channel structure in which the effective channel width is larger than the apparent channel width due to the formation of a channel on the side of the semiconductor layer, the effect of the transistor is reduced when the channel width is increased. By dividing the channel width into multiple parts, the actual channel width can be increased while maintaining the effect of the S-channel structure.

[0714] When the channel width is divided into a plurality of channels, the divided channel widths are preferably equal or substantially equal. In the transistor 510F, the channel width of the transistor 510C_1 and the channel width of the transistor 510C_2 are preferably equal or substantially equal. Assuming that W1 and W2 represent the channel width of the transistor 510C_1 and the channel width of the transistor 510C_2, respectively, W1 is preferably 0.8 times or more and 1.2 times or less of W2, more preferably 0.9 times or more and 1.1 times or less, and further preferably 0.95 times or more and 1.05 times or less.

[0715] Note that the conductive layer 505 which functions as a back gate electrode and the conductive layer 503 which functions as a wiring can be omitted as necessary. FIG. 50A to FIG. 50C The transistor 510Fa shown in the figure has the components of the transistor 510F except for the conductive layer 505 and the conductive layer 503 .

[0716] Fig.50A is a top view of the transistor 510Fa. Fig.50B is Fig.50A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.50C is Fig.50A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.50A In the top view, part of the components are omitted for clarity.

[0717] <Transistor Structure Example 7>

[0718] Reference Fig.44A and Fig.44B A structural example of the transistor 510G is described. Fig.44A is a top view of transistor 510G. Fig.44B is Fig.44A A cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. Fig.44A In the top view, part of the components are omitted for clarity.

[0719] The transistor 510G is a modified example of the transistor 510F. Therefore, in order to avoid duplication of description, the difference from the transistor 510F will be mainly described.

[0720] The transistor 510G is a transistor in which the transistor 510C_1 and the transistor 510C_2 are connected in parallel and has a different structure from the transistor E. Specifically, the conductive layer 505_1 and the conductive layer 505_2 are electrically connected. In addition, one of the source or drain of the transistor 510C_1 is electrically connected to one of the source or drain of the transistor 510C_2. Fig.44A and Fig.44B In the embodiment, one of the source or drain of the transistor 510C_1 and one of the source or drain of the transistor 510C_2 are used in common and are electrically connected to the conductive layer 546b. In addition, the transistor 510C_1 has the conductive layer 560_1 used as a gate electrode, and the transistor 510C_2 has the conductive layer 560_2 used as a gate electrode. In addition, the conductive layer 560_1 and the conductive layer 560_2 are electrically connected.

[0721] The conductive layer 560_1 and the conductive layer 560_2 can be formed using the same material and method as the conductive layer 560. Fig.44A and Fig.44B , an example is shown in which a portion of the conductive layer 560 is used as the conductive layer 560_1 and another portion of the conductive layer 560 is used as the conductive layer 560_2.

[0722] In addition, the other of the source or drain of the transistor 510C_1 is electrically connected to the conductive layer 546a, and the other of the source or drain of the transistor 510C_2 is electrically connected to the conductive layer 546c. The conductive layer 546c can be formed using the same material and method as the conductive layer 546a and the conductive layer 546b. In addition, the insulating layer 576c can be formed using the same material and method as the insulating layer 576a and the insulating layer 576b.

[0723] In the transistor 510G, the conductive layer 546b is electrically connected to one of the source and the drain of the transistor 510G, and the conductive layer 546a and the conductive layer 546b are electrically connected to the other of the source and the drain of the transistor 510G.

[0724] The transistor 510G also has the same effect as the transistor 510F.

[0725] Note that the conductive layer 505 which functions as a back gate electrode and the conductive layer 503 which functions as a wiring can be omitted as necessary. FIG. 51A to FIG. 51B The transistor 510Ga shown has the components of the transistor 510G except for the conductive layer 505 and the conductive layer 503.

[0726] Fig.51A is a top view of transistor 510Ga. Fig.51B is Fig.51A A cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. Fig.51A In the top view, part of the components are omitted for clarity.

[0727] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0728] (Implementation method 9)

[0729] This embodiment mode describes a concept of a commercial product to which the storage device described in the above embodiment mode can be applied and an example of an electronic component and an electronic device in which the storage device described in the above embodiment mode and the like are mounted.

[0730] 〈Concept of Product〉

[0731] first, Fig.52 The concept of a commercial product to which a storage device according to one embodiment of the present invention can be applied is shown. Fig.52 Region 801 shown represents high temperature characteristics (High T operation), region 802 represents high frequency characteristics (High f operation), region 803 represents low off characteristics (Ioff), and region 804 represents a region where regions 801 , 802 , and 803 overlap.

[0732] When region 801 is to be satisfied, carbides or nitrides such as silicon carbide or gallium nitride are used for the channel formation region of the transistor, which is generally satisfied. In addition, when region 802 is to be satisfied, silicides such as single crystal silicon or crystalline silicon are used for the channel formation region of the transistor, which is generally satisfied. In addition, when region 803 is to be satisfied, oxide semiconductors or metal oxides are used for the channel formation region of the transistor, which is generally satisfied.

[0733] The storage device according to one embodiment of the present invention can be applied to commodities within the range shown in area 804, for example.

[0734] It is difficult for existing products to satisfy all of the regions 801, 802, and 803. However, a transistor included in a memory device according to one embodiment of the present invention includes a crystalline OS in a channel formation region. When a crystalline OS is included in a channel formation region, a memory device and an electronic device that satisfy high temperature characteristics, high frequency characteristics, and low off characteristics can be provided.

[0735] Examples of products within the range shown in area 804 include electronic devices with low power consumption and high performance CPUs, and in-vehicle electronic devices that require high reliability in high temperature environments. An example of an electronic component and electronic device equipped with a storage device according to one embodiment of the present invention is shown below.

[0736] 〈Electronic components〉

[0737] First, refer to Fig.53A and Fig.53B An example of an electronic component in which the storage device 100 is incorporated will be described.

[0738] Fig.53A A perspective view is shown of an electronic component 700 and a substrate (circuit board 704) on which the electronic component 700 is mounted. Fig.53A The electronic component 700 shown is an IC chip, and includes leads and a circuit portion. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of these IC chips are combined and electrically connected to each other on the printed circuit board 702, thereby completing a circuit board 704.

[0739] The memory device 100 described in the above embodiment is provided as the circuit portion of the electronic component 700. Fig.53A In the embodiment, a QFP (Quad Flat Package) is used as a package of the electronic component 700, but the packaging method is not limited to this.

[0740] Fig.53B 1 is a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 100 are provided on the interposer 731.

[0741] The electronic component 730 shows an example in which the storage device 100 is used as a high bandwidth memory (HBM: High Bandwidth Memory). Alternatively, the semiconductor device 735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0742] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0743] The plug board 731 has a plurality of wirings that can be electrically connected to a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon plug board is used, TSV (Through Silicon Via: silicon through hole) can also be used as a through electrode.

[0744] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. The wiring formation of a silicon interposer can be performed in a semiconductor process, and a resin interposer is easier to form fine wiring.

[0745] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0746] In addition, in SiP or MCM using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection is not likely to occur between the integrated circuit disposed on the silicon interposer and the silicon interposer. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0747] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 are aligned. For example, in the electronic component 730 shown in this embodiment, it is preferable that the heights of the storage device 100 and the semiconductor device 735 are aligned.

[0748] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the packaging substrate 732 . Fig.53BAn example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0749] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) can be used.

[0750] 〈Electronic equipment〉

[0751] Next, refer to Fig.54 An example of an electronic device in which the above-mentioned electronic components are mounted will be described.

[0752] The robot 7100 includes an illumination sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezoelectric sensor, optical sensor, gyro sensor, etc.), a moving mechanism, etc. The electronic component 730 includes a processor, etc. and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data measured by the sensor.

[0753] The microphone has a function of detecting audio signals such as the user's voice and surrounding sounds. In addition, the speaker has a function of emitting audio signals such as sounds and warning sounds. The robot 7100 can analyze the audio signals input through the microphone and emit the required audio signals from the speaker. The robot 7100 can communicate with the user by using the microphone and the speaker.

[0754] The camera has a function of capturing images of the surroundings of the robot 7100. In addition, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture images of the surroundings using the camera and analyze the images to determine the presence or absence of obstacles during movement.

[0755] The flying object 7120 includes propellers, a camera, a battery, etc., and has an autonomous flight function. The electronic component 730 has a function of controlling the above peripheral devices.

[0756] For example, image data captured by a camera is stored in the electronic component 700. The electronic component 730 can analyze the image data to determine the presence or absence of obstacles during movement, etc. In addition, the electronic component 730 can estimate the remaining power of the battery by the change in the storage capacity of the battery.

[0757] The cleaning robot 7140 includes a display configured on the top surface, multiple cameras configured on the side, a brush, operation buttons, and various sensors, etc. Although not shown in the figure, the cleaning robot 7300 is equipped with tires, a suction port, etc. The cleaning robot 7300 can walk automatically, detect garbage, and suck garbage from the suction port on the bottom surface.

[0758] For example, the electronic component 730 can determine the presence or absence of obstacles such as walls, furniture or steps by analyzing the images taken by the camera. In addition, when objects such as wiring that may be wrapped around the brush are detected by image analysis, the rotation of the brush can be stopped.

[0759] The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 730 performs control to optimize the driving state of the automobile 7160 based on data such as navigation information, speed, engine status, gear selection status, brake usage frequency, etc. For example, image data captured by a camera is stored in the electronic component 700.

[0760] The electronic component 700 and / or the electronic component 730 may be installed in a television receiver (TV) device 7200 , a smartphone 7210 , a PC 7220 (personal computer), 7230 , a game console 7240 , a game console 7260 , or the like.

[0761] For example, the electronic component 730 provided in the TV set 7200 may be used as an image engine. For example, the electronic component 730 performs image processing such as noise removal and up-conversion of resolution.

[0762] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. The electronic component 730 controls the above peripheral devices.

[0763] PC 7220 and PC 7230 are examples of a notebook PC and a desktop PC, respectively. A keyboard 7232 and a display device 7233 can be connected to PC 7230 wirelessly or by wire. A game console 7240 is an example of a portable game console. A game console 7260 is an example of a fixed game console. The game console 7260 is connected to a controller 7262 wirelessly or by wire. The electronic component 700 and / or the electronic component 730 can be installed in the controller 7262.

[0764] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0765] [Explanation of symbols]

[0766] 100: memory device, 111: input / output circuit, 112: control circuit, 113: C receiver, 114: setting register, 115: LVDS circuit, 117: decoder, 118: register, 119: register, 127: sense amplifier, 210: memory block array, 211: memory block, 212: word line driver, 213: local sense amplifier driver, 214: local sense amplifier array, 215: global sense amplifier, 216: selector, 230: oxide, 231: switch, 232: switch, 233: switch, 234: switch

Claims

1. A storage device, comprising: a first unit array; A second unit array is disposed on the first unit array; a pair of first bit lines electrically connected to the first sense amplifier; as well as a pair of second bit lines electrically connected to a second sense amplifier, The first unit array and the second unit array have an overlapping area. The first unit array comprises: A first storage unit group includes A first storage units, where A is an integer greater than 1; A second storage unit group includes B first storage units, where B is an integer greater than 1; A third storage unit group includes C first storage units, where C is an integer greater than 1; a fourth storage unit group, comprising A first storage units; a fifth storage unit group, comprising B first storage units; and a sixth storage unit group, comprising C first storage units, The second unit array comprises: a seventh storage unit group, comprising D second storage units, wherein D is an integer greater than 1; an eighth storage unit group, comprising E second storage units, wherein E is an integer greater than 1; a ninth storage unit group, comprising F second storage units, wherein F is an integer greater than 1; a tenth storage unit group, comprising D second storage units; an eleventh storage unit group, comprising E second storage units; and A twelfth storage unit group includes F second storage units, One of the pair of first bit lines is electrically connected to the first memory cell group, the third memory cell group, and the ninth memory cell group. The other of the pair of first bit lines is electrically connected to the second memory cell group, the seventh memory cell group, and the eighth memory cell group. One of the pair of second bit lines is electrically connected to the fourth memory cell group, the sixth memory cell group, and the twelfth memory cell group. The other of the pair of second bit lines is electrically connected to the fifth memory cell group, the tenth memory cell group, and the eleventh memory cell group. When the first cell array is viewed from the Z direction, a portion of the fourth storage cell group is adjacent to the second storage cell group. When the first cell array is viewed from the Z direction, another part of the fourth storage cell group is adjacent to the third storage cell group. When the second cell array is viewed from the Z direction, a portion of the tenth memory cell group is adjacent to the eighth memory cell group. Furthermore, when the second cell array is viewed from the Z direction, another portion of the tenth memory cell group is adjacent to the ninth memory cell group. 2 . The memory device according to claim 1 , further comprising a plurality of the pair of first bit lines and a plurality of the pair of second bit lines.

3. The storage device according to claim 1 or 2, Each of the first memory cells has a first transistor and a first capacitor. And each of the second memory cells has a second transistor and a second capacitor.

4. The storage device according to claim 3, The first transistor and the second transistor include oxide semiconductors in the semiconductor layer. The storage device according to claim 1 , wherein the C is greater than or equal to 0.8 times and less than or equal to 1.2 times the B. The storage device according to claim 1 , wherein the C is equal to the B. 7 . The storage device according to claim 1 , wherein the F is greater than or equal to 0.8 times and less than or equal to 1.2 times the E. The storage device according to claim 1 , wherein the F is equal to the E.

9. A storage device, comprising: a first unit array; A second unit array is arranged on the first unit array; a pair of first bit lines and a pair of second bit lines, each electrically connected to the first sense amplifier; a pair of third bit lines and a pair of fourth bit lines, each electrically connected to the second sense amplifier; a pair of fifth bit lines and a pair of sixth bit lines, each electrically connected to the third sense amplifier; and a pair of seventh bit lines and a pair of eighth bit lines, each electrically connected to a fourth sense amplifier; The first unit array and the second unit array have an overlapping area. The first unit array comprises: A first storage unit group includes A first storage units, where A is an integer greater than 1; A second storage unit group includes B first storage units, where B is an integer greater than 1; A third storage unit group includes C first storage units, where C is an integer greater than 1; a fourth storage unit group, comprising A first storage units; a fifth storage unit group, comprising B first storage units; a sixth storage unit group, comprising C first storage units; a seventh storage unit group, comprising A first storage units; an eighth storage unit group, comprising B first storage units; a ninth storage unit group, comprising C first storage units; a tenth storage unit group, comprising A first storage units; an eleventh storage unit group, comprising B first storage units; and A twelfth storage unit group includes C first storage units, The second unit array comprises: A thirteenth storage unit group includes D second storage units, where D is an integer greater than 1; A fourteenth storage unit group includes E second storage units, where E is an integer greater than 1; A fifteenth storage unit group includes F second storage units, where F is an integer greater than 1; A sixteenth storage unit group includes D second storage units; A seventeenth storage unit group includes E second storage units; An eighteenth storage unit group, comprising F second storage units; A nineteenth storage unit group includes D second storage units; A twentieth storage unit group, including E second storage units; A twenty-first storage unit group includes F second storage units; A twenty-second storage unit group, including D second storage units; A twenty-third storage unit group includes E second storage units; and A twenty-fourth storage unit group includes F second storage units, One of the pair of first bit lines is electrically connected to the second memory cell group and the fourteenth memory cell group, One of the pair of second bit lines is electrically connected to the thirteenth memory cell group, The other of the pair of first bit lines is electrically connected to the third memory cell group and the fifteenth memory cell group, The other of the pair of second bit lines is electrically connected to the first memory cell group, One of the pair of third bit lines is electrically connected to the sixth memory cell group and the eighteenth memory cell group, One of the pair of fourth bit lines is electrically connected to the sixteenth memory cell group, The other of the pair of third bit lines is electrically connected to the fifth memory cell group and the seventeenth memory cell group, The other of the pair of fourth bit lines is electrically connected to the fourth memory cell group, One of the pair of fifth bit lines is electrically connected to the ninth memory cell group and the twenty-first memory cell group, One of the pair of sixth bit lines is electrically connected to the nineteenth memory cell group, The other of the pair of fifth bit lines is electrically connected to the eighth memory cell group and the twentieth memory cell group, The other of the pair of sixth bit lines is electrically connected to the seventh memory cell group, One of the pair of seventh bit lines is electrically connected to the eleventh memory cell group and the twenty-third memory cell group, One of the pair of eighth bit lines is electrically connected to the twenty-second memory cell group, The other of the pair of seventh bit lines is electrically connected to the twelfth memory cell group and the twenty-fourth memory cell group, The other of the pair of eighth bit lines is electrically connected to the tenth memory cell group, When the first cell array is viewed from the Z direction, the second memory cell group and the ninth memory cell group are adjacent to a portion of the fourth memory cell group. When the first cell array is viewed from the Z direction, the third storage cell group and the eighth storage cell group are adjacent to another part of the fourth storage cell group. When the first cell array is viewed from the Z direction, a portion of the tenth memory cell group is adjacent to the ninth memory cell group. When the first cell array is viewed from the Z direction, another part of the tenth storage cell group is adjacent to the eighth storage cell group. When the second cell array is viewed from the Z direction, the fourteenth memory cell group and the twenty-first memory cell group are adjacent to a portion of the sixteenth memory cell group. When the second cell array is viewed from the Z direction, the fifteenth memory cell group and the twentieth memory cell group are adjacent to another part of the sixteenth memory cell group. When the second cell array is viewed from the Z direction, a portion of the twenty-second memory cell group is adjacent to the twenty-first memory cell group. Furthermore, when the second cell array is viewed from the Z direction, another portion of the 22nd memory cell group is adjacent to the 20th memory cell group.

10. The storage device according to claim 9, Each of the first memory cells has a first transistor and a first capacitor. And each of the second memory cells has a second transistor and a second capacitor.

11. The storage device according to claim 10, The first transistor and the second transistor include oxide semiconductors in the semiconductor layer.

12. The storage device according to claim 9, wherein the one of the pair of first bit lines is electrically connected to an eleventh switch, The one of the pair of second bit lines is electrically connected to a twelfth switch, The other of the pair of first bit lines is electrically connected to a thirteenth switch, And, the other one of the pair of second bit lines is electrically connected to a fourteenth switch.

13. The storage device according to claim 9, wherein the one of the pair of third bit lines is electrically connected to a twenty-first switch, The one of the pair of fourth bit lines is electrically connected to the twenty-second switch, The other of the pair of third bit lines is electrically connected to a twenty-third switch, And, the other one of the pair of fourth bit lines is electrically connected to the twenty-fourth switch.

14. The storage device according to claim 9, wherein the one of the pair of fifth bit lines is electrically connected to a thirty-first switch, The one of the pair of sixth bit lines is electrically connected to a thirty-second switch, The other of the pair of fifth bit lines is electrically connected to a thirty-third switch, And, the other of the pair of sixth bit lines is electrically connected to a thirty-fourth switch.

15. The storage device according to claim 9, wherein the one of the pair of seventh bit lines is electrically connected to a forty-first switch, The one of the pair of eighth bit lines is electrically connected to a forty-second switch, the other of the pair of seventh bit lines is electrically connected to a forty-third switch, And, the other one of the pair of eighth bit lines is electrically connected to a forty-fourth switch. 16 . The storage device according to claim 9 , wherein the E is greater than or equal to 0.8 times and less than or equal to 1.2 times the B. The storage device according to claim 9 , wherein the E is equal to the B. 18 . The storage device according to claim 9 , wherein the F is greater than or equal to 0.8 times and less than or equal to 1.2 times the C. 19 . The storage device according to claim 9 , wherein a sum of B and C is greater than or equal to 0.8 times and less than or equal to 1.2 times greater than A. 20 . The storage device of claim 9 , wherein the sum of B and C is equal to A. 21 . The storage device according to claim 9 , wherein a sum of the E and the F is greater than or equal to 0.8 times and less than or equal to 1.2 times the D.

22. The storage device of claim 9, wherein a sum of said E and said F is equal to said D.

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