A BOOST boost circuit with low input voltage and strong driving capability

Abstract

The present invention discloses a BOOST boost circuit with low input voltage and strong driving capability, and relates to the technical field of power chip. A voltage stabilizing circuit and a driving circuit are arranged inside the chip, and the output voltage HVDD is connected to the voltage stabilizing circuit, and the voltage stabilizing circuit is connected to the driving circuit, and the driving circuit is connected to the gate of a switch tube. A diode is forwardly connected between the drain of the switch tube and the output voltage HVDD, and the source of the switch tube is grounded, and the input voltage VDD is connected to the drain of the switch tube through an inductor. Under the condition of low input voltage, the present invention can still ensure that after the BOOST boost circuit works stably, the gate driving voltage of the switch tube is sufficient to be 5V, so as to ensure its effective conduction capability.

Description

Technical Field

[0001] The invention relates to the technical field of power chip, in particular to a BOOST voltage-boosting circuit with low input voltage and strong driving capability. Background Art

[0002] The BOOST boost circuit is a common switching DC boost circuit that can make the output voltage higher than the input voltage. Due to limitations such as the working environment, the input voltage of some BOOST boost circuits is relatively low (for example, lower than 3V), while the gate voltage of the switch tube in the BOOST boost circuit is relatively high (for example, 5V). If a lower input voltage is used to drive the gate of the switch tube, when the switch tube is turned on, its gate voltage is a lower input voltage. At this time, the on-resistance of the switch tube is much larger than the on-resistance when its gate voltage is 5V. In order to achieve the driving capability required by the design, the area of ​​the switch tube can only be relatively increased, but this will increase the cost. In addition, it will also cause problems such as low efficiency due to excessive charging and discharging current of the gate capacitor. Summary of the invention

[0003] In view of the above technical problems, the present invention provides a low-cost, high-efficiency battery charging and discharging circuit, which can provide a large current to the load while charging the battery, thereby improving the output efficiency when the USB supplies power to the load.

[0004] A BOOST boost circuit with low input voltage and strong driving capability, with an input voltage VDD and an output voltage HVDD. A voltage stabilizing circuit and a driving circuit are arranged inside the chip. The output voltage HVDD is connected to the voltage stabilizing circuit, the voltage stabilizing circuit is connected to the driving circuit, the driving circuit is connected to the gate of a switching tube, a diode is forwardly connected between the drain of the switching tube and the output voltage HVDD, the source of the switching tube is grounded, and the input voltage VDD is connected to the drain of the switching tube through an inductor.

[0005] Furthermore, the voltage stabilizing circuit is composed of a regulating branch and an output branch, the regulating branch mainly includes a first NMOS tube and a feedback regulating circuit connected to the source of the first NMOS tube, the output branch mainly includes a second NMOS tube, and the output LDO_OUT of the voltage stabilizing circuit is taken from the source of the second NMOS tube; the gate of the first NMOS tube is connected to the gate of the second NMOS tube, and the output voltage HVDD is connected to the drain and gate of the first NMOS tube through a bias current source; the feedback regulating circuit mainly includes a low-voltage amplifier and a voltage boosting circuit, the positive and negative input terminals of the low-voltage amplifier are respectively connected to the reference voltage VREF and the feedback signal, and its output is connected to the source of the first NMOS tube through the voltage boosting circuit.

[0006] Furthermore, the feedback signal is taken from the output branch, the source of the second NMOS tube is grounded via the first adjustment resistor and the second adjustment resistor in sequence, and the positive and negative input terminals of the low voltage amplifier are respectively connected to the reference voltage VREF and the second adjustment resistor voltage.

[0007] Alternatively, the feedback signal is taken from the regulation branch, the source of the first NMOS tube is grounded via the first adjustment resistor and the second adjustment resistor in sequence, the positive and negative input terminals of the low-voltage amplifier are respectively connected to the reference voltage VREF and the second adjustment resistor voltage; the source of the second NMOS tube is grounded via the grounding resistor.

[0008] Alternatively, the gate of the first NMOS tube is grounded via the first adjustment resistor and the second adjustment resistor in sequence, the positive and negative input terminals of the low voltage amplifier are respectively connected to the reference voltage VREF and the second adjustment resistor voltage; the source of the second NMOS tube is grounded via the grounding resistor.

[0009] Furthermore, a voltage limiting PMOS tube is connected between the output voltage HVDD and the voltage stabilizing circuit output LDO_OUT, the output voltage HVDD is connected to the drain of the voltage limiting PMOS tube, the source of the voltage limiting PMOS tube is connected to the voltage stabilizing circuit output LDO_OUT, and its gate is connected to the control signal SCT.

[0010] Furthermore, the circuit boosting circuit is composed of a plurality of PMOS tubes whose gates and drains are connected in sequence, the output of the low voltage amplifier is connected to the gate of the first PMOS tube, and the source of the last PMOS tube is connected to the source of the first NMOS tube.

[0011] Furthermore, the circuit boosting circuit is composed of a PMOS tube and a voltage stabilizing diode, the output of the low voltage amplifier is connected to the gate of the PMOS tube, and the source of the PMOS tube is connected to the source of the first NMOS tube via the voltage stabilizing diode.

[0012] The beneficial effects of the present invention are as follows: 1. When the input voltage is low, the gate drive voltage of the switch tube can still be guaranteed to be 5V after the BOOST boost circuit works stably, thereby ensuring its effective conduction capability; 2. The voltage stabilization circuit does not require high-voltage capacitors for compensation; the process does not require the addition of device types, and can be achieved by increasing the number of MOS tubes; it is easy to integrate, does not require high-voltage compensation capacitors, and the LDO output is not affected by the matching degree of the high-voltage tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the schematic diagram of the BOOST boost circuit;

[0014] Figure 2 This is the principle diagram of the voltage stabilizing circuit in Example 1;

[0015] Figure 3 It is the principle diagram of the voltage stabilizing circuit in Example 2;

[0016] Figure 4 This is the principle diagram of the voltage stabilizing circuit in Example 3;

[0017] Figure 5 It is a schematic diagram of a voltage boosting circuit;

[0018] Figure 6 This is another schematic diagram of a voltage boost circuit;

[0019] Figure 7 The schematic diagram of the voltage stabilizing circuit of Embodiment 1 including the startup guarantee circuit;

[0020] Figure 8 The schematic diagram of the voltage stabilizing circuit of Embodiment 2 including the startup guarantee circuit;

[0021] Fig. 9 The schematic diagram of the voltage stabilizing circuit of Example 3 including the startup guarantee circuit is shown in FIG. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present invention are provided for the purpose of illustration and description, and are not intended to be exhaustive or to limit the present invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention, and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

[0023] Example 1

[0024] A BOOST boost circuit with low input voltage and strong driving capability, with input voltage VDD and output voltage HVDD. A voltage stabilizing circuit and a driving circuit are arranged inside the chip. The output voltage HVDD is connected to the voltage stabilizing circuit, the voltage stabilizing circuit is connected to the driving circuit, the driving circuit is connected to the gate of a switch tube, a diode is forwardly connected between the drain of the switch tube and the output voltage HVDD, the source of the switch tube is grounded, and the input voltage VDD is connected to the drain of the switch tube through an inductor. Figure 1 shown.

[0025] from Figure 1 It can be seen that when BOOST is just started, the output voltage HVDD is one diode drop (about 0.3V) lower than the input voltage VDD. Then the output voltage HVDD is used as the input voltage of the internal voltage regulator circuit of the chip. The voltage regulator circuit with an output of 5V is designed. This 5V voltage is used as the driving voltage of the BOOST switch tube, which effectively improves the conduction ability of the switch tube. Figure 1 Except for the driver stage, all other circuits of the chip are powered by the input voltage VDD; the voltage regulator circuit of the driver stage is powered by the high-voltage output voltage HVDD of BOOST, and the driving circuit of the switch tube is powered by the 5V voltage output by the voltage regulator circuit. Therefore, after the BOOST boost circuit works stably, the gate drive voltage of the switch tube is sufficient to be 5V, ensuring its effective conduction capability.

[0026] When conventional amplifiers are used to design LDOs, high voltage capacitors are required for phase compensation. However, high voltage capacitors are not easy to implement in integrated ICs. Even if the process supports high voltage compensation capacitors, poor matching of high voltage tubes will lead to an increase in the area of ​​the LDO or deterioration in performance. To address this problem, this embodiment also provides a voltage stabilizing circuit structure that is easy to integrate.

[0027] The voltage stabilizing circuit is composed of a regulating branch and an output branch. The regulating branch mainly includes a first NMOS tube NM1 and a feedback regulating circuit connected to the source of the first NMOS tube. The output branch mainly includes a second NMOS tube NM2. The output of the voltage stabilizing circuit is taken from the source of the second NMOS tube.

[0028] The gate of the first NMOS tube is connected to the gate of the second NMOS tube, and the output voltage HVDD is connected to the drain and gate of the first NMOS tube via the bias current source I1; the feedback regulation circuit mainly includes a low-voltage amplifier and a voltage boosting circuit, the positive and negative input terminals of the low-voltage amplifier are respectively connected to the reference voltage VREF and the feedback signal, and its output is connected to the source of the first NMOS tube via the voltage boosting circuit.

[0029] In this embodiment, the feedback signal is taken from the output branch, such as Figure 2 As shown, the source of the second NMOS tube is connected to the ground via the first adjustment resistor R1 and the second adjustment resistor R2 in sequence, and the positive and negative input terminals of the low voltage amplifier are connected to the reference voltage VREF and the second adjustment resistor voltage respectively.

[0030] The low-voltage amplifier works normally, and its positive and negative input voltages are approximately equal, that is, VREF and point A voltages are approximately equal. By adjusting the ratio of the first adjustment resistor R1 and the second adjustment resistor R2, the output LDO_OUT is higher than VDD and has driving capability. By adjusting the boost voltage of the voltage boost circuit, the normal operation of the low-voltage amplifier is guaranteed. Due to the process angle deviation and the temperature deviation of the device parameters, the boost voltage deviation of the voltage boost circuit is large, but in combination with the low-voltage amplifier, the maximum deviation range of the boost voltage that the voltage boost circuit can tolerate is 0V-VDD. In this embodiment, the output LDO_OUT is in the feedback loop, so that the output voltage value is more accurate.

[0031] The bias current I1 is used to provide a DC operating point for the first NMOS tube NM1. There are two voltage domains inside the chip, namely low voltage VDD and high voltage HVDD. The input voltage of the low voltage amplifier is VDD, that is, it works in the low voltage domain, and its output range is 0V-VDD; the first and second NMOS tubes work in the high voltage domain. The bias current I1 can be replaced by an ordinary resistor, preferably a constant current source composed of PMOS.

[0032] The voltage boost circuit in the feedback regulation circuit can be implemented in many ways, such as a plurality of PMOS tubes connected in sequence with gates and drains, such as Figure 5 As shown, the output of the low voltage amplifier is connected to the gate of the first PMOS tube, the source of the last PMOS tube is connected to the source of the first NMOS tube, and the specific number of PMOS tubes is set according to actual needs. Figure 5 There are 3 in the figure; it can also be composed of PMOS tubes and voltage regulator diodes, such as Figure 6 As shown, the output of the low voltage amplifier is connected to the gate of the PMOS tube, and the source of the PMOS tube is connected to the source of the first NMOS tube via the voltage stabilizing diode.

[0033] Example 2

[0034] Different from Embodiment 1, the feedback signal is taken from the regulating branch, the source of the first NMOS tube NM1 is connected to ground via the first adjusting resistor R1 and the second adjusting resistor R2 in sequence, the positive and negative input terminals of the low voltage amplifier are connected to the reference voltage VREF and the second adjusting resistor voltage respectively; the source of the second NMOS tube NM2 is connected to ground via the grounding resistor R3, as shown in FIG. Figure 3 shown.

[0035] This embodiment is suitable for applications where the output LDO_OUT is not required to be very precise. LDO_OUT is not in the loop, so it is easier to ensure the stability of the circuit. However, the LDO_OUT voltage will change slightly with changes in load current and ambient temperature.

[0036] Example 3

[0037] Different from Embodiment 1, the feedback signal is taken from the regulating branch, the gate of the first NMOS tube NM1 is connected to ground via the first adjusting resistor R1 and the second adjusting resistor R2 in sequence, the positive and negative input terminals of the low voltage amplifier are connected to the reference voltage VREF and the second adjusting resistor voltage respectively; the source of the second NMOS tube NM2 is connected to ground via the grounding resistor R3, as shown in FIG. Figure 4 shown.

[0038] This embodiment is also applicable to applications where the output LDO_OUT is not required to be very precise. LDO_OUT is not in the loop, so it is easier to ensure the stability of the circuit. However, the LDO_OUT voltage will change slightly with changes in load current and ambient temperature.

[0039] Example 4

[0040] When BOOST is just started, if the input voltage VDD is very low (less than 2V), the output voltage HVDD is also very low. If the voltage drop from HVDD to LDO_OUT in the voltage stabilization circuit is too large, the chip may not start.

[0041] To ensure that the chip can still start normally when the input voltage VDD is very low, it is necessary to reduce the voltage drop from HVDD to LDO_OUT in the voltage stabilization circuit in a timely manner.

[0042] To this end, in this embodiment, based on the embodiment 1, a voltage-limiting PMOS transistor PM1 is connected between the output voltage HVDD and the voltage stabilizing circuit output LDO_OUT, the output voltage HVDD is connected to the drain of the voltage-limiting PMOS transistor PM1, the source of the voltage-limiting PMOS transistor PM1 is connected to the voltage stabilizing circuit output LDO_OUT, and the gate thereof is connected to the control signal SCT, such as Figure 7 shown.

[0043] The internal circuit of the chip detects the output voltage HVDD. When the voltage value is low, the control signal SCT outputs a low level to turn on the voltage-limiting PMOS tube PM1. At this time, the LDO_OUT output is equal to the HVDD voltage to ensure that the BOOST switch tube can be turned on normally. When the output voltage HVDD rises to a predetermined voltage value, the control signal SCT outputs a high level to turn off the high-voltage PMOS tube PM1, and the loop determines the output of the voltage stabilization circuit LDO_OUT.

[0044] Of course, the voltage limiting PMOS transistor PM1 can also be applied in the same way as the voltage stabilizing circuit disclosed in Embodiment 2 and Embodiment 3, respectively. Figure 8 , Fig. 9 As shown, no further description is given here.

[0045] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field and related fields without creative work should fall within the scope of protection of the present invention.

Claims

1. A BOOST boost circuit with low input voltage and strong driving capability, input voltage VDD, output voltage HVDD, characterized in that: A voltage stabilizing circuit and a driving circuit are provided inside the chip, the output voltage HVDD is connected to the voltage stabilizing circuit, the voltage stabilizing circuit is connected to the driving circuit, the driving circuit is connected to the gate of the switch tube, a diode is forwardly connected between the drain of the switch tube and the output voltage HVDD, the source of the switch tube is grounded, and the input voltage VDD is connected to the drain of the switch tube through an inductor; The voltage stabilizing circuit is composed of a regulating branch and an output branch. The regulating branch mainly includes a first NMOS tube and a feedback regulating circuit connected to the source of the first NMOS tube. The output branch mainly includes a second NMOS tube. The output LDO_OUT of the voltage stabilizing circuit is taken from the source of the second NMOS tube. The gate of the first NMOS tube is connected to the gate of the second NMOS tube, and the output voltage HVDD is connected to the drain and gate of the first NMOS tube via a bias current source; the feedback regulation circuit mainly includes a low-voltage amplifier and a voltage boosting circuit, the positive and negative input terminals of the low-voltage amplifier are respectively connected to the reference voltage VREF and the feedback signal, and the output thereof is connected to the source of the first NMOS tube via the voltage boosting circuit; A voltage limiting PMOS tube is connected between the output voltage HVDD and the voltage stabilizing circuit output LDO_OUT, the output voltage HVDD is connected to the drain of the voltage limiting PMOS tube, the source of the voltage limiting PMOS tube is connected to the voltage stabilizing circuit output LDO_OUT, and the gate thereof is connected to the control signal SCT.

2. The BOOST boost circuit according to claim 1, characterized in that: The feedback signal is taken from the output branch, the source of the second NMOS tube is grounded via the first adjustment resistor and the second adjustment resistor in sequence, and the positive and negative input terminals of the low-voltage amplifier are respectively connected to the reference voltage VREF and the second adjustment resistor voltage.

3. The BOOST boost circuit according to claim 1, characterized in that: The feedback signal is taken from the regulating branch, the source of the first NMOS tube is grounded via the first adjustment resistor and the second adjustment resistor in sequence, the positive and negative input terminals of the low-voltage amplifier are respectively connected to the reference voltage VREF and the second adjustment resistor voltage; the source of the second NMOS tube is grounded via the grounding resistor.

4. The BOOST boost circuit according to claim 1, characterized in that: The feedback signal is taken from the regulating branch, the gate of the first NMOS tube is grounded via the first adjustment resistor and the second adjustment resistor in sequence, the positive and negative input terminals of the low-voltage amplifier are respectively connected to the reference voltage VREF and the second adjustment resistor voltage; the source of the second NMOS tube is grounded via the grounding resistor.

5. The BOOST boost circuit according to claim 1, characterized in that: The voltage boosting circuit is composed of a plurality of PMOS tubes whose gates and drains are connected in sequence, the output of the low voltage amplifier is connected to the gate of the first PMOS tube, and the source of the last PMOS tube is connected to the source of the first NMOS tube.

6. The BOOST boost circuit according to claim 1, characterized in that: The voltage boosting circuit is composed of a PMOS tube and a voltage regulator diode. The output of the low voltage amplifier is connected to the gate of the PMOS tube, and the source of the PMOS tube is connected to the source of the first NMOS tube via the voltage regulator diode.

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