Imaging element, imaging element control method, and electronic device

Abstract

The present invention provides an imaging element capable of generating an image with reduced noise. The present invention provides an imaging element, comprising: a signal output section configured to output a predetermined signal; a switch section configured to output an output from the signal output section or an output from a pixel array in a switching manner, the pixel array being configured to output a pixel signal by photoelectric conversion; and a signal processing section configured to perform signal processing using the output from the switch section.

Description

Technical Field

[0001] The present disclosure relates to an imaging element, a control method of the imaging element, and an electronic device. Background Art

[0002] A conventional CMOS image sensor compares an analog pixel signal with a reference signal having a linearly decreasing ramp waveform through a comparator, and counts the time required for the reference signal to fall below the pixel signal to perform AD (analog-to-digital) conversion on the pixel signal (see, for example, Patent Document 1).

[0003] [Citation list]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. JP 2009-124513A Summary of the invention

[0006] Technical issues

[0007] The fixed pattern noise phenomenon is caused by variations in analog circuits used in comparators and the like of CMOS image sensors. In particular, when the power supply voltage of the comparator is reduced in order to reduce the power consumption of the CMOS image sensor, vertical stripe noise is more likely to occur.

[0008] Therefore, the present disclosure proposes a novel and improved imaging element, a control method of the imaging element, and an electronic device capable of generating an image with reduced noise.

[0009] Solutions to the problem

[0010] According to the present disclosure, an imaging element is provided. The imaging element includes: a pixel array including a plurality of pixels, each pixel being configured to output a pixel signal through photoelectric conversion; a signal output unit configured to output a predetermined signal; a switch unit configured to output an output from the signal output unit or an output based on the pixel signal in a switching manner; and an AD conversion processing unit configured to perform AD conversion using the output from the switch unit.

[0011] In addition, according to the present disclosure, there is provided an imaging element control method for controlling an imaging element. The imaging element includes: a pixel array including a plurality of pixels, each pixel being configured to output a pixel signal by photoelectric conversion; a signal output unit configured to output a predetermined signal; a switch unit configured to output an output from the signal output unit or an output based on the pixel signal in a switching manner; and an AD conversion processing unit configured to perform AD conversion using an output from the switch unit. The method includes: performing control for switching the switch unit so that when a predetermined condition is met, the output from the signal output unit is output to the AD conversion processing unit.

[0012] In addition, according to the present disclosure, an electronic device is provided, including: an imaging element; and a processing unit, the processing unit being configured to process a signal output from the imaging element, wherein the imaging element includes: a pixel array, the pixel array including a plurality of pixels, each pixel being configured to output a pixel signal through photoelectric conversion; a signal output unit, the signal output unit being configured to output a predetermined signal; a switching unit, the switching unit being configured to output an output from the signal output unit or an output based on the pixel signal in a switching manner; and an AD conversion processing unit, the AD conversion processing unit being configured to perform AD conversion using the output from the switching unit.

[0013] Advantageous Effects of the Invention

[0014] As described above, the present disclosure can provide a novel and improved imaging element, a control method of the imaging element, and an electronic device capable of generating an image with reduced noise.

[0015] Note that the effects of the present disclosure are not necessarily limited to the above-described effects. In addition to or instead of the above-described effects, the present disclosure can achieve any effects described in this specification or other effects that can be grasped from this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 : is an explanatory diagram showing a configuration example of a CMOS image sensor according to an embodiment of the present disclosure.

[0017] Figure 2A is a circuit diagram showing a configuration example of a pixel included in a pixel portion.

[0018] Figure 2B It is an explanatory diagram showing a configuration example of a column readout circuit.

[0019] Figure 3A It is shown Figure 1 A circuit diagram of an example of a comparator configuration.

[0020] Figure 3BIt is shown Figure 3A Diagram of the operating point of the comparator.

[0021] Figure 4 is a timing diagram illustrating the operation of the comparator.

[0022] Figure 5 is a circuit diagram showing a configuration example of a comparator.

[0023] Figure 6 : is an explanatory diagram showing a functional configuration example of a signal processing circuit according to an embodiment of the present disclosure.

[0024] Fig. 7A is a flowchart showing an operation example of the CMOS image sensor according to the embodiment.

[0025] Figure 7B is a flowchart showing an operation example of the CMOS image sensor according to the embodiment.

[0026] Figure 8 is an explanatory diagram showing an example of correction processing by a signal processing circuit.

[0027] Fig. 9 are explanatory diagrams showing the operation of the CMOS image sensor according to the embodiment in chronological order.

[0028] Fig.10 It is an explanatory diagram showing an image example of the correction process at the start-up and the correction process for each V.

[0029] Fig.11 is a circuit diagram showing a configuration example of a comparator.

[0030] Fig.12 is a circuit diagram showing a configuration example of a comparator.

[0031] Fig.13 : is an explanatory diagram showing a configuration example of a SAR ADC included in a column readout circuit.

[0032] Fig.14 : is an explanatory diagram showing a configuration example of a SAR ADC included in a column readout circuit.

[0033] Fig.15 is an explanatory diagram showing a configuration example of a CMOS image sensor according to the embodiment.

[0034] Fig.16 This is a diagram showing an overview of a configuration example of a stacked solid-state imaging device to which the technology of the present disclosure can be applied.

[0035] Fig.17 It is a cross-sectional view showing a first configuration example of a stacked solid-state imaging device.

[0036] Fig.18 It is a cross-sectional view showing a second configuration example of the stacked solid-state imaging device.

[0037] Fig.19 It is a cross-sectional view showing a third configuration example of the stacked solid-state imaging device.

[0038] Fig. 20 This is a cross-sectional view showing another configuration example of a stacked solid-state imaging device to which the technology of the present disclosure can be applied.

[0039] Fig.21 It is an explanatory diagram showing a configuration example of an electronic device. DETAILED DESCRIPTION

[0040] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and the accompanying drawings, elements having substantially the same functional configuration are denoted by the same reference numerals, thereby omitting repeated descriptions.

[0041] Note that the description will be given in the following order.

[0042] 1. Implementation of the present disclosure

[0043] 1.1 Example of CMOS image sensor configuration

[0044] 1.2 CMOS Image Sensor Operation Example

[0045] 2. Configuration Example of a Stacked Solid-State Imaging Device

[0046] 3. Summary

[0047] <1. Implementation of the present disclosure>

[0048] [1.1. Example of CMOS image sensor configuration]

[0049] First, a configuration example of a CMOS image sensor according to an embodiment of the present disclosure will be described. Figure 1 1 is an explanatory diagram showing a configuration example of a CMOS image sensor according to an embodiment of the present disclosure. Figure 1 A configuration example of a CMOS image sensor according to an embodiment of the present disclosure will be described.

[0050] like Figure 1 As shown, the CMOS image sensor 100 according to the embodiment of the present disclosure includes a pixel portion 101, a vertical scanning circuit 102, a column readout circuit 103, a signal source 104, a switch portion 105, a reference voltage generating portion 106, a signal processing circuit 107, and an event control portion 108.

[0051] The pixel unit 101 includes unit pixels (hereinafter, referred to as pixels) arranged in a matrix, each of which includes a photoelectric conversion element that photoelectrically converts incident light into an amount of charge corresponding to the amount of incident light. Figure 2A The specific circuit structure of the unit pixel is described. In addition, the pixel unit 101 includes a pixel drive line 109 extending in the left-right direction of the figure (pixel arrangement direction / horizontal direction of the pixel row) for each row of the matrix-shaped pixel array, and a vertical signal line 110 extending in the up-down direction of the figure (pixel arrangement direction / vertical direction of the pixel column) for each column. One end of each pixel drive line 109 is connected to the output end of the vertical scanning circuit 102 corresponding to each row. Note that although one pixel drive line 109 is shown for each pixel row, more than two pixel drive lines 109 may be provided for each pixel row.

[0052] The vertical scanning circuit 102 includes a shift register and an address recorder. Although a specific configuration is not shown in this embodiment, the vertical scanning circuit 102 also includes a readout scanning system and a sweep-out scanning system.

[0053] The readout scanning system sequentially performs selective scanning in units of rows from the unit pixels from which the signals are to be read out. On the other hand, the sweep-out scanning system performs a sweep-out scanning on the readout row on which the readout scanning is performed by the readout scanning system, so as to sweep out (reset) unnecessary charges of the photoelectric conversion elements of the unit pixels in the readout row at a time of the shutter speed before the readout scanning. The so-called electronic shutter operation is performed by sweeping out (resetting) unnecessary charges by the sweep-out scanning system. Here, the electronic shutter operation refers to an operation of discharging the photoelectric charges of the photoelectric conversion element and starting a new exposure (starting the accumulation of photoelectric charges). The signal read out by the readout operation of the readout scanning system corresponds to the amount of incident light after the immediately preceding readout operation or the immediately preceding electronic shutter operation. In addition, the period from the readout moment of the immediately preceding readout operation or the sweep-out moment of the immediately preceding electronic shutter operation to the readout moment of the current readout operation corresponds to the accumulation time (exposure time) of the photoelectric charges in the unit pixel.

[0054] The pixel signal VSL output from each unit pixel in the pixel row selectively scanned by the vertical scanning circuit 102 is supplied to the column readout circuit 103 via the vertical signal line 110 of each corresponding column.

[0055] The column readout circuit 103 includes a comparator, a counter, and a latch. A comparator, a counter, and a latch are provided for each column or multiple columns of the pixel unit 101 to form an ADC. That is, in the column readout circuit 103, an ADC is provided for each column or multiple columns of the pixel unit 101. A specific configuration example of the comparator will be described below. In addition, a predetermined reference voltage is applied to the comparator of the column readout circuit 103. Figure 2B A configuration example of the column readout circuit 103 will be described.

[0056] The signal source 104 is an example of a signal output section of the present disclosure, and supplies a signal to the column readout circuit 103 through the switch section 105. When the CMOS image sensor 100 performs a process for correcting the characteristics of the column readout circuit 103 (hereinafter, simply referred to as a correction process), the signal from the signal source 104 is supplied to the column readout circuit 103. The signal source 104 may be configured to output a signal of an arbitrary voltage, and may include a plurality of signal sources each of which outputs a signal of a predetermined voltage.

[0057] The switch section 105 performs a switching operation of supplying a signal from the pixel section 101 or a signal from the signal source 104 to the column readout circuit 103. More specifically, at the time of imaging, the switch section 105 establishes a connection for supplying a signal from the pixel section 101 to the column readout circuit 103, and at the time of correction processing, establishes a connection for supplying a signal from the signal source 104 to the column readout circuit 103. The switching of the switch section 105 can be controlled by the event control section 108. The switch section 105 includes a switch element provided for each vertical signal line 110. The switching of each switch element is controlled by the event control section 108.

[0058] The signal processing circuit 107 performs predetermined signal processing on the digital pixel signal to generate two-dimensional image data. For example, the signal processing circuit 107 performs correction of vertical line defects or point defects or signal clamping, and performs digital signal processing such as parallel-serial conversion, compression, encoding, summation, averaging, and intermittent operation. The signal processing circuit 107 outputs the generated image data to the device of the subsequent stage.

[0059] In the present embodiment, the signal processing circuit 107 performs correction processing for correcting the analog characteristics of the column readout circuit 103. The signal processing circuit 107 can reduce noise caused by the analog characteristics of the column readout circuit 103 by performing the correction processing.

[0060] The event control section 108 detects the occurrence of a predetermined event, and controls the operations of the vertical scanning circuit 102, the switch section 105, and the signal processing circuit 107 according to the detection. Therefore, the event control section 108 is an example of a control section of the present disclosure. For example, in the case where it is predetermined to perform correction processing after a predetermined temperature change is detected, when a predetermined temperature change is detected by a temperature sensor (not shown), the event control section 108 switches the switch section 105 to connect the signal source 104 to the column readout circuit 103 to perform the correction processing. In addition, for example, in the case where it is predetermined to perform correction processing after a predetermined voltage change is detected inside the CMOS image sensor 100, when a predetermined voltage change is detected, the event control section 108 switches the switch section 105 to connect the signal source 104 to the column readout circuit 103 to perform the correction processing.

[0061] The driving of the vertical scanning circuit 102 , the column readout circuit 103 , the signal source 104 , the switch section 105 , the reference voltage generating section 106 , and the signal processing circuit 107 can be controlled according to a timing signal from a timing control circuit (not shown).

[0062] <Pixel Configuration Example>

[0063] Figure 2A 1 is a circuit diagram showing a configuration example of a pixel 150 included in the pixel portion 101 .

[0064] For example, the pixel 150 includes a photodiode 151 as a photoelectric conversion element, and includes four transistors as active elements of the photodiode 151 : a transfer transistor 152 ; an amplification transistor 154 ; a selection transistor 155 ; and a reset transistor 156 .

[0065] The photodiode 151 photoelectrically converts incident light into electric charges (electrons in the present embodiment) of an amount corresponding to the amount of incident light.

[0066] The transfer transistor 152 is connected between the photodiode 151 and a floating diffusion (FD) 153. When the transfer transistor 152 is turned on by a drive signal TX supplied from the vertical scanning circuit 102, the transfer transistor 152 transfers the charge accumulated on the photodiode 151 to the FD 153.

[0067] The gate of the amplifier transistor 154 is connected to the FD 153. The amplifier transistor 154 is connected to the vertical signal line 110 via the selection transistor 155 to constitute a source follower with the constant current source 157 outside the pixel portion 101. When the selection transistor 155 is turned on by the drive signal SEL supplied from the vertical scanning circuit 102, the amplifier transistor 154 amplifies the potential of the FD 153, and outputs a pixel signal indicating a voltage corresponding to the amplified potential to the vertical signal line 110. Thus, the pixel signal output from each pixel 150 is supplied to each comparator of the column readout circuit 103 via the vertical signal line 110.

[0068] The reset transistor 156 is connected between the power supply VDD and the FD 153. When the reset transistor 156 is turned on by the drive signal RST supplied from the vertical scanning circuit 102, the potential of the FD 153 is reset to the potential of the power supply VDD.

[0069] <Configuration Example of Column Readout Circuit>

[0070] Figure 2B 3 is an explanatory diagram showing a configuration example of the column readout circuit 103. The column readout circuit 103 includes a comparator 200, a counter 300, and a switch 310.

[0071] The comparator 200 is a circuit that compares the output signal from the vertical signal line 110 and the ramp signal from the signal source 104. The ramp signal from the signal source 104 has a waveform whose value changes with time and has a constant slope according to a clock pulse from a PLL (not shown). The comparator 200 outputs a signal for turning off the switch 310 at the inversion timing of the high / low relationship between the output signal from the vertical signal line 110 and the ramp signal from the signal source 104.

[0072] The counter 300 is a circuit that counts up according to the clock pulse from the PLL. The counter 300 counts up until the switch 310 is turned off to stop the supply of the clock pulse from the PLL. In other words, the counter 300 counts up until the inversion moment of the high / low relationship between the output signal from the vertical signal line 110 and the ramp signal from the signal source 104. Therefore, the value of the counter 300 corresponds to the digital value of the output signal from the vertical signal line 110.

[0073] <Comparator Configuration Example>

[0074] Figure 3A It shows Figure 1 A circuit diagram of a configuration example of a comparator 200 to which the comparator 121 is applicable.

[0075] The comparator 200 includes a differential amplifier 201, an output amplifier 221, capacitors C11 to C13, C42, a switch SW11, and a switch SW12. The differential amplifier 201 includes a PMOS transistor PT11, a PMOS transistor PT12, and NMOS transistors NT11 to NT13.

[0076] The source of the PMOS transistor PT11 and the source of the PMOS transistor PT12 are connected to the power supply VDD1. The drain of the PMOS transistor PT11 is connected to the gate of the PMOS transistor PT11 and the drain of the NMOS transistor NT11. The drain of the PMOS transistor PT12 is connected to the drain of the NMOS transistor NT12 and the output terminal T15 of the output signal OUT1. The source of the NMOS transistor NT11 is connected to the source of the NMOS transistor NT12 and the drain of the NMOS transistor NT13. The source of the NMOS transistor NT13 is connected to the ground GND1.

[0077] The PMOS transistor PT11 and the PMOS transistor PT12 constitute a current mirror circuit. In addition, the NMOS transistors NT11 to NT13 constitute a differential comparison section. More specifically, the NMOS transistor NT13 operates as a current source by the bias voltage VG input from the outside via the input terminal T14, and the NMOS transistor NT11 and the NMOS transistor NT12 operate as differential transistors.

[0078] The capacitor C11 is connected between the input terminal T11 of the pixel signal VSL or the signal source 104 capable of outputting an arbitrary voltage and the gate of the NMOS transistor NT11 , and serves as an input capacitance for the pixel signal VSL.

[0079] The capacitor C12 is connected between the input terminal T12 of the reference signal RAMP and the gate of the NMOS transistor NT11 , and serves as an input capacitance for the reference signal RAMP.

[0080] The switch SW11 is connected between the drain and the gate of the NMOS transistor NT11 , and is turned on or off according to the drive signal AZSW1 input via the input terminal T13 .

[0081] The switch SW12 is connected between the drain and the gate of the NMOS transistor NT12 , and is turned on or off according to the drive signal AZSW1 input via the input terminal T13 .

[0082] The capacitor C13 is connected between the gate of the NMOS transistor NT12 and the ground GND1.

[0083] Note that, hereinafter, the connection point between the capacitor C11, the capacitor C12, and the switch SW11 is referred to as a node HiZ. Furthermore, hereinafter, the connection point between the gate of the NMOS transistor NT12, the capacitor C13, and the switch SW12 is referred to as a node VSH.

[0084] The output amplifier 221 is used as a buffer, which buffers the output signal OUT1 of the differential amplifier 201 to output the output signal OUT1 of an appropriate level to the circuit of the subsequent stage. More specifically, the output amplifier 221 amplifies the output signal OUT1 of the differential amplifier 201 with a predetermined gain, and outputs the output signal OUT2 obtained from the output terminal T42.

[0085] The output amplifier 221 includes a PMOS transistor PT41 , an NMOS transistor NT41 , a capacitor C41 , and a switch SW41 .

[0086] The source of the PMOS transistor PT41 is connected to the power supply VDD1, the gate thereof is connected to the output of the differential amplifier 201, and the drain thereof is connected to the drain of the NMOS transistor NT41 and the output terminal T42. The source of the NMOS transistor NT41 is connected to the ground GND1, and the gate thereof is connected to the ground GND1 via the capacitor C41. The switch SW41 is connected between the drain and the gate of the NMOS transistor NT41, and is turned on or off according to the drive signal AZSW2 input from the timing control circuit via the input terminal T41.

[0087] The capacitor C42 is connected between the power supply VDD1 and the drain of the PMOS transistor PT12 (the output of the differential amplifier 201). The capacitor C42 removes the high frequency component of the output signal OUT1 of the differential amplifier 201.

[0088] <Comparator Operation>

[0089] Next, we will refer to Figure 4 The timing diagram illustrates the operation of the comparator 200. Figure 4 The timing chart of the drive signal AZSW1 , the drive signal AZSW2 , the reference signal RAMP, the pixel signal VSL, the node VSH, the node HiZ, the output signal OUT1 , and the output signal OUT2 is shown.

[0090] At time t1, the drive signal AZSW1 is set to a high level. In addition, the switch SW11 and the switch SW12 are turned on, so that the drain and gate of the NMOS transistor NT11 are connected, and the drain and gate of the NMOS transistor NT12 are connected. In addition, the reference signal RAMP is set to a predetermined reset level. In addition, the FD 153 of the pixel 150 to be read out is reset, and the pixel signal VSL is set to a reset level.

[0091] Therefore, the auto-zero operation of the differential amplifier 201 is started. That is, the drain and gate of the NMOS transistor NT11 and the drain and gate of the NMOS transistor NT12 converge to a predetermined same voltage (hereinafter, referred to as a reference voltage). Therefore, the voltage of the node HiZ and the voltage of the node VSH are set as the reference voltage.

[0092] In addition, the drive signal AZSW2 is set to a high level. In addition, the switch SW41 is turned on, so that the drain and gate of the PMOS transistor PT41 are connected.

[0093] Thus, the auto-zero operation starts of the output amplifier 221. That is, the voltage of the capacitor C41 is equal to the drain voltage of the PMOS transistor PT41, and electric charge is accumulated on the capacitor C41.

[0094] At time t2, the drive signal AZSW2 is set to a low level. In addition, the switch SW41 is turned off, thereby completing the auto-zero operation of the output amplifier 221. Note that after the switch SW41 is turned off, the voltage of the capacitor C41 is maintained and applied to the gate of the NMOS transistor NT41. Therefore, the NMOS transistor NT41 acts as a current source that flows with a current substantially equal to the current that flows when the switch SW41 is turned on.

[0095] Next, at time t3, the drive signal AZSW1 is set to a low level, and the switch SW11 and the switch SW12 are turned off. Thus, the auto-zero operation of the differential amplifier 201 is completed. Since the pixel signal VSL and the reference signal RAMP remain unchanged, the voltage of the node HiZ is maintained at the reference voltage. In addition, the voltage of the node VSH is maintained at the reference voltage by the charge accumulated on the capacitor C13.

[0096] At time t4, the voltage of the reference signal RAMP drops from the reset level by a predetermined value. Therefore, the voltage of the node HiZ drops and falls below the voltage of the node VSH (reference voltage), and the output signal OUT1 of the differential amplifier 201 changes to a low level.

[0097] At time t5, the reference signal RAMP starts to increase linearly. Accordingly, the voltage of the node HiZ also increases linearly. In addition, the counter 122 starts counting.

[0098] Then, when the voltage of the node HiZ exceeds the voltage (reference voltage) of the node VSH, the output signal OUT1 of the differential amplifier 201 is inverted to a high level. In addition, when the output signal OUT1 is inverted to a high level, the count value of the counter 122 at that point is held by the latch 123 as the value of the pixel signal VSL of the P phase (reset level).

[0099] At time t6, the voltage of the reference signal RAMP is set to the reset voltage. In addition, the transfer transistor 152 of the pixel 150 is turned on, so that the charge accumulated on the photodiode 151 during the exposure period is transferred to the FD 153, and the pixel signal VSL is set to the signal level. Therefore, the voltage of the node HiZ drops by a value corresponding to the signal level and falls below the voltage (reference voltage) of the node VSH, and the output signal OUT1 of the differential amplifier 201 is inverted to a low level.

[0100] At time t7, similarly to time t4, the voltage of the reference signal RAMP drops from the reset level by a predetermined value, and thus the voltage of the node HiZ further drops.

[0101] At time t8, similar to time t5, the reference signal RAMP starts to increase linearly. Accordingly, the voltage of the node HiZ also increases linearly. In addition, the counter 122 starts counting.

[0102] Then, when the voltage of the node HiZ exceeds the voltage (reference voltage) of the node VSH, the output signal OUT1 of the differential amplifier 201 is inverted to a high level. In addition, the count value of the counter 122 at the time point when the output signal OUT1 is inverted to a high level is held by the latch 123 as the value of the pixel signal VSL of the D phase (signal level). In addition, the latch 123 acquires the difference between the pixel signal VSL of the D phase and the pixel signal VSL of the P phase read out between time t5 and time t6 to perform CDS. In this way, AD conversion of the pixel signal VSL is performed.

[0103] Furthermore, when the output signal OUT1 of the differential amplifier 201 becomes a high level, the PMOS transistor PT41 of the output amplifier 221 is turned off, and the output signal OUT2 becomes a low level. On the other hand, when the output signal OUT1 of the differential amplifier 201 becomes a low level, the PMOS transistor PT41 of the output amplifier 221 is turned on, and the output signal OUT2 becomes a high level. That is, the output amplifier 221 outputs the output signal OUT2 at an inverted level of the output signal OUT1 of the differential amplifier 201.

[0104] Then, after time t9, the same operation as from time t1 to time t8 is repeatedly performed.

[0105] Therefore, the power consumption of the column readout circuit 103 can be reduced by lowering the voltage of the power supply VDD1 , thereby reducing the power consumption of the CMOS image sensor 100 .

[0106] Figure 5 The figure above shows an example of the configuration of a comparator.

[0107] exist Figure 5In the comparator, a reference signal RAMP having a linearly falling ramp waveform is input to one input (gate of NMOS transistor NT11) of the differential amplifier 201 via capacitor C21. A pixel signal VSL is input to the other input (gate of NMOS transistor NT12) of the differential amplifier 201 via capacitor C22.

[0108] In addition, if Figure 5 As shown in the following figure, the reference signal RAMP is compared with the pixel signal VSL, and the comparison result is output as the output signal OUT. At this time, the input voltage of the differential amplifier 201 when the output signal OUT is inverted (the voltage of the reference signal RAMP and the voltage of the pixel signal VSL) changes according to the voltage of the pixel signal VSL. Therefore, for example, when the voltage of the power supply VDD for driving the comparator drops, the input voltage of the differential amplifier 201 when the output signal OUT is inverted may exceed the input dynamic range of the comparator, which may make it impossible to obtain sufficient linearity of AD conversion.

[0109] On the other hand, in the comparator 200 , as described above, the comparison result between the voltage of the signal obtained by adding the pixel signal VSL and the reference signal RAMP via the input capacitor (the voltage of the node HiZ) and the voltage of the node VSH (the reference voltage) is output as the output signal OUT1 . Figure 3B It is shown Figure 3A The effect of the circuit shown in the figure is explained. Figure 3A In the comparator 200 shown in FIG. 1 , the input voltage (the voltage of the node HiZ and the voltage of the node VSH) of the differential amplifier 201 does not change when the output signal OUT1 is inverted, but remains constant, as shown in FIG. Figure 3B shown.

[0110] In addition, in the CMOS image sensor 100, the reference signal RAMP is Figure 5 The reference signal RAMP of the comparator changes in the opposite direction to the reference signal RAMP of the comparator, and changes linearly in the opposite direction to the pixel signal VSL. Here, changing in the opposite direction to the pixel signal VSL means changing in the opposite direction to the direction in which the pixel signal VSL changes as the signal component becomes larger. For example, in this example, the pixel signal VSL changes in the negative direction as the signal component becomes larger, and on the other hand, the reference signal RAMP changes in the positive direction opposite thereto. Therefore, the voltage of the node HiZ (the input voltage of the differential amplifier 201) is proportional to the pixel signal VSL and Figure 5 The voltage corresponding to the difference between the reference signal RAMP, and its amplitude is small.

[0111] Since the input voltage of the differential amplifier 201 when the output signal OUT1 is inverted is constant and the amplitude of the input voltage is small in this way, the input dynamic range of the differential amplifier 201 can be narrowed.

[0112] Therefore, the voltage of the power supply VDD1 for driving the comparator 200 can be reduced to below Figure 5 Therefore, the power consumption of the column readout circuit 103 can be reduced, thereby reducing the power consumption of the CMOS image sensor 100.

[0113] On the other hand, variations in analog circuits used in comparators and the like of CMOS image sensors cause fixed pattern noise phenomena. In particular, when the power supply voltage of the comparator is reduced to reduce power consumption of the CMOS image sensor, vertical stripe noise is more likely to occur.

[0114] Therefore, the CMOS image sensor 100 according to the present embodiment performs a correction process for correcting the analog characteristics of the column readout circuit 103 by the signal processing circuit 107. The CMOS image sensor 100 according to the present embodiment can generate an image with reduced noise caused by the analog characteristics of the column readout circuit 103 by performing the correction process of the signal processing circuit 107.

[0115] Specifically, during the calibration process, the switch section 105 switches to supply the signal from the signal source 104 to each comparator 200. Figure 3A In the case of the DAC shown in FIG. 1 , a signal set at an arbitrary voltage is supplied to each comparator 200. Similarly, in Figure 5 In the illustrated comparator, the switch section 105 switches to supply a signal from the signal source 104 to each comparator during correction processing. Operating the switch section 105 in this manner enables the CMOS image sensor 100 according to the present embodiment to correct the analog characteristics of the column readout circuit 103.

[0116] Figure 6 1 is an explanatory diagram showing an example of the functional configuration of the signal processing circuit 107 according to an embodiment of the present disclosure. Figure 6 A functional configuration example of the signal processing circuit 107 according to an embodiment of the present disclosure will be described.

[0117] like Figure 6 As shown, the signal processing circuit 107 according to the embodiment of the present disclosure includes a gain error measuring section 131 , a correction value calculating section 132 , a storage section 133 , and a correcting section 134 .

[0118] At the time of the calibration process, the gain error measuring section 131 measures the gain error for the output of each ADC included in the column readout circuit 103. Due to the variation in the characteristics of the analog circuit, the offset and gain between the outputs of the respective ADCs are different. Therefore, the gain error measuring section 131 measures the variation in the offset and gain that are different between the outputs of the respective ADCs. That is, when the signal from the signal source 104 is converted into a digital signal by the column readout circuit 103, the gain error measuring section 131 measures the variation in the offset and gain.

[0119] Based on the error of the gain measured by the gain error measuring section 131, the correction value calculating section 132 calculates a correction value for correcting the error of the gain. A specific correction value calculation example will be described below. The storage section 133 stores the correction value calculated by the correction value calculating section 132. The correction section 134 corrects the signal output from the column readout circuit 103 using the correction value stored in the storage section 133 at the time of imaging.

[0120] The signal processing circuit 107 having such a configuration can reduce noise caused by the analog characteristics of the column readout circuit 103. Therefore, the CMOS image sensor 100 according to the embodiment of the present disclosure can generate an image with reduced noise caused by the analog characteristics of the column readout circuit 103 by performing correction processing of the signal processing circuit 107.

[0121] The CMOS image sensor 100 according to the embodiment of the present disclosure can perform correction processing by the signal processing circuit 107 in response to the detection of the occurrence of a predetermined event. Therefore, the signal processing circuit 107 can hold information about the operating environment of the CMOS image sensor 100 such as voltage values ​​and temperature values ​​at the point in time when the correction processing is performed.

[0122] [1.2. Example of CMOS image sensor operation]

[0123] Next, an operation example of the CMOS image sensor 100 according to the embodiment of the present disclosure will be described. Fig. 7A and Figure 7B : is a flowchart showing an operation example of the CMOS image sensor 100 according to an embodiment of the present disclosure.

[0124] When the power is turned on, the CMOS image sensor 100 performs a predetermined initial setting (step S101) and enters a standby state (step S102). When performing a correction process, the CMOS image sensor 100 first performs a correction setting (step S103). For example, the correction setting may be a setting of a voltage of a signal output from the signal source 104 or a selection of a signal source to be used when the signal source 104 includes a plurality of signal sources.

[0125] After the correction setting is performed, the CMOS image sensor 100 performs AD conversion of the correction data output from the signal source 104 through the column readout circuit 103 (step S104). Then, the CMOS image sensor 100 performs calculation of the gain correction coefficient using the digital signal output from the column readout circuit 103 through the correction value calculation unit 132 (step S105). In step S105, the correction value calculation unit 132 can calculate the offset correction coefficient for offset correction. Then, the CMOS image sensor 100 stores the calculated correction coefficient in the storage unit 133 (step S106). After the correction coefficient is stored in the storage unit 133, the CMOS image sensor 100 determines whether the determination of correction re-execution at the time of imaging (described below) has been performed (step S107). When the determination of correction re-execution is not performed (step S107, no), the CMOS image sensor 100 enters a standby state (step S108). In this standby state, the switch unit 105 performs switching to output the output from the pixel unit 101 to the column readout circuit 103. On the other hand, when it is determined that the correction re-execution has been performed (step S107 , Yes), the CMOS image sensor 100 is not in the standby state but proceeds to the next process.

[0126] Here, an example of correction processing performed by the signal processing circuit 107 will be described. Figure 8 is an explanatory diagram showing an example of correction processing performed by the signal processing circuit 107 . Figure 8 The correction process performed by the signal processing circuit 107 when correcting the outputs of four ADCs is shown.

[0127] like Figure 8 As shown in the upper left figure of , due to the variation in the characteristics of the analog circuit, the change in the digital value relative to the amount of light is different between all ADCs. The fact that the change in the digital value relative to the amount of light is different between all ADCs causes vertical stripe noise.

[0128] Therefore, the signal processing circuit 107 performs correction processing so that the variation of the digital value with respect to the light amount is the same among all ADCs. Figure 8 As shown in the upper right figure of , when the light amount is zero, the signal processing circuit 107 first makes the outputs of all ADCs have the same digital value (same offset value). Then, as shown in Figure 8 As shown in the lower left figure of , the signal processing circuit 107 performs gain correction on the outputs of all ADCs, that is, a process for making the outputs of all ADCs have the same slope. The slope at this time may be the slope of the output of a specific one of the ADCs, or may be the average value of the slopes of the outputs of all ADCs.

[0129] By correcting the gain, the characteristics of all ADCs, that is, the change in the digital value relative to the light amount, are made consistent with each other. However, on the other hand, the saturation point, that is, the light amount value at which the digital value stops increasing, is inconsistent with each other. In this state, so-called saturation false color occurs. Therefore, as Figure 8 As shown in the lower right figure of , the signal processing circuit 107 performs processing for making the saturation points coincide with each other on the outputs of all ADCs. Through the above series of processing, the signal processing circuit 107 can make the characteristics of all ADCs coincide with each other.

[0130] Note that the above method is only an example of the operation of the signal processing circuit 107. The signal processing circuit 107 may perform operations for making Figure 8 The characteristics of each ADC shown in the leftmost figure are similar to those shown in Figure 8 The various treatments shown in the rightmost figure are consistent with each other. In addition, although Figure 8 The diagram shows the relationship between the light amount and the digital value, but the present disclosure is not limited to this example. For example, the signal processing circuit 107 can perform processing to make the characteristics of each ADC consistent with each other based on the relationship between the voltage value and the digital value of the signal generated based on the light amount in the pixel unit 101.

[0131] The CMOS image sensor 100 first determines whether the correction process should be performed again during imaging (step S109). For example, the criteria for determining whether the correction process should be performed again may be that the voltage value has changed to a predetermined value or more, the temperature has changed to a predetermined value or more, a predetermined time has passed after the previous correction process, or a signal indicating correction is supplied from the outside.

[0132] When it is determined that the correction process should be performed again (step S109, yes), the CMOS image sensor 100 returns to the correction setting process of the above-mentioned step S103 to perform the correction process again. In the re-execution of the correction process during imaging, the CMOS image sensor 100 can return to imaging without waiting. On the other hand, when it is determined that the correction process should not be performed again (step S109, no), the CMOS image sensor 100 reads out the output from the pixel unit 101 through the column readout circuit 103 (step S110), performs signal processing on the read data, and performs digital correction processing using the coefficients obtained by the correction process through the signal processing circuit 107 (step S111).

[0133] Then, the CMOS image sensor 100 determines whether the imaging process has been completed (step S112). When the imaging process has not been completed (step S112, No), the CMOS image sensor 100 returns to the determination of whether the correction process should be performed again in step S109. On the other hand, when the imaging process has been completed (step S112, Yes), the CMOS image sensor 100 switches to the standby mode again (step S113). In addition, when the operation should be completed, the CMOS image sensor 100 performs a predetermined completion setting (step S114) and turns off the power supply.

[0134] Next, an execution example of the correction processing performed by the CMOS image sensor 100 based on the occurrence of an event will be described. Fig. 9 1 is an explanatory diagram showing the operation of the CMOS image sensor 100 according to an embodiment of the present disclosure in chronological order. When the CMOS image sensor 100 is activated as an event, the CMOS image sensor 100 performs a correction process at the time of output of the vertical synchronization signal Vsync. The correction process at the time of activation can be executed for a longer time than the correction process after activation (described below).

[0135] For example, after starting the CMOS image sensor 100, when the voltage inside the CMOS image sensor 100 has changed by more than a predetermined value, the CMOS image sensor 100 performs a correction process corresponding to the voltage change at the output time of the vertical synchronization signal Vsync. In addition, for example, when the temperature inside the CMOS image sensor 100 has changed by more than a predetermined value, the CMOS image sensor 100 performs a correction process corresponding to the temperature change at the output time of the vertical synchronization signal Vsync. The correction at this time can be called "per V correction" and is distinguished from the correction at startup. The execution time of the per V correction can be shorter than the execution time of the correction at startup, and, for example, it can be the execution time of the per V correction to be completed within one frame.

[0136] also, Fig. 9 An example is shown in which every V correction is performed every predetermined number of frames and an example in which every V correction is performed when the temperature has changed by a predetermined value or more.

[0137] Fig.10is an explanatory diagram showing an example of a correction process at startup and a correction process for each V. As a correction process at startup, the CMOS image sensor 100 performs correction multiple times with a set of high voltage values ​​(correction image 1) and low voltage values ​​(correction image 2). On the other hand, since it is assumed that the correction process for each V is performed during the imaging process, the CMOS image sensor 100 performs correction only once with a set of high voltage values ​​(correction image 1) and low voltage values ​​(correction image 2) as the correction process for each V. Specifically, the CMOS image sensor 100 performs correction in a blank area within a frame. By performing the correction process for each V in this manner, the CMOS image sensor 100 can generate an image with reduced noise for subsequent frame images.

[0138] Figure 3A An example is shown in which a DAC capable of outputting an arbitrary voltage is provided as the signal source 104. However, the present disclosure is not limited to this example. The signal source 104 may include a plurality of voltage sources that output a signal of a predetermined voltage. Fig.11 : is an explanatory diagram showing an example of the correction process at startup and the correction process for each V. Fig.11 An example is shown in which two voltage sources are provided as the signal source 104 to output a signal of a predetermined voltage. At the time of the correction process, the switch section 105 switches to output the signal output from each voltage source to the comparator 200. The signals supplied from at least two voltage sources to the comparator 200 can grasp the slope of the relationship between the light amount and the digital value, such as Figure 8 Therefore, the signal processing circuit 107 can correct the change in the analog characteristic of the comparator 200 based on the digital signal output from the comparator 200 at the time of the correction process.

[0139] Similarly, the signal source 104 including a plurality of voltage sources outputting signals of predetermined voltages may be connected to Figure 5 The comparator shown. Fig.12 It is an explanatory diagram showing a configuration example of a comparator. Fig.12 An example is shown in which two voltage sources that output signals of predetermined voltages are provided as the signal source 104 .

[0140] The CMOS image sensor 100 of this embodiment can use a successive approximation register (SAR) ADC as the ADC included in the column readout circuit 103. Also when the SAR ADC is used in the column readout circuit 103, the CMOS image sensor 100 of this embodiment can correct the variation of the analog characteristics of the comparator.

[0141] Fig.13 2 is an explanatory diagram showing a configuration example of a SAR ADC included in the column readout circuit 103 . Fig.13An example is shown in which a DAC capable of outputting an arbitrary voltage is provided as the signal source 104. In addition, a SAR ADC is used as Fig.13 ADC shown. Fig.13 The ADC shown includes a switch section 171 , a capacitor array 172 , a comparator 173 , and a SAR logic circuit 174 .

[0142] Fig.14 2 is an explanatory diagram showing a configuration example of a SAR ADC included in the column readout circuit 103 . Fig.14 An example is shown in which two voltage sources outputting signals of predetermined voltages are provided as the signal source 104. In addition, the SAR ADC is used as Fig.14 The ADC shown in the figure is composed of Fig.13 It is needless to say that the configuration of the SARADC included in the column readout circuit 103 is not limited to Fig.13 and Fig.14 The composition shown.

[0143] The CMOS image sensor 100 according to the present embodiment may have a configuration in which data photoelectrically converted by the pixel portion 101 is read out from the pixel portion 101 not in units of columns but in units of areas. Fig.15 2 is an explanatory diagram showing a configuration example of a CMOS image sensor 100 according to an embodiment of the present disclosure. Fig.15 FIG. 1 shows a configuration example of a CMOS image sensor 100 having a configuration in which a readout circuit 103 is provided to read out data in groups, each group including a plurality of adjacent pixels in a pixel portion 101. Fig.15 In the configuration shown, a signal from a pixel group including a plurality of pixels is output from the pixel portion 101 to the readout circuit 103, and the readout circuit 103 reads out a signal from the pixel portion 101 or reads out a signal from the signal source 104 in units of pixel groups, and outputs the readout signal to the signal processing circuit 107. As an example, Fig.15 The readout circuit 103 is shown, which includes a readout circuit A1 for reading out a signal from the pixel group A1, a readout circuit A2 for reading out a signal from the pixel group A2, a readout circuit B1 for reading out a signal from the pixel group B1, and a readout circuit B2 for reading out a signal from the pixel group B2. Similarly, this configuration can supply the output from the pixel section 101 or the output from the signal source 104 to the column readout circuit 103 by switching the switch section 105.

[0144] <2. Configuration Example of Stacked Solid-State Imaging Device>

[0145] Fig.16 This is a diagram showing an overview of a configuration example of a stacked solid-state imaging device to which the technology of the present disclosure can be applied.

[0146] Fig.16 A shows a schematic configuration example of a non-stacked solid-state imaging device. Fig.16 As shown in FIG. 1A , the solid-state imaging device 23010 includes a bare chip (semiconductor substrate) 23011. A pixel region 23012 in which pixels are arranged in an array, a control circuit 23013 that drives the pixels and performs other various control operations, and a logic circuit 23014 for performing signal processing are mounted on the bare chip 23011.

[0147] Fig.16 B and C show schematic configuration examples of stacked solid-state imaging devices. Fig.16 As shown in FIGS. 1A and 1B , the solid-state imaging device 23020 includes two dies stacked together and electrically connected to each other to constitute a semiconductor chip: a sensor die 23021 ; and a logic die 23024 .

[0148] exist Fig.16 In B, the pixel region 23012 and the control circuit 23013 are mounted on the sensor die 23021, and the logic circuit 23014 including a signal processing circuit that performs signal processing is mounted on the logic die 23024.

[0149] exist Fig.16 In C, the pixel area 23012 is mounted on the sensor die 23021, and the control circuit 23013 and the logic circuit 23014 are mounted on the logic die 23024.

[0150] Fig.17 It is a cross-sectional view showing a first configuration example of a stacked solid-state imaging device 23020.

[0151] A photodiode (PD), a floating diffusion (FD), a Tr (MOS FET) constituting a pixel serving as the pixel region 23012, and a Tr serving as a control circuit 23013 are formed on the sensor die 23021. In addition, a wiring layer 23101 including a plurality of layers (in this example, three layers of wiring 23110) is formed on the sensor die 23021. Note that the control circuit 23013 (Tr) may be formed on the logic chip 23024 instead of on the sensor die 23021.

[0152] Tr constituting the logic circuit 23014 is formed on the logic die 23024. In addition, a wiring layer 23161 including a plurality of layers (in this example, three layers of wiring 23170) is formed on the logic die 23024. In addition, a connection hole 23171 including an insulating film 23172 formed on the inner wall surface is formed on the logic die 23024. A connection conductor 23173 connected to the wiring 23170 and the like is buried inside the connection hole 23171.

[0153] The sensor die 23021 and the logic die 23024 are bonded together with the wiring layers 23101 and 23161 facing each other to form a stacked solid-state imaging device 23020 in which the sensor die 23021 and the logic die 23024 are stacked together. A film 23191 such as a protective film is formed on the bonding surfaces of the sensor die 23021 and the logic die 23024.

[0154] The sensor die 23021 includes a connection hole 23111 that penetrates the sensor chip 23021 from the back side (the side where light enters the PD, the upper side) of the sensor die 23021 and reaches the uppermost layer of the wiring 23170 of the logic die 23024. In addition, the sensor die 23021 includes a connection hole 23121 that is formed near the connection hole 23111 from the back side of the sensor die 23021 to the first layer of the wiring 23110. An insulating film 23112 is formed on the inner wall surface of the connection hole 23111, and an insulating film 23122 is formed on the inner wall surface of the connection hole 23121. In addition, connection conductors 23113 and 23123 are buried inside the connection holes 23111 and 23121, respectively. The connection conductor 23113 and the connection conductor 23123 are electrically connected to each other on the back side of the sensor die 23021. Therefore, the sensor die 23021 and the logic die 23024 are electrically connected to each other via the wiring layer 23101 , the connection via 23121 , the connection via 23111 , and the wiring layer 23161 .

[0155] Fig.18 It is a cross-sectional view showing a second configuration example of the stacked solid-state imaging device 23020.

[0156] In the second configuration example of the solid-state imaging device 23020 , the sensor die 23021 (wiring layer 23101 [wiring 23110 ]) and the logic die 23024 (wiring layer 23161 [wiring 23170 ]) are electrically connected to each other via one connection hole 23211 formed in the sensor die 23021 .

[0157] That is, in Fig.18 In the embodiment, the connection hole 23211 penetrates the sensor die 23021 from the back side of the sensor die 23021 and reaches the uppermost layer of the wiring 23170 of the logic die 23024 and the uppermost layer of the wiring 23110 of the sensor die 23021. The insulating film 23212 is formed on the inner wall surface of the connection hole 23211, and the connection conductor 23213 is buried inside the connection hole 23211. Fig.17 In FIG. 2 , the sensor die 23021 and the logic die 23024 are electrically connected to each other through two connection holes 23111 and 23121. Fig.18In the embodiment, the sensor die 23021 and the logic die 23024 are electrically connected to each other through a connection hole 23211.

[0158] Fig.19 It is a cross-sectional view showing a third configuration example of the stacked solid-state imaging device 23020.

[0159] exist Fig.19 In the solid-state imaging device 23020, a film 23191 such as a protective film is not formed on the bonding surface of the sensor die 23021 and the logic die 23024, which is different from the solid-state imaging device 23020 in which a film 23191 such as a protective film is formed on the bonding surface of the sensor die 23021 and the logic die 23024. Fig.17 The situation is different.

[0160] Fig.19 The solid-state imaging device 23020 can be constructed such that: the sensor die 23021 and the logic die 23024 are stacked together so that the wiring 23110 and the wiring 23170 are in direct contact with each other, and the wiring 23110 and the wiring 23170 are directly bonded by applying a predetermined load while heating.

[0161] Fig. 20 This is a cross-sectional view showing another configuration example of a stacked solid-state imaging device to which the technology of the present disclosure can be applied.

[0162] exist Fig. 20 In the figure, the solid-state imaging device 23401 has a three-layer stacked structure in which three bare chips: a sensor bare chip 23411; a logic bare chip 23412; and a memory bare chip 23413 are stacked together.

[0163] For example, the memory die 23413 includes a storage circuit that stores data temporarily required for signal processing performed in the logic die 23412 .

[0164] Although the logic die 23412 and the memory die 23413 are stacked in this order Fig. 20 However, the logic die 23412 and the memory die 23413 may also be stacked in the opposite order, that is, the memory die 23413 and the logic die 23412 may be stacked under the sensor die 23411 in this order.

[0165] Note that Fig. 20 In the embodiment, the PD serving as the photoelectric conversion portion of the pixel and the source / drain regions of the pixel Tr are formed on the sensor bare chip 23411.

[0166] The gate electrode is formed around the PD via a gate insulating film. The gate electrode and the paired source / drain regions form pixel Tr 23421 and pixel Tr 23422.

[0167] The pixel Tr 23421 adjacent to the PD is a transfer Tr, and one of the paired source / drain regions of the pixel Tr 23421 is an FD.

[0168] In addition, an interlayer insulating film is formed on the sensor die 23411, and a connection hole is formed on the interlayer insulating film. A connection conductor 23431 connected to the pixel Tr 23421 and the pixel Tr 23422 is formed in the connection hole.

[0169] Furthermore, a wiring layer 23433 including multilayer wirings 23432 connected to the respective connection conductors 23431 is formed on the sensor die 23411 .

[0170] In addition, an aluminum pad 23434 used as an electrode for external connection is formed in the lowermost layer of the wiring layer 23433 of the sensor die 23411. That is, in the sensor die 23411, the aluminum pad 23434 is formed at a position closer to the bonding surface 23440 bonded to the logic die 23412 than the wiring 23432. The aluminum pad 23434 is used as one end of a wiring for inputting a signal from the outside or outputting a signal to the outside.

[0171] Furthermore, the sensor die 23411 includes a contact 23441 for electrical connection with the logic die 23412. The contact 23441 is connected to a contact 23451 of the logic die 23412 and is also connected to an aluminum pad 23442 of the sensor die 23411.

[0172] Furthermore, the sensor die 23411 includes a pad hole 23443 formed from the back side (upper side) of the sensor die 23411 to the aluminum pad 23442 .

[0173] The technology according to the present disclosure can be applied to the solid-state imaging device as described above.

[0174] For example, the CMOS image sensor 100 according to the embodiment of the present disclosure may be manufactured as follows: Fig.16 The stacked solid-state imaging device shown in B and C. In this case, for example, the sensor die 23021 may be provided with a pixel portion 101, and the logic die 23024 may be provided with a vertical scanning circuit 102, a column readout circuit 103, a signal source 104, a switch portion 105, a reference voltage generating portion 106, a signal processing circuit 107, and an event control portion 108.

[0175] For example, the technology according to the present disclosure can be applied to an imaging element included in a digital camera, a digital still camera, a mobile phone, a tablet computer, or a personal computer. In addition, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body such as an automobile, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, and a robot. The technology according to the present disclosure applied to the above-mentioned device can reduce the power consumption of the imaging device, and can generate an image with reduced noise caused by the analog characteristics of the column readout circuit.

[0176] Fig.21 1 is an explanatory diagram showing a configuration example of an electronic device 500 to which the CMOS image sensor 100 according to the embodiment of the present disclosure is applied.

[0177] For example, the electronic device 500 is an imaging apparatus such as a digital still camera or a video camera, or a portable terminal device such as a smartphone or a tablet.

[0178] exist Fig.21 , the electronic device 500 includes a lens 501, an imaging element 502, a DSP circuit 503, a frame memory 504, a display unit 505, a recording unit 506, an operation unit 507, and a power supply unit 508. In addition, in the electronic device 500, the DSP circuit 503, the frame memory 504, the display unit 505, the recording unit 506, the operation unit 507, and the power supply unit 508 are connected to each other via a bus 509.

[0179] Figure 1 The CMOS image sensor 100 may be applicable to the imaging element 502 .

[0180] The DSP circuit 503 is a signal processing circuit that processes a signal supplied from the imaging element 502. The DSP circuit 503 outputs image data obtained by processing the signal from the imaging element 502. The frame memory 504 temporarily holds the image data processed by the DSP circuit 503 in units of frames.

[0181] The display section 505 includes, for example, a panel display such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays a moving image or a still image acquired by the imaging element 502. The recording section 506 records image data of the moving image or the still image acquired by the imaging element 502 in a recording medium such as a semiconductor memory or a hard disk.

[0182] The operation unit 507 outputs operation instructions for various functions included in the electronic device 500 according to the user's operation. The power supply unit 508 appropriately supplies various power sources as operation power sources for the DSP circuit 503, frame memory 504, display unit 505, recording unit 506 and operation unit 507 to these power supply objects.

[0183] <3. Conclusion>

[0184] As described above, the embodiments of the present disclosure can provide the CMOS image sensor 100 capable of generating an image with reduced noise caused by the analog characteristics of the column readout circuit.

[0185] The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the technical scope of the present disclosure is not limited to the above examples. It is obvious that a person skilled in the art of the present disclosure can conceive of various modifications or amendments within the scope of the technical ideas described in the claims, and it should be understood that these modifications and amendments also belong to the technical scope of the present disclosure.

[0186] In addition, the effects described in this specification are not restrictive effects, but merely illustrative or exemplary effects. In other words, in addition to or in place of the above effects, the technology according to the present disclosure can also achieve other effects that are obvious to those skilled in the art based on the description of this specification.

[0187] Note that the following configurations also belong to the technical scope of the present disclosure.

[0188] (1) An imaging element, comprising:

[0189] A pixel array, the pixel array comprising a plurality of pixels, each pixel being configured to output a pixel signal through photoelectric conversion;

[0190] a signal output portion configured to output a predetermined signal;

[0191] a switch section configured to output the output from the signal output section or the output based on the pixel signal in a switching manner; and

[0192] An AD conversion processing section is configured to perform AD conversion using the output from the switch section.

[0193] (2) The imaging element according to (1), further including a control section configured to perform control for switching the switch section so that the output from the signal output section is output to the AD conversion processing section when a predetermined condition is satisfied.

[0194] (3) The imaging element according to (2), wherein the control section switches the switch section so as to output the output from the signal output section to the AD conversion processing section in a predetermined cycle.

[0195] (4) The imaging element according to (2) or (3), wherein the control section switches the switch section in response to detection of a predetermined temperature change, thereby outputting the output from the signal output section to the AD conversion processing section.

[0196] (5) The imaging element according to (2) or (3), wherein the control section switches the switch section in response to detection of a predetermined voltage change, thereby outputting the output from the signal output section to the AD conversion processing section.

[0197] (6) The imaging element according to any one of (1) to (5), wherein the signal output section outputs a signal having an arbitrary voltage value.

[0198] (7) The imaging element according to any one of (1) to (5), wherein the signal output section outputs signals of at least two voltage values ​​in a switching manner.

[0199] (8) An imaging element according to any one of (1) to (7), wherein the AD conversion processing unit converts the pixel signal into a digital signal based on a comparison result between a first voltage corresponding to a signal obtained by adding the pixel signal and a reference signal that changes linearly in the opposite direction of the pixel signal and a second voltage used as a reference.

[0200] (9) The imaging element according to (8), wherein the AD conversion processing section includes a comparator configured to perform comparison between the first voltage and the second voltage and output an output signal indicating a comparison result.

[0201] (10) The imaging element according to (9), further including a signal processing circuit configured to perform signal processing on an output from the AD conversion processing section.

[0202] (11) An imaging element according to (10), wherein, in a state in which the switch unit outputs the output from the signal output unit to the AD conversion processing unit, the signal processing circuit performs signal processing for calculating a correction value, wherein the correction value makes the relationship between the light amount and the digital value consistent between the outputs from multiple AD conversion processing units.

[0203] (12) The imaging element according to (11), wherein, in a state where the switch section outputs the output from the pixel array to the AD conversion processing section, the signal processing circuit performs correction processing on the output from the AD conversion processing section using the correction value.

[0204] (13) The imaging element according to any one of (1) to (12), wherein the AD conversion processing section includes at least one comparator, and the comparator includes a first differential transistor and a second differential transistor.

[0205] (14) The imaging element according to (13), wherein a reference signal is input to the first differential transistor, and an output from the signal output section or an output based on the pixel signal is selectively input to the second differential transistor via the switch section.

[0206] (15) The imaging element according to (13) or (14), wherein the first differential transistor is connected to a reference voltage, and the second differential transistor is connected to the first capacitance and the second capacitance.

[0207] (16) The imaging element according to (15), wherein a reference signal is input to the first capacitor, and is selectively input to the second capacitor by switching based on an output of the pixel signal or an output from the signal output section.

[0208] (17) The imaging element according to (16), wherein the reference voltage is a ground voltage.

[0209] (18) An imaging element control method for controlling an imaging element, the imaging element comprising:

[0210] A pixel array, the pixel array comprising a plurality of pixels, each pixel being configured to output a pixel signal through photoelectric conversion;

[0211] a signal output portion configured to output a predetermined signal;

[0212] a switch section configured to output the output from the signal output section or the output based on the pixel signal in a switching manner; and

[0213] An AD conversion processing section configured to perform AD conversion using an output from the switch section, the method comprising:

[0214] Control for switching the switch section is performed so that, when a predetermined condition is satisfied, the output from the signal output section is output to the AD conversion processing section.

[0215] (19) An electronic device comprising:

[0216] an imaging element; and

[0217] a processing unit configured to process a signal output from the imaging element, wherein

[0218] The imaging element comprises:

[0219] A pixel array, the pixel array comprising a plurality of pixels, each pixel being configured to output a pixel signal through photoelectric conversion;

[0220] a signal output portion configured to output a predetermined signal;

[0221] a switch section configured to output the output from the signal output section or the output based on the pixel signal in a switching manner; and

[0222] An AD conversion processing section is configured to perform AD conversion using the output from the switch section.

[0223] Reference numerals list

[0224] 100 CMOS Image Sensor

[0225] 109 pixel drive lines

[0226] 110 vertical signal line

[0227] 121 Comparator

[0228] 122 Counter

[0229] 123 Latch

[0230] 150 pixels

[0231] 151 Photodiode

[0232] 152 Pass transistor

[0233] 154 Amplifier transistor

[0234] 155 Select transistor

[0235] 156 Reset transistor

[0236] 157 Constant current source

[0237] 171 Switch Department

[0238] 172 Capacitor Array

[0239] 173 Comparator

[0240] 174 SAR Logic Circuit

[0241] 200 Comparator

[0242] 201 Differential Amplifier

Claims

1. An imaging element, comprising: A pixel array, the pixel array comprising a plurality of pixels, each pixel being configured to output a pixel signal through photoelectric conversion; a signal output portion configured to output a predetermined signal; a switch section configured to output an output from the signal output section or an output from the pixel array in a switching manner; and an AD conversion processing section connected to an input terminal of a reference signal and connected to the signal output section through the switch section, the AD conversion processing section being configured to perform AD conversion using an output from the switch section, During imaging, the reference signal is supplied to the AD conversion processing unit and the pixel signal is supplied to the AD conversion processing unit via the switch unit, and during correction processing, the predetermined signal from the signal output unit is supplied to the AD conversion processing unit via the switch unit. 2 . The imaging element according to claim 1 , further comprising a control section configured to perform control for switching the switch section so that the output from the signal output section is output to the AD conversion processing section when a predetermined condition is satisfied.

3. The imaging element according to claim 2, wherein: The control section switches the switch section so that the output from the signal output section is output to the AD conversion processing section in a predetermined cycle.

4. The imaging element according to claim 2, wherein: The control section switches the switch section in response to detection of a predetermined temperature change, thereby outputting an output from the signal output section to the AD conversion processing section.

5. The imaging element according to claim 2, wherein: The control section switches the switch section in response to detection of a predetermined voltage change, thereby outputting the output from the signal output section to the AD conversion processing section.

6. The imaging element according to any one of claims 1 to 5, wherein The signal output unit outputs a signal having an arbitrary voltage value.

7. The imaging element according to any one of claims 1 to 5, wherein The signal output unit outputs signals of at least two voltage values ​​in a switching manner.

8. The imaging element according to any one of claims 1 to 5, wherein The AD conversion processing section converts the pixel signal into a digital signal based on a comparison result between a first voltage corresponding to a signal obtained by adding the pixel signal and the reference signal linearly changing in a reverse direction of the pixel signal and a second voltage serving as a reference.

9. The imaging element according to claim 8, wherein: The AD conversion processing section includes a comparator configured to perform comparison between a first voltage and a second voltage and output an output signal indicating a comparison result. 10 . The imaging element according to claim 9 , further comprising a signal processing circuit configured to perform signal processing on an output from the AD conversion processing section.

11. The imaging element according to claim 10, wherein In a state where the switch section outputs the output from the signal output section to the AD conversion processing section, the signal processing circuit performs signal processing for calculating a correction value that makes the relationship between the light amount and the digital value consistent between the outputs from the plurality of AD conversion processing sections.

12. The imaging element according to claim 11, wherein The signal processing circuit performs correction processing on the output from the AD conversion processing section using the correction value in a state in which the switch section outputs the output from the pixel array to the AD conversion processing section.

13. The imaging element according to any one of claims 1 to 5, wherein The AD conversion processing section includes at least one comparator, and the comparator includes a first differential transistor and a second differential transistor.

14. The imaging element according to claim 13, wherein: The reference signal is input to the first differential transistor, and the output from the signal output section or the output from the pixel array is selectively input to the second differential transistor via the switch section.

15. The imaging element according to claim 13, wherein The first differential transistor is connected to a reference voltage, and the second differential transistor is connected to the first capacitor and the second capacitor.

16. The imaging element according to claim 15, wherein The reference signal is input to the first capacitor, and the output from the pixel array or the output from the signal output section is selectively input to the second capacitor by switching.

17. The imaging element according to claim 16, wherein: The reference voltage is a ground voltage.

18. An imaging element control method for controlling an imaging element, the imaging element comprising: A pixel array, the pixel array comprising a plurality of pixels, each pixel being configured to output a pixel signal through photoelectric conversion; a signal output portion configured to output a predetermined signal; a switch section configured to output an output from the signal output section or an output from the pixel array in a switching manner; and an AD conversion processing section connected to an input terminal of a reference signal and connected to the signal output section through the switch section, the AD conversion processing section being configured to perform AD conversion using an output from the switch section, wherein, during imaging, the reference signal is supplied to the AD conversion processing unit and the pixel signal is supplied to the AD conversion processing unit via the switch unit, and during correction processing, the predetermined signal from the signal output unit is supplied to the AD conversion processing unit via the switch unit, The method comprises: Control for switching the switch section is performed so that, when a predetermined condition is satisfied, the output from the signal output section is output to the AD conversion processing section.

19. An electronic device comprising: The imaging element according to any one of claims 1 to 17; and A processing section configured to process a signal output from the imaging element.

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