Micro memory package structure and memory package structure

Abstract

The present invention provides a micro memory packaging structure, which includes a circuit substrate, a first chip, a second chip and a packaging colloid. The circuit substrate has a first surface, a second surface facing away from the first surface and a conductive pattern located on the second surface. The first chip is configured on the first surface. The first chip has a first active surface away from the first surface and a redistribution wiring layer located on the first active surface, and the redistribution wiring layer is electrically connected to the circuit substrate. The second chip is configured on the first active surface and is electrically connected to the redistribution wiring layer. The second chip has a second active surface facing the first active surface. The packaging colloid is configured on the first surface and covers the first chip and the second chip. A memory packaging structure with an antenna is also provided.

Description

Technical Field

[0001] The present invention relates to a memory packaging structure, and in particular to a micro memory packaging structure and a memory packaging structure. Background Art

[0002] With the booming development of the electronics industry, electronic products are also developing towards being light, thin, short, small, highly integrated and multifunctional. Generally speaking, the packaging form is usually wire bonding packaging. However, since this packaging structure requires more wires (such as gold wires), it will require a larger wire bonding space to be reserved and will also increase a lot of material costs. Therefore, how to reduce the overall size and reduce the production cost will become an important topic. Summary of the invention

[0003] The invention provides a micro memory packaging structure, which can reduce the overall size and manufacturing cost.

[0004] The invention provides a memory packaging structure which is integrated with an antenna.

[0005] The micro memory packaging structure of the present invention includes a circuit substrate, a first chip, a second chip and a packaging colloid. The circuit substrate has a first surface, a second surface facing away from the first surface and a conductive pattern located on the second surface. The first chip is configured on the first surface. The first chip has a first active surface away from the first surface and a redistribution wiring layer located on the first active surface, and the redistribution wiring layer is electrically connected to the circuit substrate. The second chip is configured on the first active surface and is electrically connected to the redistribution wiring layer. The second chip has a second active surface facing the first active surface. The packaging colloid is configured on the first surface and covers the first chip and the second chip.

[0006] The memory packaging structure of the present invention includes a circuit substrate, a first chip, a second chip, an antenna and a packaging colloid. The circuit substrate has a first surface, a second surface facing away from the first surface and a conductive pattern located on the second surface. The first chip is configured on the first surface. The first chip has a first active surface away from the first surface and a redistribution wiring layer located on the first active surface, and the redistribution wiring layer is electrically connected to the circuit substrate. The second chip is configured on the first active surface and is electrically connected to the redistribution wiring layer. The second chip has a second active surface facing the first active surface. The antenna is configured on the circuit substrate, and the antenna is located on one side of the first chip. The packaging colloid is configured on the first surface and covers the first chip and the second chip.

[0007] Based on the above, the micro memory package structure of the present invention can reduce the reserved bonding space and thus reduce the overall size, and can reduce the manufacturing cost of bonding materials because the second chip is bonded to the first chip with the second active surface facing the first active surface.

[0008] The memory packaging structure of the present invention is integrated with an antenna, and since the second chip is bonded to the first chip in a manner that the second active surface faces the first active surface, the antenna is configured on the circuit substrate and is located on one side of the first chip. Therefore, the reserved wiring space can be reduced and the clearance area around the antenna can be increased, thereby improving the sensing sensitivity of the antenna.

[0009] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a schematic top view of a micro memory packaging structure according to an embodiment of the present invention;

[0011] Figure 1B yes Figure 1A A schematic cross-sectional view along the section line A-A';

[0012] Figure 2 is a cross-sectional schematic diagram of a memory packaging structure according to another embodiment of the present invention;

[0013] Figure 3 is a cross-sectional schematic diagram of a memory packaging structure according to another embodiment of the present invention;

[0014] Figure 4 yes Figure 2 , Figure 3 A schematic top view of the antenna in FIG.

[0015] Figure 5A is a cross-sectional schematic diagram of a memory packaging structure according to yet another embodiment of the present invention;

[0016] Figure 5B yes Figure 5A Schematic diagram of the top view of the antenna.

[0017] Description of Reference Numerals

[0018] 100a: Micro memory package structure

[0019] 100b, 100c, 100d: Memory packaging structure

[0020] 110: Circuit board

[0021] 110a: first surface

[0022] 110b: Second surface

[0023] 1161, 1162, 1163: Patterned circuit layer

[0024] 118: Conductive pattern

[0025] 120: First Chip

[0026] 120a, 130a: Active surface

[0027] 122: Re-routing the circuit layer

[0028] 130: Second chip

[0029] 132: Conductive part

[0030] 140: Wire

[0031] 150: Passive components

[0032] 160: Encapsulation colloid

[0033] 1701, 1702, 1703: Antenna

[0034] 1704: Antenna substrate

[0035] 1705: Antenna pattern

[0036] R: Insulation area DETAILED DESCRIPTION

[0037] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the accompanying drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0038] Figure 1A 1 is a top view of a memory packaging structure according to an embodiment of the present invention. Figure 1B yes Figure 1A Schematic cross-sectional view along the section line AA' In this embodiment, the size of the micro memory package structure 100a may conform to the size of a Micro Secure Digital (Micro SD) memory card.

[0039] Please also refer to Figure 1A and Figure 1B In this embodiment, the micro memory package structure 100a includes a circuit substrate 110, a first chip 120, a second chip 130 and a packaging colloid 160. The circuit substrate 110 may include a plurality of dielectric layers and inner circuit layers (not shown).

[0040] The dielectric layer can be made of non-organic or organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, benzocyclobutene, etc. The inner circuit layer can be made of copper, aluminum, nickel or other suitable conductive materials. It should be noted that Figure 1B The substrate shown has at least one dielectric layer (not shown), and the number of layers in the circuit substrate 110 can be determined according to product requirements.

[0041] In this embodiment, the circuit substrate 110 has a first surface 110a, a second surface 110b facing away from the first surface 110a, a patterned circuit layer 1161 located on the first surface 110a, and a conductive pattern 118 located on the second surface 110b. The patterned circuit layer 1161 may partially cover the first surface 110a of the circuit substrate 110, so as to be used for subsequent electrical connection between the first chip 120 and the circuit substrate 110. The conductive pattern 118 may be convexly disposed on the second surface 110b. The conductive pattern 118 is, for example, a conductive pad, a contact, or a gold finger.

[0042] In the present embodiment, the first chip 120 is disposed on the first surface 110a. The first chip 120 has a first active surface 120a away from the first surface 110a and a redistribution wiring layer 122 located on the first active surface 120a, and the redistribution wiring layer 122 is electrically connected to the circuit substrate 110. In one embodiment, the redistribution wiring layer 122 may be located only on the first active surface 120a. The first chip 120 is, for example, a memory chip. For example, the memory chip may be a flash memory (NAND Flash).

[0043] In this embodiment, the second chip 130 is disposed on the first active surface 120a and electrically connected to the redistribution wiring layer 122, wherein the second chip 130 has a second active surface 130a facing the first active surface 120a. The second chip 130 can be electrically connected to the redistribution wiring layer 122 by a flip-chip method, so that the second chip 130 is electrically connected to the first chip 120. Figure 1B shown.

[0044] For example, the second chip 130 may further have a plurality of conductive portions 132 located on the second active surface 130a, and the plurality of conductive portions 132 are bonded to the redistribution wiring layer 122. Furthermore, the conductive portions 132 of the second chip 130 may be disposed on the redistribution wiring layer 122, so that the electrical connection between the second chip 130 and the redistribution wiring layer 122 may be achieved.

[0045] In the present embodiment, since the second chip 130 is bonded to the first chip 120 with the second active surface 130a facing the first active surface 120a, the overall size can be reduced and the manufacturing cost can be reduced. Furthermore, the above method can reduce the reserved wiring space and thus reduce the overall size, and can reduce the manufacturing cost of the wiring material. In addition, the redistribution wiring layer 122 can be used for redistribution of circuit signals. Therefore, the second chip 130 with the second active surface 130a facing the first active surface 120a and electrically connected to the first chip 120 through the redistribution wiring layer 122 can shorten the signal conduction path and increase the access speed.

[0046] The conductive portion 132 may be a conductive ball, a conductive bump or a conductive pillar. In one embodiment, the conductive ball, the conductive bump or the conductive pillar may be made of copper, tin, gold, nickel, solder or a combination thereof, but the present invention is not limited thereto. The second chip 130 is, for example, a control chip.

[0047] In one embodiment, the orthographic projection of the first chip 120 on the circuit substrate 110 may overlap the orthographic projection of the second chip 130 on the circuit substrate 110. For example, the orthographic projection range of the second chip 130 on the circuit substrate 110 may be located within the orthographic projection range of the first chip 120 on the circuit substrate 110. Further, the size of the second chip 130 may be smaller than the size of the first chip 120.

[0048] In one embodiment, the micro memory package structure 100a may further include at least one conductive wire 140. The redistribution wiring layer 122 may be electrically connected to the circuit substrate 110 by wire bonding. Further, the redistribution wiring layer 122 may be electrically connected to the patterned circuit layer 1161 on the circuit substrate 110 by the conductive wire 140, but the present invention is not limited thereto, and the connection method of the conductive wire 140 may be adjusted according to actual process requirements.

[0049] In one embodiment, the micro memory package structure 100a may further include at least one passive component 150. The passive component 150 is disposed on the first surface 110a of the circuit substrate 110 and is electrically connected to the circuit substrate 110. The passive component 150 may be located on a portion of the patterned circuit layer 1161. In one embodiment, the orthographic projection of the passive component 150 on the circuit substrate 110 is located between the orthographic projection of the conductive pattern 118 on the circuit substrate 110 and the orthographic projection of the first chip 120 on the circuit substrate 110. The passive component 150 and the conductive pattern 118 may be located on the same side of the first chip 120. Compared to the passive component 150, the conductive pattern 118 may be farther away from the first chip 120.

[0050] In this embodiment, the encapsulation 160 is disposed on the first surface 110a and covers the first chip 120 and the second chip 130. Specifically, the encapsulation 160 covers the side surface of the first chip 120 and the side surface of the second chip 130. Furthermore, the encapsulation 160 may also cover the wires 140 and the passive components 150 on the first surface 110a of the circuit substrate 110. The material of the encapsulation 160 is, for example, epoxy molding compound (EMC).

[0051] It must be noted here that the following embodiments continue to use the component numbers and some contents of the above-mentioned embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the above-mentioned embodiments, and the following embodiments will not be repeated.

[0052] Figure 2 FIG. 1 is a cross-sectional schematic diagram of a memory packaging structure according to another embodiment of the present invention. Figure 2 The memory package structure 100b of this embodiment is similar to the micro memory package structure 100a of the above embodiment, but the difference is that the memory package structure 100b is not limited to a micro memory package structure, and the memory package structure 100b of this embodiment includes an antenna 1701. The antenna 1701 is configured on the circuit substrate 110, and the antenna 1701 is located on one side of the first chip 120. Further, the antenna 1701 can be buried in the circuit substrate 110. In this embodiment, the antenna 1701 can be a part of the inner circuit layer, so that the antenna 1701 can be integrated into the inner circuit layer to further reduce the manufacturing cost.

[0053] In this embodiment, since the second chip 130 is bonded to the first chip 120 with the second active surface 130a facing the first active surface 120a, and the antenna 1701 is configured on the circuit substrate and located on one side of the first chip 120, the pre-reserved wiring space can be reduced to increase the clearance area around the antenna 1701, thereby improving the sensing sensitivity of the antenna 1701.

[0054] For example, the antenna 1701 is a radio frequency identification (RFID) antenna that can be applied to near field communication (NFC). When the memory package structure 100b is applied to near field communication, the area of ​​the clearance area around the antenna 1701 can be increased through the above configuration, thereby increasing the sensing distance of the antenna 1701 and improving the sensing sensitivity of the antenna 1701.

[0055] Here, the clearance area refers to an area without conductive materials, which is used to prevent the electronic components in the external environment from generating electromagnetic interference to the antenna 1701. For example, the circuit substrate 110 may have an insulating region R between the first surface 110a and the second surface 110b, and the insulating region R is located directly above the antenna 1701. In other words, the insulating region R is located between the first surface 110a and the antenna 1701. Therefore, the insulating region R may be a part of the clearance area around the antenna 1701.

[0056] In one embodiment, the passive component 150 may be located between the first chip 120 and the antenna 1701. The passive component 150, the antenna 1701 and the conductive pattern 118 may be located on the same side of the first chip 120. Compared with the passive component 150, the antenna 1701 and the conductive pattern 118 may be farther away from the first chip 120, and the orthographic projection of the antenna 1701 on the circuit substrate 110 overlaps the orthographic projection of the conductive pattern 118 on the circuit substrate 110. In one embodiment, the orthographic projection area of ​​the antenna 1701 on the circuit substrate 110 is smaller than the orthographic projection area of ​​the conductive pattern 118 on the circuit substrate 110, but the present invention is not limited thereto.

[0057] Figure 3 FIG. 1 is a cross-sectional schematic diagram of a memory packaging structure according to another embodiment of the present invention. Figure 3 The memory package structure 100c of this embodiment is similar to the memory package structure 100b of the above embodiment, but the difference is that the antenna 1702 of the memory package structure 100c of this embodiment is configured on the first surface 110a of the circuit substrate 110. The antenna 1702 is electrically connected to the patterned circuit layer 1162. In one embodiment, the antenna 1702 can be a part of the patterned circuit layer 1162, and the encapsulation colloid 160 can cover the antenna 1702.

[0058] Figure 4 yes Figure 2 , Figure 3 A top view of the antenna in Figure 1. Figure 4 , Figure 2 The antenna 1701 and Figure 3 The antenna 1702 may be a helical antenna. The helical antenna may be a near-field antenna or a far-field antenna. The winding method and graphic presentation of this antenna design may adjust the antenna area and appearance design method according to the actual design impedance matching requirements.

[0059] Figure 5A FIG. 4 is a cross-sectional schematic diagram of a memory packaging structure according to another embodiment of the present invention. Figure 5B yes Figure 5A Please also refer to the top view of the antenna in Figure 5A and Figure 5BThe memory package structure 100d of this embodiment is similar to the memory package structure 100c of the above embodiment, and the difference is that the antenna 1703 of the memory package structure 100d of this embodiment includes an antenna substrate 1704 and an antenna pattern 1705 configured on the antenna substrate 1704, and the antenna 1703 can be an array antenna, such as Figure 5B As shown. Specifically, the antenna substrate 1704 is disposed on the first surface 110a of the circuit substrate 110, and the antenna substrate 1704 is electrically connected to the circuit substrate 110. The antenna substrate 1704 may be located on the patterned circuit layer 1163 to be electrically connected to the circuit substrate 110 through the patterned circuit layer 1163. In one embodiment, the antenna 1703 may be combined with the circuit substrate 110 by surface-mount technology (SMT), but the present invention is not limited thereto.

[0060] In summary, the micro memory package structure of the present invention can reduce the reserved wire bonding space and thus reduce the overall size because the second chip is bonded to the first chip with the second active surface facing the first active surface, and can reduce the manufacturing cost of wire bonding materials. Furthermore, the second chip is electrically connected to the first chip with the second active surface facing the first active surface through the redistribution wiring layer, which can shorten the signal conduction path and increase the access speed.

[0061] The memory packaging structure of the present invention is integrated with an antenna, and since the second chip is bonded to the first chip in a manner that the second active surface faces the first active surface, the antenna is configured on the circuit substrate and is located on one side of the first chip. Therefore, the reserved wiring space can be reduced and the clearance area around the antenna can be increased, thereby improving the sensing sensitivity of the antenna.

[0062] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A memory packaging structure, comprising: A circuit substrate having a first surface, a second surface facing away from the first surface, and a conductive pattern on the second surface; A first chip is disposed on the first surface, wherein the first chip has a first active surface away from the first surface and a redistribution wiring layer located on the first active surface, and the redistribution wiring layer is electrically connected to the circuit substrate; A second chip is disposed on the first active surface and electrically connected to the redistribution wiring layer, wherein the second chip has a second active surface facing the first active surface; An antenna, configured on the circuit substrate, and located on one side of the first chip; as well as The packaging colloid is disposed on the first surface and covers the first chip and the second chip. 2 . The memory package structure according to claim 1 , wherein the antenna is embedded in the circuit substrate. 3 . The memory packaging structure according to claim 2 , wherein the circuit substrate further has an insulating region located between the first surface and the second surface, and the insulating region is located directly above the antenna, and the insulating region is located between the first surface and the antenna. 4 . The memory package structure according to claim 1 , wherein the antenna is disposed on the first surface of the circuit substrate. 5 . The memory package structure according to claim 4 , wherein the circuit substrate further has a patterned circuit layer located on the first surface, and the antenna is a part of the patterned circuit layer. 6 . The memory package structure according to claim 4 , wherein the circuit substrate further has a patterned circuit layer located on the first surface, and the antenna is electrically connected to the patterned circuit layer. 7 . The memory package structure according to claim 4 , wherein the encapsulant covers the antenna.

8. The memory package structure according to claim 4, wherein the antenna comprises an antenna substrate and an antenna pattern configured on the antenna substrate, wherein the antenna substrate is configured on the first surface of the circuit substrate, and the antenna substrate is electrically connected to the circuit substrate.

9. The memory package structure according to claim 1, further comprising: At least one passive component is disposed on the first surface of the circuit substrate and located between the first chip and the antenna. 10 . The memory package structure according to claim 1 , wherein an orthographic projection of the first chip on the circuit substrate overlaps an orthographic projection of the second chip on the circuit substrate. 11 . The memory package structure according to claim 1 , wherein the orthographic projection range of the second chip on the circuit substrate is located within the orthographic projection range of the first chip on the circuit substrate. 12 . The memory packaging structure according to claim 1 , wherein the second chip further has a plurality of conductive portions located on the second active surface, and the plurality of conductive portions are bonded to the redistribution wiring layer.

13. The memory package structure according to claim 1, further comprising: At least one conductive wire, the redistribution circuit layer is electrically connected to the circuit substrate through the conductive wire. 14 . The memory package structure according to claim 13 , wherein the circuit substrate further has a patterned circuit layer located on the first surface, and the redistribution circuit layer is electrically connected to the patterned circuit layer through the conductive wire. 15 . The memory package structure according to claim 1 , wherein the first chip is a memory chip and the second chip is a control chip.

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