Method for forming semiconductor structure
By forming a multi-layer dielectric and metal structure on the semiconductor substrate and controlling the size of the bottom of the through hole by using the positioning effect of the second dielectric layer, the short circuit problem caused by the expansion of the through hole is solved and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202010022609.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-01-09
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2040-01-09
AI Technical Summary
The existing self-aligning through-hole process can easily cause the through-hole to expand when forming the through-hole, resulting in bridges and short circuits between the conductive plug and the connected metal wire.
A first dielectric layer is formed on a semiconductor substrate, and several discrete first metal layers are formed thereon. Then a second dielectric layer is formed between the first metal layers. After oxidation treatment, a metal oxide layer is formed, and then thereafter, it is placed. The third dielectric layer is formed on the surface, and through holes are formed by etching, and the bottom size of the through holes is controlled by the positioning of the second dielectric layer to avoid short circuits.
By controlling the size of the bottom of the through-hole, short circuit between the conductive plug and the connected metal wire is avoided, and the performance reliability of the semiconductor structure is improved.
Smart Images
Figure CN113097127B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits (ULSI), the internal circuit density is getting higher and higher, and the number of components contained is increasing, so that the surface of the chip cannot provide enough area to make the required interconnects. In order to meet the increased demand for interconnects after the components are reduced, the design of more than two layers of multi-layer metal interconnects using through holes has become a method that must be adopted in ultra-large-scale integrated circuit technology.
[0003] However, as semiconductor process nodes continue to decrease, metal interconnects in semiconductor devices become increasingly dense, and the critical dimensions (CD) of interconnects become increasingly smaller. In order to expand the process window of photolithography, a self-aligned via (SAV) process can be used when forming the through hole. However, when the through hole is formed by the existing self-aligned process, the through hole will be enlarged, which will cause the conductive plug to bridge with the metal wires adjacent to the lower metal wires connected to it after the conductive plug is filled with metal in the through hole, resulting in a short circuit. Summary of the invention
[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can limit the expansion of through holes and avoid the short circuit problem between the through holes and metal lines.
[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, forming a first dielectric layer on the semiconductor substrate; forming a plurality of discrete first metal layers in the first dielectric layer, wherein the top of the first metal layer is higher than the top surface of the first dielectric layer; forming a second dielectric layer on the first dielectric layer between adjacent first metal layers; oxidizing the first metal layer to form a metal oxide layer; forming a third dielectric layer on the surface of the second dielectric layer and the metal oxide layer; and etching the third dielectric layer until the metal oxide layer is exposed to form a through hole.
[0006] Optionally, a method of forming the second dielectric layer on the first dielectric layer includes atomic layer deposition or chemical vapor deposition.
[0007] Optionally, the material of the second dielectric layer includes aluminum oxide, aluminum nitride, boron nitride, tin dioxide, or titanium dioxide.
[0008] Optionally, the method further includes: forming a cap layer on the first dielectric layer, wherein the first metal layer is located within the cap layer and the first dielectric layer, and a top of the first metal layer is flush with a top of the cap layer.
[0009] Optionally, before forming the second dielectric layer, the cap layer is removed by etching.
[0010] Optionally, before forming the second dielectric layer, a self-assembled monolayer is further formed on the first metal layer.
[0011] Optionally, the method of forming the self-assembled monolayer is atomic layer deposition.
[0012] Optionally, the material of the self-assembled monolayer is a carbon-containing compound.
[0013] Optionally, the method for etching the third dielectric layer includes: forming a mask layer on the surface of the third dielectric layer, the mask layer having an opening, the opening exposing the third dielectric layer on the top of the metal oxide layer; etching the third dielectric layer along the opening until the metal oxide layer is exposed.
[0014] Optionally, the material of the mask layer includes titanium nitride, boron nitride, aluminum nitride or tantalum nitride.
[0015] Optionally, the method for etching the third dielectric layer is dry etching, and the process parameters of the dry etching include: the gas used includes CHF 3 , C 4 F 6 , O 2 , Ar, C 4 F 2 and H 2 , where CHF 3 The gas flow rate is 10~300sccm, C 4 F 6 The gas flow rate is 10 to 300 sccm, O 2 The gas flow rate is 0 to 100 sccm, the Ar gas flow rate is 50 to 500 sccm, and the C 4 F 2 The gas flow rate is 20-100 sccm, H 2 The gas flow rate is 0 to 100 sccm, the chamber pressure is 5 to 100 mTorr, and the radio frequency power is 100 to 1000 watts.
[0016] Optionally, the material of the first dielectric layer is a low-K dielectric material or an ultra-low-K dielectric material; and the material of the third dielectric layer is a low-K dielectric material or an ultra-low-K dielectric material.
[0017] Optionally, after forming the through hole, the method further includes: removing the metal oxide layer at the bottom of the through hole to expose the surface of the first metal layer; and filling the through hole with a second metal layer to form a conductive plug connected to the first metal layer.
[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0019] Before etching to form a through hole, a second dielectric layer is formed on the first dielectric layer between adjacent first metal layers. When etching is used to form the through hole, the second dielectric layer can control the bottom size of the through hole, limit the expansion of the through hole, and avoid short circuits between the through hole and the adjacent metal layers of the connected first metal layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figures 1 to 4 is a structural schematic diagram of a method for forming a semiconductor structure according to an embodiment of the prior art;
[0021] Figures 5 to 12 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0022] As known from the background art, the existing self-aligned via process may cause the via enlargement problem.
[0023] Figures 1 to 4 It is a structural schematic diagram of a method for forming a semiconductor structure according to an embodiment of the prior art.
[0024] refer to Figure 1 , providing a semiconductor structure, the semiconductor structure comprising a first interlayer dielectric layer 100, a covering layer 110 located on the surface of the first interlayer dielectric layer 100, and a first metal layer 120 located within the first interlayer dielectric layer 100 and the covering layer 110, wherein the top of the first metal layer 120 is lower than the top surface of the first interlayer dielectric layer 100.
[0025] refer to Figure 2 , a barrier layer 121 and an etch stop layer 122 are sequentially formed on the surface of the first metal layer 120 , and the barrier layer 121 and the etch stop layer 122 also cover the surface of the cover layer 110 .
[0026] refer to Figure 3, a second interlayer dielectric layer 130 is formed on the etch barrier layer 122, a patterned hard mask layer 140 is formed on the second interlayer dielectric layer 130, and the second interlayer dielectric layer 130 is etched to the etch stop layer 122 using the patterned hard mask layer 140 as a mask, and then the etch stop layer 122 and the barrier layer 121 are continuously etched until the surface of the first metal layer 120 is exposed to form a through hole 150.
[0027] refer to Figure 4 , removing the patterned hard mask layer 140 , forming a second metal layer 160 in the through hole 150 , and connecting the second metal layer 160 to the first metal layer 120 .
[0028] The inventors have discovered that when the above method is used to form a through hole, if the opening of the patterned hard mask layer 140 is too large, it is easy to cause the size of the through hole formed by etching to be too large. When the spacing between metal layers becomes smaller and smaller, the bottom size of the through hole is too large, which is easy to bridge with the metal layer below, resulting in a short circuit, which is not conducive to the performance of the semiconductor structure.
[0029] In order to solve the above problems, the inventors have provided a method for forming a semiconductor structure after research, wherein a second dielectric layer is formed on the first dielectric layer between adjacent first metal layers, and the second dielectric layer and a third dielectric layer to be subsequently etched have a high selectivity. When etching the third dielectric layer to form a through hole, since the second dielectric layer has a positioning function on both sides of the first metal layer, the through hole can be formed in a completely self-aligned manner, and the size of the bottom of the through hole is limited to avoid the occurrence of a short circuit.
[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0031] Figures 5 to 12 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.
[0032] refer to Figure 5 , providing a semiconductor substrate (not shown), and forming a first dielectric layer 200 on the semiconductor substrate.
[0033] The material of the first dielectric layer 200 is an ultra-low K dielectric material (an ultra-low K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.5) or a low K dielectric material (a low K dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.5 and less than 3.9). When the material of the first dielectric layer 200 is a low K dielectric material or an ultra-low K dielectric material, the material of the first dielectric layer 200 is SiOH, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-phosphorus-doped silicon dioxide), hydrogenated silsesquioxane (HSQ, (HSiO 1.5 ) n ) or methylsilsesquioxane (MSQ, (CH3SiO 1.5 ) n In this embodiment, the material of the first dielectric layer 200 is an ultra-low K dielectric material, and the ultra-low K dielectric material is SiCOH. Using the ultra-low K dielectric material as the dielectric layer can reduce the RC delay of the metal interconnect structure.
[0034] Continue to refer Figure 5 , a plurality of discrete first metal layers 300 are formed in the first dielectric layer 200 , and the top of the first metal layer 300 is higher than the top surface of the first dielectric layer 200 .
[0035] In this embodiment, the method for forming the first metal layer 300 includes: forming a plurality of parallel grooves in the first dielectric layer 200 by photolithography and etching processes; and then filling the grooves with metal to form the first metal layer 300 .
[0036] The material of the first metal layer 300 includes copper or cobalt. In this embodiment, the material of the first metal layer 300 is copper.
[0037] It should be noted that, before forming the first metal layer 300, a cap layer 210 is also formed on the first dielectric layer 200. The cap layer 210 and the first dielectric layer 200 are subsequently etched to form the first metal layer 300 within the cap layer 210 and the first dielectric layer 200, and the top of the first metal layer 300 is flush with the top of the cap layer 210.
[0038] In this embodiment, the material of the capping layer 210 is silicon carbide; in other embodiments, the material of the capping layer 210 may also be an oxide layer with a higher K value, such as an oxide with a relative dielectric constant of about 4.
[0039] After the first metal layer 300 is formed, a second dielectric layer is formed on the first dielectric layer 200 between adjacent first metal layers 300 .
[0040] refer to Figure 6 It should be noted that, in this embodiment, the cap layer 210 is removed before forming the second dielectric layer 400. The reason for removing the cap layer 210 is that the cap layer 210 is not dense enough, which will affect the time-dependent breakdown of the formed semiconductor structure. Removing the cap layer 210 and subsequently re-forming the second dielectric layer with better density at the position of the cap layer 210 can enhance the time-dependent breakdown of the semiconductor structure.
[0041] In this embodiment, the method for removing the cap layer 210 is a plasma etching process.
[0042] Continue to refer Figure 6 After removing the cap layer 210 and before forming the second dielectric layer, a self-assembled monolayer 310 is first formed on the first metal layer 300 .
[0043] In this embodiment, the self-assembled monolayer 310 is selectively deposited on the surface of the first metal layer 300, but not on the surface of the first dielectric layer 200. When the second dielectric layer is subsequently formed on the first dielectric layer 200, it plays a role in protecting the first metal layer 300 and avoiding damage to the first metal layer 300, thereby affecting the performance of the interconnection structure.
[0044] In this embodiment, the method of forming the self-assembled monolayer 310 is atomic layer deposition.
[0045] In this embodiment, the material of the self-assembled monolayer 310 is a carbon-containing non-metallic compound.
[0046] refer to Figure 7 , a second dielectric layer 400 is formed on the first dielectric layer 200 between adjacent first metal layers 300 .
[0047] In this embodiment, the method for forming the second dielectric layer 400 on the first dielectric layer 200 is atomic layer deposition. In other embodiments, the second dielectric layer may be formed by chemical vapor deposition or plasma chemical vapor deposition.
[0048] In this embodiment, the second dielectric layer 400 grows in a directional manner and is only formed on the surface of the first dielectric layer 200 , but does not grow on the surface of the self-assembled monolayer 310 .
[0049] In this embodiment, the material of the second dielectric layer 400 is aluminum oxide; the reason for selecting aluminum oxide is that aluminum oxide and the subsequently formed third dielectric layer have a higher etching selectivity ratio, and when the third dielectric layer is subsequently etched to form a through hole, the aluminum oxide will not be damaged, thereby ensuring the size of the bottom of the through hole.
[0050] In other embodiments, the material of the second dielectric layer 400 may also be aluminum nitride, boron nitride, tin dioxide, or titanium dioxide.
[0051] In this embodiment, the top of the second dielectric layer 400 is higher than the top surface of the first metal layer 300 .
[0052] In this embodiment, the second dielectric layer 400 is formed. On the one hand, the second dielectric layer 400 has a high density, which can enhance the time-dependent breakdown of the semiconductor structure, thereby improving the performance of the semiconductor structure. On the other hand, the second dielectric layer 400 is located between adjacent first metal layers 300, and plays a positioning role in the subsequent etching of the third dielectric layer. It can self-align the etching to form a through hole, thereby reducing the position deviation between the through hole and the first metal layer. On the other hand, the size of the bottom of the through hole is also limited. Even when the etching process window is large, the bottom size of the through hole formed by etching is fixed, thereby avoiding bridging between the subsequently formed through hole and the first metal layer that does not need to be connected, thereby avoiding short circuit.
[0053] refer to Figure 8 After forming the second dielectric layer 400 , the self-assembled monolayer 310 is removed.
[0054] In this embodiment, an ashing process is used to remove the self-assembled monolayer 310. The process parameters of the ashing process include: the gas used includes oxygen, the gas flow rate of oxygen is 50-1000 sccm, the chamber pressure is 0.5-5 Torr, and the source power is 500-3000 watts.
[0055] Continue to refer Figure 8 After removing the self-assembled monolayer 310 , the first metal layer 300 is oxidized to form a metal oxide layer 320 on the surface of the first metal layer 300 .
[0056] In this embodiment, the metal oxide layer 320 serves to protect the first metal layer 300 and prevent the first metal layer from being damaged when the third dielectric layer is subsequently etched to form a through hole, and can also serve as an etching stop layer.
[0057] In this embodiment, an isotropic plasma oxidation process is used to form the metal oxide layer 320. The metal oxide layer formed by the plasma oxidation process has a strong bonding force with the metal substrate and better compactness, which is beneficial to improving the performance of the semiconductor structure.
[0058] The material of the metal oxide layer 320 depends on the material of the first metal layer 300. In this embodiment, the metal oxide layer 320 is copper oxide; in other embodiments, the metal oxide layer 320 may also be cobalt oxide.
[0059] refer to Fig. 9 , a third dielectric layer 500 is formed on the surfaces of the second dielectric layer 400 and the metal oxide layer 320 .
[0060] The material of the third dielectric layer 500 is an ultra-low K dielectric material or a low K dielectric material. When the material of the third dielectric layer 500 is a low K dielectric material or an ultra-low K dielectric material, the material of the third dielectric layer 500 is SiOH, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-phosphorus-doped silicon dioxide), hydrogenated silsesquioxane (HSQ, (HSiO 1.5 ) n ) or methylsilsesquioxane (MSQ, (CH3SiO 1.5 ) n In this embodiment, the material of the third dielectric layer 500 is an ultra-low-K dielectric material, and the ultra-low-K dielectric material is SiCOH.
[0061] In this embodiment, the third dielectric layer 500 is subsequently etched to form a through hole.
[0062] In this embodiment, the steps of forming the through hole specifically include:
[0063] Continue to refer Fig. 9 A mask layer 510 is formed on the surface of the third dielectric layer 500 , wherein the mask layer 510 has an opening 511 , and the opening 511 exposes the third dielectric layer 500 on the top of the metal oxide layer 320 .
[0064] In this embodiment, the position corresponding to the opening 511 is the position where a through hole is subsequently formed, and the opening 511 exposes the third dielectric layer 500 corresponding to the position of the first metal layer 300 .
[0065] In this embodiment, the mask layer 510 is formed by chemical vapor deposition. In other embodiments, the mask layer 510 may be formed by physical vapor deposition or atomic layer deposition.
[0066] In this embodiment, the material of the mask layer 510 is titanium nitride; in other embodiments, the material of the mask layer 510 may also be one or more of aluminum nitride, boron nitride or tantalum nitride.
[0067] refer to Fig.10 , the third dielectric layer 500 is etched along the opening 511 until the metal oxide layer 320 is exposed, thereby forming a through hole 600 .
[0068] Since the second dielectric layer 400 and the third dielectric layer 500 have a high etching selectivity, the second dielectric layer 400 will not be affected when etching the third dielectric layer 500, so the bottom size of the through hole 600 is limited by the adjacent second dielectric layer 400, and the bottom size of the through hole 600 is the spacing between the adjacent second dielectric layers 400 (shown as d in the figure). Due to the existence of the second dielectric layer 400, the bottom size of the through hole is fixed, and the etching process window can be appropriately increased without affecting the bottom size of the through hole.
[0069] In this embodiment, the method for etching the third dielectric layer 500 is dry etching, and the process parameters of the dry etching include: the gas used includes CHF 3 , C 4 F 6 , O 2 , Ar, C 4 F 2 and H 2 , where CHF 3 The gas flow rate is 10~300sccm, C 4 F 6 The gas flow rate is 10-300 sccm, O 2 The gas flow rate is 0-100 sccm, the Ar gas flow rate is 50-500 sccm, and the C 4 F 2 The gas flow rate is 20-100 sccm, H 2 The gas flow rate is 0-100 sccm, the chamber pressure is 5-100 mTorr, and the RF power is 100-1000 watts.
[0070] refer to Fig.11 After the through hole 600 is formed, the metal oxide layer 320 at the bottom of the through hole 600 is removed to expose the surface of the first metal layer 300.
[0071] In this embodiment, the method for removing the metal oxide layer 320 is a wet etching process, and the process parameters of the wet etching process include: the etching solution used is a mixed solution of sulfuric acid and hydrogen peroxide.
[0072] In this embodiment, the metal oxide layer 320 at the bottom of the through hole 600 is removed in order to make the second metal layer contact and connect with the first metal layer 300 when the second metal layer is subsequently filled in the through hole 600.
[0073] In this embodiment, a wet etching process is also used to remove the mask layer 510 .
[0074] refer to Fig.12After removing the metal oxide layer 320 , the through hole 600 is filled with the second metal layer 610 to form a conductive plug connected to the first metal layer 300 .
[0075] In this embodiment, the method for forming the conductive plug includes: filling the through hole 600 with a second metal material layer, the second metal material layer covering the side wall and the bottom of the through hole 600 and the surface of the third dielectric layer 500; chemically mechanically polishing the second metal material layer to make the top of the second metal material layer flush with the top surface of the third dielectric layer 500 to form the second metal layer 610, and the second metal layer 610 is in contact and connected with the first metal layer 300.
[0076] In this embodiment, the second metal material layer is filled in the through hole 600 by electrochemical plating.
[0077] The material of the second metal layer 610 can be copper, cobalt, tungsten or platinum. In this embodiment, the second metal layer 610 is copper.
[0078] In this embodiment, the conductive plug, i.e., the second metal layer 610, has the second dielectric layer 400 on both sides, which, on the one hand, fixes the size of the bottom of the conductive plug, and on the other hand, isolates the conductive plug from the metal layer adjacent to the first metal layer to which it is connected, thereby avoiding short circuit and improving the performance reliability of the semiconductor structure.
[0079] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate; forming a plurality of discrete first metal layers in the first dielectric layer, wherein the tops of the first metal layers are higher than the top surface of the first dielectric layer; forming a self-assembled monolayer on the first metal layer; forming a second dielectric layer on the first dielectric layer between adjacent first metal layers, wherein the top of the second dielectric layer is higher than the top surface of the first metal layer; removing the self-assembled monolayer; performing oxidation treatment on the first metal layer to form a metal oxide layer; forming a third dielectric layer on the surfaces of the second dielectric layer and the metal oxide layer; The third dielectric layer is etched until the metal oxide layer is exposed to form a through hole.
2. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the second dielectric layer on the first dielectric layer includes atomic layer deposition or chemical vapor deposition.
3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second dielectric layer includes aluminum oxide, aluminum nitride, boron nitride, tin dioxide, or titanium dioxide.
4. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A cap layer is formed on the first dielectric layer, the first metal layer is located within the cap layer and the first dielectric layer, and a top of the first metal layer is flush with a top of the cap layer.
5. The method for forming a semiconductor structure according to claim 4, wherein: Before forming the second dielectric layer, the cap layer is removed by etching.
6. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the self-assembled monolayer is atomic layer deposition.
7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the self-assembled monolayer is a carbon-containing compound.
8. The method for forming a semiconductor structure according to claim 1, wherein: The method of etching the third dielectric layer comprises: forming a mask layer on the surface of the third dielectric layer, wherein the mask layer has an opening, and the opening exposes the third dielectric layer on the top of the metal oxide layer; The third dielectric layer is etched along the opening until the metal oxide layer is exposed.
9. The method for forming a semiconductor structure according to claim 8, wherein: The material of the mask layer includes titanium nitride, boron nitride, aluminum nitride or tantalum nitride.
10. The method for forming a semiconductor structure according to claim 1, wherein: The method for etching the third dielectric layer is dry etching, and the process parameters of the dry etching include: the gases used include CHF3, C4F6, O2, Ar, C4F2 and H2, wherein the flow rate of CHF3 gas is 10-300sccm, the flow rate of C4F6 gas is 10-300sccm, the flow rate of O2 gas is 0-100sccm, the flow rate of Ar gas is 50-500sccm, the flow rate of C4F2 gas is 20-100sccm, the flow rate of H2 gas is 0-100sccm, the chamber pressure is 5-100 mTorr, and the RF power is 100-1000 watts.
11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dielectric layer is a low-K dielectric material or an ultra-low-K dielectric material; the material of the third dielectric layer is a low-K dielectric material or an ultra-low-K dielectric material.
12. The method for forming a semiconductor structure according to claim 1, wherein: After forming the through hole, the method further comprises: removing the metal oxide layer at the bottom of the through hole to expose the surface of the first metal layer; The through hole is filled with a second metal layer to form a conductive plug connected to the first metal layer.